diff --git a/Tests/isa/CPrograms/Benchmarks/Memaccess/build.sh b/Tests/isa/CPrograms/Benchmarks/Memaccess/build.sh new file mode 100644 index 0000000..1208a27 --- /dev/null +++ b/Tests/isa/CPrograms/Benchmarks/Memaccess/build.sh @@ -0,0 +1,13 @@ +scp ../../start.S home-1:/home/akilan/cheri/output/sdk/bin/ +# scp main.c home-1:/home/akilan/cheri/output/sdk/bin/ +scp ../../malloc.c home-1:/home/akilan/cheri/output/sdk/bin/ + +scp memaccess.c home-1:/home/akilan/cheri/output/sdk/bin/ + +ssh home-1 'cd /home/akilan/cheri/output/sdk/bin/ && ./clang --target=riscv64-unknown-elf -march=rv64gcxcheri -mabi=lp64d -nostdlib -nostartfiles -fno-builtin-malloc -mcmodel=medany -Wl,-Ttext=0x80000000 -o testC start.S malloc.c memaccess.c' + +# ssh home-1 'cd /home/akilan/cheri/output/sdk/bin/ && ./llvm-objdump -d testC' + +scp home-1:/home/akilan/cheri/output/sdk/bin/testC ../../../ + + diff --git a/Tests/isa/CPrograms/Benchmarks/Memaccess/memaccess.c b/Tests/isa/CPrograms/Benchmarks/Memaccess/memaccess.c new file mode 100644 index 0000000..b4f0cf6 --- /dev/null +++ b/Tests/isa/CPrograms/Benchmarks/Memaccess/memaccess.c @@ -0,0 +1,364 @@ +/* +memaccesstest.c +Author Alex Bordei at bigstep +All rights reserved. +*/ + +// source: https://github.com/bigstepinc/memaccesstest/tree/master + +// #include +#include +#include +#include +// #include +// #include +// #include "config.h" + +// #ifndef __MACH__ +// #include +// #else +// #include +// #endif + +// #include "malloc.h" + +// #define malloc MALLOCCHERI +// #define free FREECHERI + +#define NPAD 7 +#define MIN_WSS sizeof(struct l) +#define MAX_WSS 70 + +void free(void * __capability ptr); +void * __capability malloc(size_t size); + + + +// struct l{ +// struct l *n; +// struct l *p; +// long int pad[NPAD-1]; + +// }; + +struct l{ + struct l * __capability n; + struct l * __capability p; + long int pad[NPAD-1]; +}; + +// uint64_t rand64() +// { +// // Combin 4 parts of low 16-bit of each rand() +// uint64_t R0 = (uint64_t)random() << 48; +// uint64_t R1 = (uint64_t)random() << 48 >> 16; +// uint64_t R2 = (uint64_t)random() << 48 >> 32; +// uint64_t R3 = (uint64_t)random() << 48 >> 48; +// return R0 | R1 | R2 | R3; +// }; + +#ifdef DEBUG +// void print_ll_lin(struct l *root,unsigned long working_set_size) +// { +// struct l *current=root->n; +// unsigned long count; +// printf("0"); +// count=0; +// while(current!=root) +// { +// // printf("->%ld",current-root); +// current=current->n; +// count++; +// if(count>working_set_size/sizeof(struct l)) +// { +// // printf("Error:cycle!"); +// break; +// } + +// } +// // printf("\n"); +// } +// void print_ll_lin_back(struct l *root,unsigned long working_set_size) +// { +// struct l *current=root->p; +// unsigned long count; +// printf("0"); +// count=0; +// while(current!=root) +// { +// // printf("->%ld",current-root); +// current=current->p; +// count++; +// if(count>working_set_size/sizeof(struct l)) +// { +// // printf("Error:cycle!"); +// break; +// } + +// } +// printf("\n"); +// } +// void print_ll(struct l *root,unsigned long working_set_size) +// { +// unsigned long i; +// for(i=0;i<(working_set_size/sizeof(struct l));i++) +// printf("DEBUG: %ld<-%ld->%ld\n",(root+i)->p-root,i,((root+i)->n)-root); +// printf("DEBUG "); +// print_ll_lin(root, working_set_size); +// printf("DEBUG "); +// print_ll_lin_back(root, working_set_size); + +// } +#endif + +// void build_sequencial_ll(struct l * root, long working_set_size) +void build_sequencial_ll(struct l * __capability root, long working_set_size) +{ + + unsigned long i; + + struct l * __capability current; + + + for(i=0;i<(working_set_size/sizeof(struct l));i++) + { + current=root+i; + if(i==(working_set_size/sizeof(struct l)-1)) + current->n=root; + else + current->n=current+1; + if(i==0) + current->p=root+working_set_size/sizeof(struct l)-1; + else + current->p=current-1; + } +} + +// void build_random_ll(struct l *root, long working_set_size) +// { + +// unsigned long i; + + +// struct l *a; +// struct l *b; +// struct l *oldan; +// struct l *oldbn; +// struct l *oldap; +// struct l *oldbp; + +// unsigned long rnd; +// unsigned long tries; + +// build_sequencial_ll(root, working_set_size); + +// //construct the array of elements +// //link the list to the next element in the array + +// for(i=1;i<(working_set_size/sizeof(struct l)-1);i++) +// { + +// a=(root+i); +// b=a; +// tries=5; +// while((b==a || b==root) && tries) +// { +// rnd=rand64() % (working_set_size/sizeof(struct l)-1); +// b=root+rnd; +// tries--; +// } +// if(!tries) +// continue; + + +// oldan=a->n; //a->n is lost along the way +// oldbn=b->n; //b->n is lost along the way +// oldap=a->p; //a->p is lost along the way +// oldbp=b->p; //b->p is lost along the way + +// a->p->n=b; +// b->p->n=a; + +// if(b!=oldan) +// { +// b->n=oldan; +// oldan->p=b; +// } +// else +// { +// b->n=a; +// a->p=b; +// } + +// if(a!=oldbn) +// { +// a->n=oldbn; +// oldbn->p=a; +// } +// else +// { +// a->n=b; +// b->p=a; +// } + +// if(b!=oldap) +// b->p=oldap; +// else +// b->p=a; + +// if(a!=oldbp) +// a->p=oldbp; +// else +// a->p=b; + + +// #ifdef DEBUG +// printf("DEBUG: Round i=%ld\n",i); +// printf("DEBUG: A=%ld B=%ld\n",a-root,b-root); +// print_ll(root, working_set_size); +// #endif +// } + +// } + + + +struct thread_start_data +{ + struct l * __capability root; + unsigned long working_set_size; + int thread_index; +}; + +void * walk(void * __capability param) +{ + + struct thread_start_data * __capability data=param; + unsigned long start,end; + + + struct l * __capability root=data->root; + // struct l* current=root->n; + struct l * __capability current = root->n; + + // #ifdef __MACH__ + // start=mach_absolute_time(); + // #else + // struct timespec ts; + // clock_gettime(CLOCK_MONOTONIC_RAW,&ts); + // start=ts.tv_nsec; + // #endif + + + ///////////////////////////////////// + //traverse the linked list + + while(current!=root) + { +// #ifdef ADDTEST +// current->pad[0]+=current->n->pad[0]; +// #endif + +// #ifdef INCTEST +// current->pad[0]++; +// #endif + current=current->n; + } + + + ///////////////////////////////////// +// #ifdef __MACH__ +// end=mach_absolute_time(); +// #else +// clock_gettime(CLOCK_MONOTONIC_RAW,&ts); +// end=ts.tv_nsec; +// #endif + + + // printf("%d,%ld,%ld,%ld\n",data->thread_index,data->working_set_size, end-start, data->working_set_size/sizeof(struct l)); + + // free(data); + return NULL; +} + +int main(void) +{ +// clock_t tic = clock(); +// INITREGULARALLOC(); +//#ifdef DEBUG + // printf("DEBUG:sizeof(struct l)=%ld\n",sizeof(struct l)); +// #endif + struct l * __capability root; + unsigned long working_set_size; + int i; + // struct thread_start_data *tdata; + struct thread_start_data * __capability tdata; + + + // pthread_t threads[NTHREADS]; + + root=malloc(MAX_WSS/sizeof(struct l) * sizeof(struct l)); + + for(working_set_size=MIN_WSS;working_set_size0 +// for(i=0;ithread_index=i; +// tdata->root=root; +// tdata->working_set_size=working_set_size; +// pthread_create(&threads[i], NULL, walk, (void*) tdata); +// } + +// for(i=0;ithread_index=0; + tdata->root=root; + tdata->working_set_size=working_set_size; + // clock_t tic2 = clock(); + for (int i = 0; i < 64000; i++) { + walk(tdata); + } + + tdata = malloc(sizeof(struct thread_start_data)); + tdata->thread_index=0; + tdata->root=root; + tdata->working_set_size=working_set_size; + // clock_t tic2 = clock(); + for (int i = 0; i < 64000; i++) { + walk(tdata); + } + + // clock_t toc2 = clock(); + // printf("Elapsed build walk: %f seconds\n", (double)(toc2 - tic2) / CLOCKS_PER_SEC); +// #endif + } + + // printf("-----------------------------------------------"); + + + free(root); + root = NULL; + + return 0; + +} \ No newline at end of file diff --git a/Tests/isa/CPrograms/build-assembler.sh b/Tests/isa/CPrograms/build-assembler.sh index 757cf57..c4eabd0 100644 --- a/Tests/isa/CPrograms/build-assembler.sh +++ b/Tests/isa/CPrograms/build-assembler.sh @@ -1,6 +1,6 @@ # Send assembler file to remote machine to run scp start.S home-1:/home/akilan/cheri/output/sdk/bin/ -# scp main.c home-1:/home/akilan/cheri/output/sdk/bin/ +scp main.c home-1:/home/akilan/cheri/output/sdk/bin/ scp malloc.c home-1:/home/akilan/cheri/output/sdk/bin/ # scp cheri.S home:/home/akilan/cheri/output/sdk/bin/ @@ -13,7 +13,7 @@ scp malloc.c home-1:/home/akilan/cheri/output/sdk/bin/ # ssh home-1 'cd /home/akilan/cheri/output/sdk/bin/ && ./clang --target=riscv64-unknown-elf -march=rv64gcxcheri -mabi=lp64d -nostdlib -nostartfiles -Wl,-Ttext=0x80000000 -o testC start.S main.c' # Malloc test implementation -ssh home-1 'cd /home/akilan/cheri/output/sdk/bin/ && ./clang --target=riscv64-unknown-elf -march=rv64gcxcheri -mabi=lp64d -nostdlib -nostartfiles -fno-builtin-malloc -mcmodel=medany -Wl,-Ttext=0x80000000 -o testC start.S malloc.c' +ssh home-1 'cd /home/akilan/cheri/output/sdk/bin/ && ./clang --target=riscv64-unknown-elf -march=rv64gcxcheri -mabi=lp64d -nostdlib -nostartfiles -fno-builtin-malloc -mcmodel=medany -Wl,-Ttext=0x80000000 -o testC start.S main.c malloc.c' # Disassembly ouput ssh home-1 'cd /home/akilan/cheri/output/sdk/bin/ && ./llvm-objdump -d testC' diff --git a/Tests/isa/CPrograms/main.c b/Tests/isa/CPrograms/main.c index 372e164..b171757 100644 --- a/Tests/isa/CPrograms/main.c +++ b/Tests/isa/CPrograms/main.c @@ -1,5 +1,14 @@ +// #include +// #include + #include #include +#include + +#include "riscv_test.h" + +void free(void * __capability ptr); +void * __capability malloc(size_t size); void test() { @@ -13,40 +22,79 @@ void test() { } // Add delta value for TLB translation -static inline void * __capability add_delta(void * __capability cap, int offset) { - void * __capability result; +// static inline void * __capability add_delta(void * __capability cap, int offset) { +// void * __capability result; - asm volatile ( - "candperm %0, %1, %2" - : "=C" (result) // Output: %0 (result) - : "C" (cap), // Input: %1 (original cap) - "r" (offset) // Input: %2 (offset register) - : // No clobbered registers - ); +// asm volatile ( +// "candperm %0, %1, %2" +// : "=C" (result) // Output: %0 (result) +// : "C" (cap), // Input: %1 (original cap) +// "r" (offset) // Input: %2 (offset register) +// : // No clobbered registers +// ); - return result; -} +// return result; +// } + +// int main(void) { +// void *__capability csp1; + +// void *__capability base = cheri_ddc_get(); + +// uintptr_t addr = 0x80001000; // must be valid RAM in your system + +// csp1 = cheri_address_set(base, addr); +// csp1 = cheri_bounds_set(csp1, 16); + +// csp1 = add_delta(csp1, 15); + +// *((char *__capability)csp1) = 'Z'; + +// char val = *((char *__capability)csp1); +// char val1 = *((char *__capability)csp1); + +// if (val != 'Z') { +// while (1); +// } + +// return 0; +// } int main(void) { - void *__capability csp1; + char * __capability a = malloc(30); + char * __capability b = malloc(16); - void *__capability base = cheri_ddc_get(); - uintptr_t addr = 0x80001000; // must be valid RAM in your system + // if (!a || !b) return -1; - csp1 = cheri_address_set(base, addr); - csp1 = cheri_bounds_set(csp1, 16); + a[0] = 'A'; + a[1] = 'C'; + b[0] = 'B'; - csp1 = add_delta(csp1, 3); + // This will fault (out-of-bounds) + // a[20] = 'X'; - *((char *__capability)csp1) = 'Z'; - - char val = *((char *__capability)csp1); - char val1 = *((char *__capability)csp1); - - if (val != 'Z') { + if (a[1] != 'C') { while (1); } + if (b[0] != 'B') { + while (1); + } + + free(&b); + b = NULL; + + if (b[0] == 'B') { + while (1); + } + + char * __capability c = malloc(16); + + // if (c[0] != 'B') { + // while (1); + // } + + return 0; } \ No newline at end of file diff --git a/Tests/isa/CPrograms/malloc.c b/Tests/isa/CPrograms/malloc.c index d817fbb..f090761 100644 --- a/Tests/isa/CPrograms/malloc.c +++ b/Tests/isa/CPrograms/malloc.c @@ -13,7 +13,7 @@ // | | (Distance 1 between address) // [1, 2, 3. ....... n] -> virtual -#define HEAP_SIZE 10096 +#define HEAP_SIZE 65536 // 64 KB heap #define PHYS_BASE 0x80000000 #define VIRT_BASE 0xFFFFFFFF80000000 @@ -64,7 +64,7 @@ void * __capability malloc(size_t size) { cap = cheri_bounds_set(cap, size); // Hard-coded delta value - cap = add_delta(cap, 4); + cap = add_delta(cap, 10); bump += size; diff --git a/Tests/isa/testC b/Tests/isa/testC index 07cfb17..f6e8ada 100755 Binary files a/Tests/isa/testC and b/Tests/isa/testC differ diff --git a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test-error-1.txt b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test-error-1.txt new file mode 100644 index 0000000..77fad68 --- /dev/null +++ b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test-error-1.txt @@ -0,0 +1,19153 @@ +make -C ../../Tests/elf_to_hex +make[1]: Entering directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/TooobaTest/Toooba/Tests/elf_to_hex' +make[1]: 'elf_to_hex' is up to date. +make[1]: Leaving directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/TooobaTest/Toooba/Tests/elf_to_hex' +../../Tests/elf_to_hex/elf_to_hex ../../Tests/isa/testC Mem.hex +c_mem_load_elf: ../../Tests/isa/testC is a 64-bit ELF file +Section .text : addr 80000000 to addr 800004f4; size 0x 4f4 (= 1268) bytes +Section .data : addr 800014f4 to addr 80001504; size 0x 10 (= 16) bytes +Section .sbss : addr 80001508 to addr 80001510; size 0x 8 (= 8) bytes +Section .bss : addr 80001510 to addr 80003e00; size 0x 28f0 (= 10480) bytes +Section .riscv.attributes: Ignored +Section .comment : Ignored +Section .symtab : Searching for addresses of '_start', 'exit' and 'tohost' symbols +Writing symbols to: symbol_table.txt + No 'exit' label found + No 'tohost' symbol found +Section .shstrtab : Ignored +Section .strtab : Ignored +Min addr: 80000000 (hex) +Max addr: 80003dff (hex) +Writing mem hex to file 'Mem.hex' +Subtracting 0x80000000 base from addresses +./exe_HW_sim +v1 +tohost +Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 496 to 33554430. +1: top.soc_top.rl_reset_start_initial ... +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +11: Mem_Controller.set_addr_map: addr_base 0x80000000 addr_lim 0xc0000000 + SoC address map: + Boot ROM: 0x1000 .. 0x2000 + Mem0 Controller: 0x80000000 .. 0xc0000000 + UART0: 0xc0000000 .. 0xc0000080 +11: top.soc_top.rl_reset_complete_initial +calling cycle +================================================================ +Bluespec RISC-V standalone system simulation v1.2 +Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved. +================================================================ +INFO: watch_tohost 1, tohost_addr = 0x0, fromhost_addr = 0x0 +12: top.soc_top.method start (tohost 0, fromhost 0) +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +100: top.soc_top.rl_step_0, n = 0, do_release +100: top.soc_top do_release(restartRunning: True, to_host_addr: 0) +100: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0 +calling cycle +101: top.soc_top.rl_ctrl_req +101: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0 +101: top.soc_top do_release(restartRunning: True, to_host_addr: 0) +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000020 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle +[RFile] wr_ 1: r 40 <= 0000000000000400000000001fffff44000000 +calling cycle +[RFile] wr_ 0: r 41 <= 0000000000000408000000001fffff44000000 +instret:0 PC:0x1ffff0000000000000000000000001000 instr:0x00000297 iType:Auipc [doCommitNormalInst [0]] 167 +calling cycle +instret:1 PC:0x1ffff0000000000000000000000001004 instr:0x02028593 iType:Alu [doCommitNormalInst [0]] 168 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Csr, execFunc: tagged Alu Csrs, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Valid csrAddrMHARTID, scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle +[RFile] wr_ 0: r 42 <= 0000000000000000000000001fffff44000000 +calling cycle +instret:2 PC:0x1ffff0000000000000000000000001008 instr:0xf1402573 iType:Csr [doCommitSystemInst] 224 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 3340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 3350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000018, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x00001018 +After delta: vaddr = 0x00001018 +calling cycle + 3360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000018, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000000001000 o: 'h0000000000001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000001018, write: False, capStore: False, potentialCapLoad: False } +calling cycle + 3370 : [doFinishMem] DTlbResp { resp: <'h0000000000001018,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000001018, check_high: 'h00000000000001020, check_inclusive: True } }, specBits: 'h000 } +calling cycle +calling cycle +[doDeqLdQ_MMIO_issue] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid }; MMIOCRq { addr: 'h0000000000001018, func: tagged Ld , byteEn: , data: TaggedData { tag: , data: }, loadTags: False } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +[RFile] wr_ 3: r 43 <= 0000000020000000000000001fffff44000000 +[doDeqLdQ_MMIO_deq] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid }; TaggedData { tag: False, data: }; TaggedData { tag: False, data: } +calling cycle +instret:3 PC:0x1ffff000000000000000000000000100c instr:0x0182b283 iType:Ld [doCommitNormalInst [0]] 403 +calling cycle +calling cycle +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000000; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:4 PC:0x1ffff0000000000000000000000001010 instr:0x00028067 iType:Jr [doCommitNormalInst [0]] 408 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling 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+calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00080000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipcc, execFunc: tagged Alu Add, capFunc: tagged CapModify tagged SpecialRW tagged TCC , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrPCC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h48, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h48, src2: tagged Valid 'h48, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000004b2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 46 <= 0000000000020000000000001fffff44000000 +[RFile] wr_ 1: r 45 <= 40000000200000000000ffff1fffff44000000 +calling cycle +[RFile] wr_ 1: r 47 <= 0000000000020000400000001fffff44000000 +instret:5 PC:0x1ffff0000000000000000000080000000 instr:0x020000db iType:Auipcc [doCommitNormalInst [0]] 1155 +instret:6 PC:0x1ffff0000000000000000000080000004 instr:0x000802b7 iType:Alu [doCommitNormalInst [1]] 1155 +calling cycle +[RFile] wr_ 0: r 48 <= 0000000020000400000000001fffff44000000 +instret:7 PC:0x1ffff0000000000000000000080000008 instr:0x00002285 iType:Alu [doCommitNormalInst [0]] 1156 +calling cycle +[RFile] wr_ 0: r 4a <= 0000000020000004000000001fffff44000000 +[RFile] wr_ 1: r 49 <= 0000000020000400000000001fffff44000000 +instret:8 PC:0x1ffff000000000000000000008000000a instr:0x000002b2 iType:Alu [doCommitNormalInst [0]] 1157 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4b <= 0000000020000006000000001fffff44000000 +[ALU redirect - 1] 'h1ffff00000000000000000000800004c2; 'h0; InstTag { way: 'h1, ptr: 'h05, t: 'h0b } + 11580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:9 PC:0x1ffff000000000000000000008000000c instr:0x2052815b iType:Cap [doCommitNormalInst [0]] 1158 +instret:10 PC:0x1ffff0000000000000000000080000010 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1158 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h05, t: 'h0b } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:11 PC:0x1ffff0000000000000000000080000014 instr:0x4b2080e7 iType:Jr [doCommitNormalInst [0]] 1160 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 13430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 13440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff8 +After delta: vaddr = 0x80000ff8 + 13440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4c <= 00000000200003f4000000001fffff44000000 + 13450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000018 o: 'h0000000080000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: True, capStore: False, potentialCapLoad: False } + 13450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff0 +After delta: vaddr = 0x80000ff0 + 13450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4f <= 0000000020000400000000001fffff44000000 + 13460 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } + 13460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: True, capStore: False, potentialCapLoad: False } + 13460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd8 +After delta: vaddr = 0x80000fd8 + 13460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:12 PC:0x1ffff00000000000000000000800004c2 instr:0x00007179 iType:Alu [doCommitNormalInst [0]] 1346 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 50 <= 0000000000000000000000001fffff44000000 + 13470 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } + 13470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd8, write: True, capStore: False, potentialCapLoad: False } + 13470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffec, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fec +After delta: vaddr = 0x80000fec + 13470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:13 PC:0x1ffff00000000000000000000800004c4 instr:0x0000f406 iType:St [doCommitNormalInst [0]] 1347 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffcce }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 53 <= 0000000000000000c00000001fffff44000000 + 13480 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd8, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h84c4 } + 13480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffec, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fec, write: True, capStore: False, potentialCapLoad: False } + 13480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fe0 +After delta: vaddr = 0x80000fe0 + 13480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 13480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84c4 } +instret:14 PC:0x1ffff00000000000000000000800004c6 instr:0x0000f022 iType:St [doCommitNormalInst [0]] 1348 +instret:15 PC:0x1ffff00000000000000000000800004c8 instr:0x00001800 iType:Alu [doCommitNormalInst [1]] 1348 +calling cycle + 13490 : [doFinishMem] DTlbResp { resp: <'h0000000080000fec,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fec, check_high: 'h00000000080000ff0, check_inclusive: True } }, specBits: 'h000 } + 13490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe0 o: 'h0000000080000fe0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe0, write: True, capStore: False, potentialCapLoad: False } + 13490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 13490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84c4 } + 13490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 13490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fe0 +After delta: vaddr = 0x80000fe0 +instret:16 PC:0x1ffff00000000000000000000800004ca instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 1349 +instret:17 PC:0x1ffff00000000000000000000800004cc instr:0xfca43c23 iType:St [doCommitNormalInst [1]] 1349 +calling cycle + 13500 : [doFinishMem] DTlbResp { resp: <'h0000000080000fe0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fe0 o: 'h0000000080000fe0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fe0, check_high: 'h00000000080000fe8, check_inclusive: True } }, specBits: 'h000 } + 13500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe0 o: 'h0000000080000fe0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe0, write: False, capStore: False, potentialCapLoad: False } +instret:18 PC:0x1ffff00000000000000000000800004d0 instr:0xfea42623 iType:St [doCommitNormalInst [0]] 1350 +instret:19 PC:0x1ffff00000000000000000000800004d4 instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 1350 +calling cycle + 13510 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84c4 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000ff8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[RFile] wr_ 1: r 57 <= 0000000020000138000000001fffff44000000 + 13510 : [doFinishMem] DTlbResp { resp: <'h0000000080000fe0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fe0 o: 'h0000000080000fe0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fe0, check_high: 'h00000000080000fe8, check_inclusive: True } }, specBits: 'h000 } + 13510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000fe0, shiftedBE: tagged DataMemAccess , pcHash: 'h84da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, data: TaggedData { tag: False, data: } } +instret:20 PC:0x1ffff00000000000000000000800004d6 instr:0xfea43023 iType:St [doCommitNormalInst [0]] 1351 +calling cycle +[RFile] wr_ 0: r 58 <= 000000002000013a000000001fffff44000000 +[ALU redirect - 0] 'h1ffff00000000000000000000800001ae; 'h0; InstTag { way: 'h0, ptr: 'h0c, t: 'h18 } + 13520 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 55 <= 0000000000000000c00000001fffff44000000 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h0c, t: 'h18 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000fe0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +calling cycle +instret:21 PC:0x1ffff00000000000000000000800004da instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 1355 +calling cycle +[RFile] wr_ 1: r 56 <= 0000000000000006000000001fffff44000000 +calling cycle +instret:22 PC:0x1ffff00000000000000000000800004de instr:0x0000050e iType:Alu [doCommitNormalInst [0]] 1357 +instret:23 PC:0x1ffff00000000000000000000800004e0 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1357 +calling cycle +instret:24 PC:0x1ffff00000000000000000000800004e4 instr:0xcce080e7 iType:Jr [doCommitNormalInst [0]] 1358 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 14290 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000ff8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84c4 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h84c6 } + 14310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84c6 } +calling cycle + 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84c6 } + 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84c6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fd8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h84cc } + 14330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fd8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84cc } +calling cycle + 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fd8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84cc } + 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fd8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84cc } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fec, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h84d0 } + 14350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84d0 } +calling cycle + 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84d0 } + 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84d0 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fe0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h84d6 } + 14370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fe0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84d6 } +calling cycle + 14380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fe0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84d6 } + 14380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fe0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84d6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 14650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 14660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc8 +After delta: vaddr = 0x80000fc8 + 14660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 59 <= 00000000200003e4000000001fffff44000000 + 14670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800004e8 o: 'h00000000800004e8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc8, write: True, capStore: False, potentialCapLoad: False } + 14670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc0 +After delta: vaddr = 0x80000fc0 + 14670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5c <= 00000000200003f4000000001fffff44000000 + 14680 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc8, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h000 } + 14680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc0, write: True, capStore: False, potentialCapLoad: False } + 14680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 14680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:25 PC:0x1ffff00000000000000000000800001ae instr:0x00007139 iType:Alu [doCommitNormalInst [0]] 1468 +calling cycle +[RFile] wr_ 0: r 5e <= 0000000000000005000000001fffff44000000 + 14690 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc0, check_high: 'h00000000080000fc8, check_inclusive: True } }, specBits: 'h000 } + 14690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: True, capStore: False, potentialCapLoad: False } + 14690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 +instret:26 PC:0x1ffff00000000000000000000800001b0 instr:0x0000fc06 iType:St [doCommitNormalInst [0]] 1469 +calling cycle + 14700 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fc8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81b0 } + 14700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000014 o: 'h0000000000000014 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: True, capStore: False, potentialCapLoad: False } + 14700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b0 } +instret:27 PC:0x1ffff00000000000000000000800001b2 instr:0x0000f822 iType:St [doCommitNormalInst [0]] 1470 +instret:28 PC:0x1ffff00000000000000000000800001b4 instr:0x00000080 iType:Alu [doCommitNormalInst [1]] 1470 +calling cycle + 14710 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 14710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b0 } + 14710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b0 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:29 PC:0x1ffff00000000000000000000800001b6 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 1471 +instret:30 PC:0x1ffff00000000000000000000800001ba instr:0x00004551 iType:Alu [doCommitNormalInst [1]] 1471 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fc0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81b2 } + 14720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b2 } +instret:31 PC:0x1ffff00000000000000000000800001bc instr:0xfea43023 iType:St [doCommitNormalInst [0]] 1472 +calling cycle + 14730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b2 } + 14730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b2 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81b6 } + 14740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b6 } +calling cycle + 14750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b6 } + 14750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +calling cycle +calling cycle + 14770 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b6 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000fb8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000019 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffe5e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +[RFile] wr_ 1: r 60 <= 0000000000000006400000001fffff44000000 +calling cycle +[RFile] wr_ 0: r 61 <= 0000000000001900000000001fffff44000000 +[RFile] wr_ 1: r 62 <= 0000000020000071000000001fffff44000000 +instret:32 PC:0x1ffff00000000000000000000800001c0 instr:0x00004565 iType:Alu [doCommitNormalInst [0]] 1522 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h155 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 63 <= 0000000020000073000000001fffff44000000 +[ALU redirect - 0] 'h1ffff0000000000000000000080000022; 'h0; InstTag { way: 'h1, ptr: 'h11, t: 'h23 } +instret:33 PC:0x1ffff00000000000000000000800001c2 instr:0x0000052a iType:Alu [doCommitNormalInst [0]] 1523 +instret:34 PC:0x1ffff00000000000000000000800001c4 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1523 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h11, t: 'h23 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:35 PC:0x1ffff00000000000000000000800001c8 instr:0xe5e080e7 iType:Jr [doCommitNormalInst [0]] 1525 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 15450 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000fb8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81bc } + 15470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81bc } +calling cycle + 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81bc } + 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81bc } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 15840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 64 <= 00000000200003c8000000001fffff44000000 + 15850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800001cc o: 'h00000000800001cc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 15850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 15850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 67 <= 00000000200003e4000000001fffff44000000 + 15860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 15860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 15860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 + 15860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:36 PC:0x1ffff0000000000000000000080000022 instr:0x00007159 iType:Alu [doCommitNormalInst [0]] 1586 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000004ce }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 15870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000006400 o: 'h0000000000006400 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: True, capStore: False, potentialCapLoad: False } + 15870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 +instret:37 PC:0x1ffff0000000000000000000080000024 instr:0x0000f486 iType:St [doCommitNormalInst [0]] 1587 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 15880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8024 } + 15880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } + 15880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } +instret:38 PC:0x1ffff0000000000000000000080000026 instr:0x0000f0a2 iType:St [doCommitNormalInst [0]] 1588 +instret:39 PC:0x1ffff0000000000000000000080000028 instr:0x00001880 iType:Alu [doCommitNormalInst [1]] 1588 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 15890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h802e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } + 15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 15890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:40 PC:0x1ffff000000000000000000008000002a instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1589 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000771 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00002000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6d <= 000000002000040e800000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8026 } + 15900 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 69 <= 0000000000001900000000001fffff44000000 + 15900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001508 +After delta: vaddr = 0x80001508 + 15900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 15900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h028 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6e <= 0000000020000542000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 15910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080001508 o: 'h0000000080001508 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001508 o: 'h0000000080001508 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001508, write: False, capStore: False, potentialCapLoad: False } + 15910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } + 15910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 15910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 15910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15920 : [doFinishMem] DTlbResp { resp: <'h0000000080001508,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001508 o: 'h0000000080001508 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001508, check_high: 'h00000000080001510, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h802a } + 15920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080001508, shiftedBE: tagged DataMemAccess , pcHash: 'h8042 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 15920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } + 15920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 15920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080001508, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } +instret:41 PC:0x1ffff000000000000000000008000002e instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 1592 +calling cycle +[RFile] wr_ 0: r 6a <= 0000000000001901c00000001fffff44000000 +[RFile] wr_ 1: r 72 <= 0000000000000800000000001fffff44000000 + 15930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 15930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 15930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080001508, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } + 15930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 15930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 + 15930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 73 <= 00000000000009dc400000001fffff44000000 +[RFile] wr_ 1: r 6b <= 0000000000001900000000001fffff44000000 + 15940 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000000001900000000001fffff44000000 + 15940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000006400 o: 'h0000000000006400 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: True, capStore: False, potentialCapLoad: False } + 15940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } + 15940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:42 PC:0x1ffff0000000000000000000080000032 instr:0x0000051d iType:Alu [doCommitNormalInst [0]] 1594 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000498 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15950 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080001508, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001508, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 15950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 15950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:43 PC:0x1ffff0000000000000000000080000034 instr:0x00009961 iType:Alu [doCommitNormalInst [0]] 1595 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 15960 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f68, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 15960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 +instret:44 PC:0x1ffff0000000000000000000080000036 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1596 +instret:45 PC:0x1ffff000000000000000000008000003a instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1596 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 76 <= 40000000000000000000ffff1fffff44000000 + 15970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: True, potentialCapLoad: True } + 15970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:46 PC:0x1ffff000000000000000000008000003e instr:0x4ce50513 iType:Alu [doCommitNormalInst [0]] 1597 +calling cycle +[RFile] wr_ 1: r 78 <= 000000002000041c000000001fffff44000000 + 15980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } + 15980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 15980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 79 <= 0000000020000542000000001fffff44000000 + 15990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001508 o: 'h0000000080001508 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } + 15990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001508 +After delta: vaddr = 0x80001508 +calling cycle + 16000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h001 } + 16000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080001508 o: 'h0000000080001508 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001508 o: 'h0000000080001508 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001508, write: False, capStore: False, potentialCapLoad: False } +calling cycle + 16010 : [doFinishMem] DTlbResp { resp: <'h0000000080001508,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001508 o: 'h0000000080001508 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001508, check_high: 'h00000000080001510, check_inclusive: True } }, specBits: 'h001 } + 16010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080001508, shiftedBE: tagged DataMemAccess , pcHash: 'h807c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080001508, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807c } +calling cycle + 16020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080001508, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807c } + 16020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000492 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7c <= 000000002000041f800000001fffff44000000 + 16500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 16500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7d <= 0000000020000544000000001fffff44000000 + 16510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } + 16510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } + 16520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h808c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 16520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 16520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h001 } + 16530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8090 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16530 : [doRespLdForward] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 05 <= 40000000000000000000ffff1fffff44000000 + 16530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 16530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8090 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: True } + 16540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8090 } + 16540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 16540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } + 16550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h809c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } + 16550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 16560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h001 } + 16560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 16560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809c } + 16560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 16560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 +calling cycle + 16570 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000000001900000000001fffff44000000 + 16570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: True } +calling cycle + 16580 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809c } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f30, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[RFile] wr_ 0: r 02 <= 0000000000000001000000001fffff44000000 + 16580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } + 16580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } +calling cycle +[RFile] wr_ 0: r 45 <= 000000002000002c800000001fffff44000000 + 16590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } + 16590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +calling cycle +[RFile] wr_ 1: r 4a <= 000000002000002e800000001fffff44000000 +[ALU redirect - 1] 'h1ffff00000000000000000000800000e4; 'h1; InstTag { way: 'h1, ptr: 'h05, t: 'h0b } +calling cycle +[ROB incorrectSpec] 'h1 ; InstTag { way: 'h1, ptr: 'h05, t: 'h0b } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 16740 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001508, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080001508, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } + 16750 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 +calling cycle + 16760 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6f <= 0000000000000000000000001fffff44000000 + 16760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080001508, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807c } + 16760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 16760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080001508, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807c } + 16760 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } + 16760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080001508, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 16770 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7b <= 0000000000000000000000001fffff44000000 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 16780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:47 PC:0x1ffff0000000000000000000080000042 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 1678 +calling cycle +[RFile] wr_ 1: r 71 <= 0000000000001900000000001fffff44000000 + 16790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 17050 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f68, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 17060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17060 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 17060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8036 } + 17070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8090 } + 17070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 17070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8090 } + 17070 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } + 17070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } +calling cycle + 17080 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 17080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } + 17080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000771 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00002000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h028 }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 17440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 17450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 72 <= 0000000000000800000000001fffff44000000 + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } + 17460 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000498 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 73 <= 00000000000009dc400000001fffff44000000 + 17470 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000000001900000000001fffff44000000 + 17470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 76 <= 40000000000000000000ffff1fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: True, potentialCapLoad: True } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000492 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 78 <= 000000002000041c000000001fffff44000000 + 17490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } + 17490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:48 PC:0x1ffff0000000000000000000080000044 instr:0xfd843583 iType:Ld [doCommitNormalInst [0]] 1749 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 71 <= 0000000000001900000000001fffff44000000 + 17500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 17500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 0000000020000542000000001fffff44000000 +[ALU redirect - 0] 'h1ffff0000000000000000000080000058; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } + 17510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001508 o: 'h0000000080001508 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } + 17510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001508 +After delta: vaddr = 0x80001508 + 17510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:49 PC:0x1ffff0000000000000000000080000048 instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 1751 +instret:50 PC:0x1ffff000000000000000000008000004a instr:0x00006589 iType:Alu [doCommitNormalInst [1]] 1751 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:51 PC:0x1ffff000000000000000000008000004c instr:0x7715859b iType:Alu [doCommitNormalInst [0]] 1753 +instret:52 PC:0x1ffff0000000000000000000080000050 instr:0x00b57463 iType:Br [doCommitNormalInst [1]] 1753 +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000074 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 +calling cycle +[RFile] wr_ 0: r 76 <= 0000000000000000000000001fffff44000000 + 17610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: True, capStore: False, potentialCapLoad: True } +calling cycle + 17620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } +instret:53 PC:0x1ffff0000000000000000000080000058 instr:0x0040006f iType:J [doCommitNormalInst [0]] 1762 +instret:54 PC:0x1ffff000000000000000000008000005c instr:0xfea0055b iType:Cap [doCommitNormalInst [1]] 1762 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:55 PC:0x1ffff0000000000000000000080000060 instr:0xfea44023 iType:St [doCommitNormalInst [0]] 1763 +instret:56 PC:0x1ffff0000000000000000000080000064 instr:0x0740006f iType:J [doCommitNormalInst [1]] 1763 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8060 } + 17640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 + 17640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8060 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: False, capStore: False, potentialCapLoad: True } + 17650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8060 } + 17650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8060 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 17650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 17660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f70, shiftedBE: tagged DataMemAccess , pcHash: 'h80d8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 17660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 17660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d8 } +calling cycle + 17670 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f30, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 17670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 17670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h80dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + 17670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d8 } + 17670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d8 } + 17670 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } + 17670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[RFile] wr_ 1: r 7c <= 00000000200003e4000000001fffff44000000 + 17680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 17680 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 79 <= 0000000000000000000000001fffff44000000 + 17680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17680 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 17680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809c } + 17680 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } + 17680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 17680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 17690 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 17690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } + 17690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 17690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } + 17690 : [Ld resp] 'h0a; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 17690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17700 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h80de } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17700 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: } } + 17700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 17700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 17700 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 17700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80de } +instret:57 PC:0x1ffff00000000000000000000800000d8 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1770 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17710 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 0000000020000073000000001fffff44000000 + 17710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80de } + 17710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80de } + 17710 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } + 17710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17720 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7b <= 00000000200003f4000000001fffff44000000 + 17720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 + 17730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:58 PC:0x1ffff00000000000000000000800000dc instr:0x000070a6 iType:Ld [doCommitNormalInst [0]] 1773 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[ALU redirect - 1] 'h1ffff00000000000000000000800001cc; 'h0; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } + 17740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } + 17740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 + 17740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:59 PC:0x1ffff00000000000000000000800000de instr:0x00007406 iType:Ld [doCommitNormalInst [0]] 1774 +instret:60 PC:0x1ffff00000000000000000000800000e0 instr:0x00006165 iType:Alu [doCommitNormalInst [1]] 1774 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:61 PC:0x1ffff00000000000000000000800000e2 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 1776 +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 17820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: False, potentialCapLoad: True } + 17830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 17830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h800, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7f <= 0000000000000000000000001fffff44000000 + 17840 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 17840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: True, capStore: False, potentialCapLoad: False } + 17840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 17850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +instret:62 PC:0x1ffff00000000000000000000800001cc instr:0xfca44823 iType:St [doCommitNormalInst [0]] 1785 +instret:63 PC:0x1ffff00000000000000000000800001d0 instr:0x00004501 iType:Alu [doCommitNormalInst [1]] 1785 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 40 <= 0000000000000000800000001fffff44000000 + 17860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h81cc } + 17860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 17860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81cc } +instret:64 PC:0x1ffff00000000000000000000800001d2 instr:0xfca42623 iType:St [doCommitNormalInst [0]] 1786 +instret:65 PC:0x1ffff00000000000000000000800001d6 instr:0x0040006f iType:J [doCommitNormalInst [1]] 1786 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17870 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 0000000000000000000000001fffff44000000 + 17870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81cc } + 17870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81cc } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 17870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h400, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h169 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 43 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81d2 } + 17880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: True, capStore: False, potentialCapLoad: False } + 17880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 17880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000038 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h002 } + 17890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d2 } + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d2 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:66 PC:0x1ffff00000000000000000000800001da instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 1789 +instret:67 PC:0x1ffff00000000000000000000800001de instr:0x00004509 iType:Alu [doCommitNormalInst [1]] 1789 +calling cycle +[RFile] wr_ 1: r 45 <= 0000000000000000c00000001fffff44000000 +[ALU redirect - 0] 'h1ffff00000000000000000000800001e8; 'h1; InstTag { way: 'h0, ptr: 'h0a, t: 'h14 } + 17900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h002 } + 17900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: False, data: } } +calling cycle +[ROB incorrectSpec] 'h1 ; InstTag { way: 'h0, ptr: 'h0a, t: 'h14 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 17920 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +instret:68 PC:0x1ffff00000000000000000000800001e0 instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 1792 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 18460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hc00, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 43 <= 0000000000000000000000001fffff44000000 + 18470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 18470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +calling cycle + 18480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 18480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +instret:69 PC:0x1ffff00000000000000000000800001e8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 1848 +instret:70 PC:0x1ffff00000000000000000000800001ec instr:0x00004501 iType:Alu [doCommitNormalInst [1]] 1848 +calling cycle +[RFile] wr_ 1: r 45 <= 0000000000000000c00000001fffff44000000 + 18490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 18490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: False, data: } } +instret:71 PC:0x1ffff00000000000000000000800001ee instr:0xfca42423 iType:St [doCommitNormalInst [0]] 1849 +instret:72 PC:0x1ffff00000000000000000000800001f2 instr:0x0040006f iType:J [doCommitNormalInst [1]] 1849 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81ee } + 18500 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 02 <= 0000000000000000000000001fffff44000000 + 18500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ee } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 18510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ee } + 18510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ee } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 18510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +instret:73 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 1852 +instret:74 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 1852 +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h2; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } +calling cycle +[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:75 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 1855 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 19010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 19020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 19030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 19030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 08 <= 0000000020000484000000001fffff44000000 + 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 19040 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:76 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 1904 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 42 <= 000000002000053d000000001fffff44000000 + 19050 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 0000000000000000000000001fffff44000000 + 19050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 19060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 19070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 19070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:77 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 1907 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 53 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 4e <= 0000000000000000000000001fffff44000000 + 19080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 19080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 19080 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } + 19080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014f4 +After delta: vaddr = 0x800014f4 + 19080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 51 <= 000000002000053d000000001fffff44000000 + 19090 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 0000000000000000000000001fffff44000000 + 19090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h00000000800014f4 o: 'h00000000800014f4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014f4 o: 'h00000000800014f4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014f4, write: False, capStore: False, potentialCapLoad: False } + 19090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 19090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:78 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 1909 +instret:79 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 1909 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 55 <= 0000000020000f20000000001fffff44000000 + 19100 : [doFinishMem] DTlbResp { resp: <'h00000000800014f4,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014f4 o: 'h00000000800014f4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014f4, check_high: 'h000000000800014f8, check_inclusive: True } }, specBits: 'h000 } + 19100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h00000000800014f4, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 19100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 19100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h00000000800014f4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:80 PC:0x1ffff0000000000000000000080000214 instr:0x2e458693 iType:Alu [doCommitNormalInst [0]] 1910 +instret:81 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 1910 +calling cycle +[RFile] wr_ 1: r 57 <= 0000000000000000000000001fffff44000000 + 19110 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 19110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 19110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h00000000800014f4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 19110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 19110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } +calling cycle +[RFile] wr_ 0: r 54 <= 0000000000000000000000001fffff44000000 + 19120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 19120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 19120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 19120 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 19120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } +calling cycle + 19130 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0c, addr: 'h00000000800014f4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800014f4, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[RFile] wr_ 0: r 4b <= 0000000020000f20000000001fffff44000000 + 19130 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000000000006000000001fffff44000000 + 19130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 19130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 19130 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 19130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[RFile] wr_ 0: r 4c <= 0000000020000f20000000001fffff44000000 + 19140 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000000000000001fffff44000000 +calling cycle +calling cycle +calling cycle +[RFile] wr_ 1: r 5d <= 0000000000000000000000001fffff44000000 +calling cycle +[RFile] wr_ 1: r 56 <= 0000000020000f20000000001fffff44000000 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 19600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 19610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 19620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 19620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 19630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 19630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 19630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 19630 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } + 19630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19640 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 19640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19640 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5f <= 0000000000000000000000001fffff44000000 + 19640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 19640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 19650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 19650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 19650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 19650 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 19650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 19650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 19660 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000005000000001fffff44000000 + 19660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 19660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 19660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 19660 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 19660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5e <= 0000000000000000000000001fffff44000000 + 19670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 19670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19670 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000000000000001fffff44000000 + 19670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003c88 +After delta: vaddr = 0x80003c88 + 19670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'he00, localHist: 'h2aa, globalTaken: True, localTaken: True, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 60 <= 0000000020000f20000000001fffff44000000 + 19680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003c88 o: 'h0000000080003c88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003c88, write: True, capStore: False, potentialCapLoad: False } + 19680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 19680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 19680 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } + 19680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19690 : [doFinishMem] DTlbResp { resp: <'h0000000080003c88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003c88 o: 'h0000000080003c88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003c88, check_high: 'h00000000080003c90, check_inclusive: True } }, specBits: 'h000 } + 19690 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 61 <= 0000000000000000000000001fffff44000000 + 19690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 19690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 65 <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 6c <= 0000000000000000000000001fffff44000000 + 19700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 19700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014f4 +After delta: vaddr = 0x800014f4 +calling cycle +[RFile] wr_ 0: r 66 <= 000000002000053d000000001fffff44000000 + 19710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 19710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h00000000800014f4 o: 'h00000000800014f4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014f4 o: 'h00000000800014f4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014f4, write: False, capStore: False, potentialCapLoad: False } + 19710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } +calling cycle +[RFile] wr_ 1: r 69 <= 0000000000000000000000001fffff44000000 + 19720 : [doFinishMem] DTlbResp { resp: <'h00000000800014f4,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014f4 o: 'h00000000800014f4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014f4, check_high: 'h000000000800014f8, check_inclusive: True } }, specBits: 'h000 } + 19720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h00000000800014f4, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 19720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 19720 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 19720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h00000000800014f4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +calling cycle +[RFile] wr_ 0: r 6a <= 0000000020000f20000000001fffff44000000 + 19730 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6e <= 0000000000000000000000001fffff44000000 + 19730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h00000000800014f4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 19730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +calling cycle +[RFile] wr_ 0: r 6b <= 0000000020000f20000000001fffff44000000 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 19860 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800014f4, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 19870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19870 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 19870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h00000000800014f4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 19870 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } + 19870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 +calling cycle + 19880 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 0000000000000006400000001fffff44000000 + 19880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h00000000800014f4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 19880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 19880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h00000000800014f4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 19880 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } + 19880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h00000000800014f4, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 19890 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5c <= 0000000000000006400000001fffff44000000 + 19890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003c90 +After delta: vaddr = 0x80003c90 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 19900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000019 o: 'h0000000000000019 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003c90 o: 'h0000000080003c90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003c90, write: True, capStore: False, potentialCapLoad: False } +instret:82 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 1990 +calling cycle + 19910 : [doFinishMem] DTlbResp { resp: <'h0000000080003c90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003c90 o: 'h0000000080003c90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003c90, check_high: 'h00000000080003c94, check_inclusive: True } }, specBits: 'h000 } +instret:83 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 1991 +instret:84 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 1991 +calling cycle +instret:85 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 1992 +instret:86 PC:0x1ffff0000000000000000000080000228 instr:0xa5c58593 iType:Alu [doCommitNormalInst [1]] 1992 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:87 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 1993 +instret:88 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 1993 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:89 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 1994 +instret:90 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 1994 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003c90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 19950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003c90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:91 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 1995 +instret:92 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 1995 +calling cycle + 19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003c90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:93 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 1996 +instret:94 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 1996 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:95 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 1997 +instret:96 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 1997 +calling cycle + 19980 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003c90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080003c90, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:97 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 1998 +instret:98 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 1998 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h00000000800014f4, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:99 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 1999 +instret:100 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [1]] 1999 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:101 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [0]] 2000 +instret:102 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [1]] 2000 +calling cycle +instret:103 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 2001 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +[RFile] wr_ 2: r 68 <= 0000000000000000000000001fffff44000000 +calling cycle + 20120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:104 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 2012 +instret:105 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 2012 +calling cycle + 20130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003c80 +After delta: vaddr = 0x80003c80 +instret:106 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 2013 +instret:107 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 2013 +calling cycle + 20140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003c80, write: True, capStore: False, potentialCapLoad: False } +instret:108 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 2014 +instret:109 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 2014 +calling cycle + 20150 : [doFinishMem] DTlbResp { resp: <'h0000000080003c80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003c80, check_high: 'h00000000080003c88, check_inclusive: True } }, specBits: 'h000 } +calling cycle +instret:110 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2016 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +calling cycle +instret:111 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 2018 +instret:112 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 2018 +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff9fe }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 20260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h827a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + 20270 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } + 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:113 PC:0x1ffff0000000000000000000080000276 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2027 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000008c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 74 <= 00000000200010a0800000001fffff44000000 + 20280 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000000000000000000001fffff44000000 + 20280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 +calling cycle +[RFile] wr_ 1: r 75 <= 0000000020000f20000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } +calling cycle +[RFile] wr_ 1: r 78 <= 00000000200000a4000000001fffff44000000 + 20300 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 20300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h828c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } +instret:114 PC:0x1ffff000000000000000000008000027a instr:0xfc842503 iType:Ld [doCommitNormalInst [0]] 2030 +calling cycle +[RFile] wr_ 0: r 72 <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 76 <= 00000000200000a6000000001fffff44000000 +[ALU redirect - 1] 'h1ffff000000000000000000008000031c; 'h0; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } + 20310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + 20310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + 20310 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 20310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +[RFile] wr_ 0: r 71 <= 0000000020000f20000000001fffff44000000 + 20330 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000000000000000000001fffff44000000 +instret:115 PC:0x1ffff000000000000000000008000027e instr:0x00551593 iType:Alu [doCommitNormalInst [0]] 2033 +instret:116 PC:0x1ffff0000000000000000000080000282 instr:0x00004517 iType:Auipc [doCommitNormalInst [1]] 2033 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } +instret:117 PC:0x1ffff0000000000000000000080000286 instr:0x9fe50513 iType:Alu [doCommitNormalInst [0]] 2034 +instret:118 PC:0x1ffff000000000000000000008000028a instr:0x0000952e iType:Alu [doCommitNormalInst [1]] 2034 +calling cycle +instret:119 PC:0x1ffff000000000000000000008000028c instr:0xfd04258f iType:Ld [doCommitNormalInst [0]] 2035 +instret:120 PC:0x1ffff0000000000000000000080000290 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2035 +calling cycle +instret:121 PC:0x1ffff0000000000000000000080000294 instr:0x08c080e7 iType:Jr [doCommitNormalInst [0]] 2036 +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 20400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 63 <= 00000000200003cc000000001fffff44000000 + 20410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000298 o: 'h0000000080000298 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 20410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 20410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7d <= 00000000200003e4000000001fffff44000000 + 20420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 20420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 20420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 20420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:122 PC:0x1ffff000000000000000000008000031c instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 2042 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 20430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 20430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 20430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 20430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:123 PC:0x1ffff000000000000000000008000031e instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2043 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 20440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 20440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 20440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +instret:124 PC:0x1ffff0000000000000000000080000320 instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 2044 +instret:125 PC:0x1ffff0000000000000000000080000322 instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 2044 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 20450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 20450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:126 PC:0x1ffff0000000000000000000080000324 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 2045 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 20460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 20460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h832c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 20460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +instret:127 PC:0x1ffff0000000000000000000080000328 instr:0xfcb44823 iType:St [doCommitNormalInst [0]] 2046 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 20470 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 05 <= 0000000020000f20000000001fffff44000000 + 20470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 20470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20480 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080003c90, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 20480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8336 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 20480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003c80 +After delta: vaddr = 0x80003c80 +calling cycle + 20490 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000020000f20000000001fffff44000000 + 20490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003c80, write: False, capStore: False, potentialCapLoad: False } + 20490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20490 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 20490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003c90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:128 PC:0x1ffff000000000000000000008000032c instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2049 +calling cycle + 20500 : [doFinishMem] DTlbResp { resp: <'h0000000080003c80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003c80, check_high: 'h00000000080003c88, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003c88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 20500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080003c80, shiftedBE: tagged DataMemAccess , pcHash: 'h8330 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 20500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003c88 +After delta: vaddr = 0x80003c88 + 20500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003c88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +calling cycle + 20510 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0b <= 0000000000000000000000001fffff44000000 + 20510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003c88 o: 'h0000000080003c88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003c88, write: False, capStore: False, potentialCapLoad: False } + 20510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003c88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 20510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003c88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080003c80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20520 : [doFinishMem] DTlbResp { resp: <'h0000000080003c88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003c88 o: 'h0000000080003c88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003c88, check_high: 'h00000000080003c90, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003c80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 20520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080003c88, shiftedBE: tagged DataMemAccess , pcHash: 'h833a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 20520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080003c88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } +calling cycle + 20530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080003c88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080003c88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + 20530 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003c80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +instret:129 PC:0x1ffff0000000000000000000080000330 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2053 +calling cycle + 20540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 20540 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000000000006000000001fffff44000000 + 20540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003c80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 20540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003c80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h831e } + 20550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 20550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } +instret:130 PC:0x1ffff0000000000000000000080000332 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2055 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } + 20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } + 20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080003c88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8320 } + 20570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } +instret:131 PC:0x1ffff0000000000000000000080000336 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2057 +calling cycle + 20580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } + 20580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:132 PC:0x1ffff000000000000000000008000033a instr:0x00006508 iType:Ld [doCommitNormalInst [0]] 2058 +instret:133 PC:0x1ffff000000000000000000008000033c instr:0xfca43023 iType:St [doCommitNormalInst [1]] 2058 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8324 } + 20590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } +calling cycle + 20600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } + 20600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8328 } + 20610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } +calling cycle + 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } + 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8332 } + 20630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } +calling cycle + 20640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } + 20640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h833c } + 20650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +calling cycle + 20660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 20660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 20950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 20960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 20970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8340 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 20970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8340 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8340 } + 20980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8340 } + 20980 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } + 20980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 20980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf00, localHist: 'h2aa, globalTaken: True, localTaken: True, pcIndex: 'h1ae }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0a <= 0000000000000000000000001fffff44000000 + 20990 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000020000f20000000001fffff44000000 + 20990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } + 20990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 20990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 21000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 21000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003c90 +After delta: vaddr = 0x80003c90 + 21000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 21010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8354 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 21010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003c90 o: 'h0000000080003c90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003c90, write: False, capStore: False, potentialCapLoad: False } + 21010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 +instret:134 PC:0x1ffff0000000000000000000080000340 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2101 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21020 : [doFinishMem] DTlbResp { resp: <'h0000000080003c90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003c90 o: 'h0000000080003c90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003c90, check_high: 'h00000000080003c94, check_inclusive: True } }, specBits: 'h000 } + 21020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080003c90, shiftedBE: tagged DataMemAccess , pcHash: 'h8344 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21020 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 0000000000000000000000001fffff44000000 + 21020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 21020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080003c90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb4, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 21030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8358 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080003c90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + 21030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080003c90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + 21030 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 21030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb4, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb4, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21040 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 0000000000000006400000001fffff44000000 + 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } + 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } + 21040 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } } + 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb4, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f44 +After delta: vaddr = 0x80000f44 + 21040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Lt, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf80, localHist: 'h2aa, globalTaken: True, localTaken: True, pcIndex: 'h1bd }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffbc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0d <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080003c90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21050 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0e <= 0000000000000000000000001fffff44000000 + 21050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb4, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f44 o: 'h0000000080000f44 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f44, write: True, capStore: False, potentialCapLoad: False } + 21050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffbc, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f4c +After delta: vaddr = 0x80000f4c + 21050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb4, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f44,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f44 o: 'h0000000080000f44 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f44, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h002 } + 21060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffbc, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000019 o: 'h0000000000000019 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } + 21060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb4, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f44 +After delta: vaddr = 0x80000f44 + 21060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffbc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:135 PC:0x1ffff0000000000000000000080000344 instr:0x00004908 iType:Ld [doCommitNormalInst [0]] 2106 +calling cycle + 21070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 21070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb4, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f44 o: 'h0000000080000f44 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f44, write: False, capStore: False, potentialCapLoad: False } + 21070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffbc, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f4c +After delta: vaddr = 0x80000f4c +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000360; 'h1; InstTag { way: 'h0, ptr: 'h0f, t: 'h1e } + 21080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f44,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f44 o: 'h0000000080000f44 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f44, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h002 } + 21080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f44, shiftedBE: tagged DataMemAccess , pcHash: 'h8372 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 21080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffbc, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } +instret:136 PC:0x1ffff0000000000000000000080000346 instr:0xfaa42e23 iType:St [doCommitNormalInst [0]] 2108 +instret:137 PC:0x1ffff000000000000000000008000034a instr:0x00004501 iType:Alu [doCommitNormalInst [1]] 2108 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8346 } + 21090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } +[ROB incorrectSpec] 'h1 ; InstTag { way: 'h0, ptr: 'h0f, t: 'h1e } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 21100 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 21100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 21100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:138 PC:0x1ffff000000000000000000008000034c instr:0xfaa42c23 iType:St [doCommitNormalInst [0]] 2110 +instret:139 PC:0x1ffff0000000000000000000080000350 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2110 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h834c } + 21110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } + 21120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:140 PC:0x1ffff0000000000000000000080000354 instr:0xfb842503 iType:Ld [doCommitNormalInst [0]] 2112 +calling cycle +instret:141 PC:0x1ffff0000000000000000000080000358 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2113 +instret:142 PC:0x1ffff000000000000000000008000035c instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2113 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000015a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:143 PC:0x1ffff0000000000000000000080000360 instr:0x15a0006f iType:J [doCommitNormalInst [0]] 2162 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 22130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 22140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 22140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 +calling cycle + 22150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 22150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h84ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + 22150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ba } +calling cycle +[RFile] wr_ 1: r 51 <= 00000000200003e4000000001fffff44000000 + 22160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 22160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h84bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ba } + 22160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ba } + 22160 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } } + 22160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84bc } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22170 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0d <= 00000000200000a6000000001fffff44000000 + 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84bc } + 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84bc } + 22170 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } + 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22180 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4e <= 00000000200003f4000000001fffff44000000 + 22180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:144 PC:0x1ffff00000000000000000000800004ba instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2219 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +instret:145 PC:0x1ffff00000000000000000000800004bc instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2220 +instret:146 PC:0x1ffff00000000000000000000800004be instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2220 +calling cycle + 22210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h004 } + 22210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:147 PC:0x1ffff00000000000000000000800004c0 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2221 +instret:148 PC:0x1ffff0000000000000000000080000298 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2221 +calling cycle + 22220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 22220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 22220 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 22220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:149 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [0]] 2222 +calling cycle + 22230 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000000000000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h780, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 22250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:150 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [0]] 2225 +calling cycle +[RFile] wr_ 1: r 54 <= 0000000000000000400000001fffff44000000 + 22260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 22260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +calling cycle +[RFile] wr_ 0: r 52 <= 0000000000000000c00000001fffff44000000 + 22270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 22270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +instret:151 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 2227 +calling cycle + 22280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 22280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, data: TaggedData { tag: False, data: } } +instret:152 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [0]] 2228 +instret:153 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [1]] 2228 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 22290 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5a <= 0000000000000000400000001fffff44000000 + 22290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 22300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +instret:154 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 2231 +instret:155 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 2231 +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h0; InstTag { way: 'h0, ptr: 'h16, t: 'h2c } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h16, t: 'h2c } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:156 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2234 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 22390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 22400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 22410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 22410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5f <= 0000000020000484000000001fffff44000000 + 22420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 22420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 22420 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } + 22420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:157 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2242 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 56 <= 000000002000053d000000001fffff44000000 + 22430 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5d <= 0000000000000000400000001fffff44000000 + 22430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 22450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 22450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:158 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2245 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 42 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 57 <= 0000000000000001000000001fffff44000000 + 22460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 22460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 22460 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } + 22460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014f8 +After delta: vaddr = 0x800014f8 + 22460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 58 <= 000000002000053e000000001fffff44000000 + 22470 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 60 <= 0000000000000000000000001fffff44000000 + 22470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014f8, write: False, capStore: False, potentialCapLoad: False } + 22470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 22470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:159 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 2247 +instret:160 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2247 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 66 <= 0000000020000f20000000001fffff44000000 + 22480 : [doFinishMem] DTlbResp { resp: <'h00000000800014f8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014f8, check_high: 'h000000000800014fc, check_inclusive: True } }, specBits: 'h000 } + 22480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h00000000800014f8, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 22480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 22480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:161 PC:0x1ffff0000000000000000000080000214 instr:0x2e458693 iType:Alu [doCommitNormalInst [0]] 2248 +instret:162 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 2248 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5c <= 0000000000000008000000001fffff44000000 + 22490 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 22490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 22490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 22490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 22490 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 22490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 22490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5e <= 0000000000000000000000001fffff44000000 + 22500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 22500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22500 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000000000019000000001fffff44000000 + 22500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 22500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 22500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 22500 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 22500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 62 <= 0000000020000f20000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h00000000800014f8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 22510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22510 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000006000000001fffff44000000 + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 22510 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cb0 +After delta: vaddr = 0x80003cb0 + 22510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 61 <= 0000000020000f28000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22520 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6a <= 0000000000000000000000001fffff44000000 + 22520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000064 o: 'h0000000000000064 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cb0 o: 'h0000000080003cb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cb0, write: True, capStore: False, potentialCapLoad: False } + 22520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 22520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 22520 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } + 22520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 22520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:163 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2252 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 22530 : [doFinishMem] DTlbResp { resp: <'h0000000080003cb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cb0 o: 'h0000000080003cb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cb0, check_high: 'h00000000080003cb4, check_inclusive: True } }, specBits: 'h000 } + 22530 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 41 <= 0000000000000000400000001fffff44000000 + 22530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 22530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:164 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 2253 +instret:165 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 2253 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22540 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 22540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 22540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:166 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 2254 +instret:167 PC:0x1ffff0000000000000000000080000228 instr:0xa5c58593 iType:Alu [doCommitNormalInst [1]] 2254 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6d <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 22550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 22550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 22550 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } + 22550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 22550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:168 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 2255 +instret:169 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2255 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 68 <= 0000000020000f20000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22560 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000000000005000000001fffff44000000 + 22560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 22560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 22560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 22560 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 22560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:170 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2256 +instret:171 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 2256 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6f <= 0000000000000008000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003cb0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 22570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22570 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000000000000400000001fffff44000000 + 22570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ca8 +After delta: vaddr = 0x80003ca8 + 22570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:172 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2257 +instret:173 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 2257 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbc0, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6e <= 0000000020000f28000000001fffff44000000 + 22580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ca8 o: 'h0000000080003ca8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ca8, write: True, capStore: False, potentialCapLoad: False } + 22580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 22580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 22580 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } + 22580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003cb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:174 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 2258 +instret:175 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 2258 +calling cycle + 22590 : [doFinishMem] DTlbResp { resp: <'h0000000080003ca8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ca8 o: 'h0000000080003ca8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ca8, check_high: 'h00000000080003cb0, check_inclusive: True } }, specBits: 'h000 } + 22590 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7c <= 0000000000000000000000001fffff44000000 + 22590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003cb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 22590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003cb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 22590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:176 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2259 +instret:177 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2259 +calling cycle +[RFile] wr_ 0: r 75 <= 0000000000000001000000001fffff44000000 +[RFile] wr_ 1: r 7b <= 0000000000000008000000001fffff44000000 + 22600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 22600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014f8 +After delta: vaddr = 0x800014f8 +instret:178 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2260 +instret:179 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 2260 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 72 <= 000000002000053e000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003ca8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 22610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014f8, write: False, capStore: False, potentialCapLoad: False } + 22610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } +calling cycle +[RFile] wr_ 1: r 67 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22620 : [doFinishMem] DTlbResp { resp: <'h00000000800014f8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014f8, check_high: 'h000000000800014fc, check_inclusive: True } }, specBits: 'h000 } + 22620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h00000000800014f8, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 22620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 22620 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } + 22620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:180 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2262 +calling cycle +[RFile] wr_ 0: r 64 <= 0000000020000f20000000001fffff44000000 + 22630 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000000000000000000001fffff44000000 + 22630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 22630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 22630 : [Ld resp] 'h14; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 22630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080003ca8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +instret:181 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 2263 +instret:182 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 2263 +calling cycle +[RFile] wr_ 0: r 7e <= 0000000020000f28000000001fffff44000000 + 22640 : [doRespLdMem] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 0000000000000019000000001fffff44000000 + 22640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080003ca8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 22640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080003ca8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:183 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 2264 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h00000000800014f8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[ALU redirect - 1] 'h1ffff0000000000000000000080000276; 'h0; InstTag { way: 'h1, ptr: 'h08, t: 'h11 } + 22660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:184 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 2266 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h08, t: 'h11 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff9fe }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 22750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h827a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + 22760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + 22760 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } + 22760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000008c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 01 <= 00000000200010a0800000001fffff44000000 + 22770 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0b <= 0000000000000000400000001fffff44000000 + 22770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 44 <= 0000000020000f20000000001fffff44000000 + 22780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 46 <= 00000000200000a4000000001fffff44000000 + 22790 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 22790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h828c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7f <= 0000000000000008000000001fffff44000000 +[RFile] wr_ 1: r 43 <= 00000000200000a6000000001fffff44000000 + 22800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + 22800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + 22800 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 22800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 40 <= 0000000020000f28000000001fffff44000000 + 22810 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 0000000000000000000000001fffff44000000 + 22810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 22810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4a <= 00000000200003cc000000001fffff44000000 + 22820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000298 o: 'h0000000080000298 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 22820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 22820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 45 <= 00000000200003e4000000001fffff44000000 + 22830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 22830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 22830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 22830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 22840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 22840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 22840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 22850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 22850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 22850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 2: r 78 <= 0000000000000000000000001fffff44000000 + 22860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 22860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 22860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 22870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h832c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 22870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:185 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 2287 +instret:186 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 2287 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 22880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8336 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22880 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7d <= 0000000020000f28000000001fffff44000000 + 22880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ca0 +After delta: vaddr = 0x80003ca0 + 22880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:187 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 2288 +instret:188 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 2288 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 22890 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000020000f28000000001fffff44000000 + 22890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ca0, write: True, capStore: False, potentialCapLoad: False } + 22890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ca0 +After delta: vaddr = 0x80003ca0 + 22890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:189 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 2289 +instret:190 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 2289 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22900 : [doFinishMem] DTlbResp { resp: <'h0000000080003ca0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ca0, check_high: 'h00000000080003ca8, check_inclusive: True } }, specBits: 'h000 } + 22900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ca0, write: False, capStore: False, potentialCapLoad: False } + 22900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ca8 +After delta: vaddr = 0x80003ca8 + 22900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22910 : [doFinishMem] DTlbResp { resp: <'h0000000080003ca0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ca0, check_high: 'h00000000080003ca8, check_inclusive: True } }, specBits: 'h000 } + 22910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080003ca0, shiftedBE: tagged DataMemAccess , pcHash: 'h8330 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ca8 o: 'h0000000080003ca8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ca8, write: False, capStore: False, potentialCapLoad: False } + 22910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 22910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:191 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2291 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22920 : [doFinishMem] DTlbResp { resp: <'h0000000080003ca8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ca8 o: 'h0000000080003ca8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ca8, check_high: 'h00000000080003cb0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003ca0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 22920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080003ca8, shiftedBE: tagged DataMemAccess , pcHash: 'h833a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22920 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000000000000000000001fffff44000000 + 22920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 22920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 22920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080003ca8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hde0, localHist: 'h155, globalTaken: True, localTaken: False, pcIndex: 'h1ae }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0e <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 22930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8340 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } + 22930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080003ca8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + 22930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080003ca8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + 22930 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } + 22930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 22930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003ca0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +instret:192 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 2293 +instret:193 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 2293 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000015a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 22940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 22940 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 0000000000000006000000001fffff44000000 + 22940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 22940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003ca0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 22940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003ca0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 22940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:194 PC:0x1ffff0000000000000000000080000276 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2294 +instret:195 PC:0x1ffff000000000000000000008000027a instr:0xfc842503 iType:Ld [doCommitNormalInst [1]] 2294 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 22950 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000020000f28000000001fffff44000000 + 22950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 22950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 22950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:196 PC:0x1ffff000000000000000000008000027e instr:0x00551593 iType:Alu [doCommitNormalInst [0]] 2295 +instret:197 PC:0x1ffff0000000000000000000080000282 instr:0x00004517 iType:Auipc [doCommitNormalInst [1]] 2295 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 22960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 22960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8354 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } + 22960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cb0 +After delta: vaddr = 0x80003cb0 + 22960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:198 PC:0x1ffff0000000000000000000080000286 instr:0x9fe50513 iType:Alu [doCommitNormalInst [0]] 2296 +instret:199 PC:0x1ffff000000000000000000008000028a instr:0x0000952e iType:Alu [doCommitNormalInst [1]] 2296 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } + 22970 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000000000000001fffff44000000 + 22970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cb0 o: 'h0000000080003cb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cb0, write: False, capStore: False, potentialCapLoad: False } + 22970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 22970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:200 PC:0x1ffff000000000000000000008000028c instr:0xfd04258f iType:Ld [doCommitNormalInst [0]] 2297 +instret:201 PC:0x1ffff0000000000000000000080000290 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2297 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 58 <= 00000000200003e4000000001fffff44000000 + 22980 : [doFinishMem] DTlbResp { resp: <'h0000000080003cb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cb0 o: 'h0000000080003cb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cb0, check_high: 'h00000000080003cb4, check_inclusive: True } }, specBits: 'h000 } + 22980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080003cb0, shiftedBE: tagged DataMemAccess , pcHash: 'h8344 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 22980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 22980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080003cb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } +instret:202 PC:0x1ffff0000000000000000000080000294 instr:0x08c080e7 iType:Jr [doCommitNormalInst [0]] 2298 +instret:203 PC:0x1ffff000000000000000000008000031c instr:0x0000711d iType:Alu [doCommitNormalInst [1]] 2298 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 22990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8358 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 22990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080003cb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + 22990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080003cb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + 22990 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 22990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 +instret:204 PC:0x1ffff000000000000000000008000031e instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2299 +instret:205 PC:0x1ffff0000000000000000000080000320 instr:0x0000e8a2 iType:St [doCommitNormalInst [1]] 2299 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080003ca0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h831e } + 23000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h84ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23000 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 0000000000000019000000001fffff44000000 + 23000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + 23000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } +instret:206 PC:0x1ffff0000000000000000000080000322 instr:0x00001080 iType:Alu [doCommitNormalInst [0]] 2300 +instret:207 PC:0x1ffff0000000000000000000080000324 instr:0xfea43423 iType:St [doCommitNormalInst [1]] 2300 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h6f0, localHist: 'h2aa, globalTaken: True, localTaken: True, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h002 } + 23010 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 65 <= 0000000000000000000000001fffff44000000 + 23010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } + 23010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 23010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffbc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f4c +After delta: vaddr = 0x80000f4c +instret:208 PC:0x1ffff0000000000000000000080000328 instr:0xfcb44823 iType:St [doCommitNormalInst [0]] 2301 +instret:209 PC:0x1ffff000000000000000000008000032c instr:0xfe843503 iType:Ld [doCommitNormalInst [1]] 2301 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8320 } + 23020 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h84bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23020 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 69 <= 00000000200000a6000000001fffff44000000 + 23020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffbc, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000064 o: 'h0000000000000064 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } + 23020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } +instret:210 PC:0x1ffff0000000000000000000080000330 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2302 +instret:211 PC:0x1ffff0000000000000000000080000332 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 2302 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080003ca8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 23030 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 57 <= 00000000200003f4000000001fffff44000000 + 23030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } + 23030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 23030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:212 PC:0x1ffff0000000000000000000080000336 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2303 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8324 } + 23040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 23040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } +instret:213 PC:0x1ffff000000000000000000008000033a instr:0x00006508 iType:Ld [doCommitNormalInst [0]] 2304 +instret:214 PC:0x1ffff000000000000000000008000033c instr:0xfca43023 iType:St [doCommitNormalInst [1]] 2304 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 23050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } + 23050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 23050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 23050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 41 <= 0000000020000484000000001fffff44000000 +[RFile] wr_ 1: r 5b <= 0000000000000000c00000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080003cb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8328 } + 23060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 23060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h028 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 23060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h028, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:215 PC:0x1ffff0000000000000000000080000340 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2306 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h028, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h028, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 23070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h028 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 23070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 23070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 23070 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } + 23070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h028 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 23070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } +instret:216 PC:0x1ffff0000000000000000000080000344 instr:0x00004908 iType:Ld [doCommitNormalInst [0]] 2307 +instret:217 PC:0x1ffff0000000000000000000080000346 instr:0xfaa42e23 iType:St [doCommitNormalInst [1]] 2307 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h028, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h028, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 68 <= 000000002000053d000000001fffff44000000 + 23080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h020 } + 23080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23080 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 42 <= 0000000000000000400000001fffff44000000 + 23080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h020 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 23080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 23080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 23080 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } + 23080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } +instret:218 PC:0x1ffff000000000000000000008000034a instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 2308 +instret:219 PC:0x1ffff000000000000000000008000034c instr:0xfaa42c23 iType:St [doCommitNormalInst [1]] 2308 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h020 } + 23090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23090 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 55 <= 0000000000000000400000001fffff44000000 + 23090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 23090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 23090 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 23090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:220 PC:0x1ffff0000000000000000000080000350 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2309 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 56 <= 0000000020001089000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23100 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000000400000001fffff44000000 + 23100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 23100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 23100 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 23100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 23100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } +instret:221 PC:0x1ffff0000000000000000000080000354 instr:0xfb842503 iType:Ld [doCommitNormalInst [0]] 2310 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5e <= 0000000000000000800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23110 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6e <= 0000000000000000000000001fffff44000000 + 23110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 23110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } + 23110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 23110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h020 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 23110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:222 PC:0x1ffff0000000000000000000080000358 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2311 +instret:223 PC:0x1ffff000000000000000000008000035c instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2311 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8332 } + 23120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h020 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 23120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h020 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 23120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } +instret:224 PC:0x1ffff0000000000000000000080000360 instr:0x15a0006f iType:J [doCommitNormalInst [0]] 2312 +instret:225 PC:0x1ffff00000000000000000000800004ba instr:0x000060e6 iType:Ld [doCommitNormalInst [1]] 2312 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 72 <= 0000000020000f20000000001fffff44000000 +[RFile] wr_ 1: r 5c <= 0000000000000001000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23130 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 23130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 23130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } + 23130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 23130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014f8 +After delta: vaddr = 0x800014f8 + 23130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } +instret:226 PC:0x1ffff00000000000000000000800004bc instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2313 +instret:227 PC:0x1ffff00000000000000000000800004be instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2313 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6b <= 000000002000053e000000001fffff44000000 +[RFile] wr_ 1: r 6f <= 0000000000000000000000001fffff44000000 + 23140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h833c } + 23140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014f8, write: False, capStore: False, potentialCapLoad: False } + 23140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 23140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 23140 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 23140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 23140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } +instret:228 PC:0x1ffff00000000000000000000800004c0 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2314 +instret:229 PC:0x1ffff0000000000000000000080000298 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2314 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7a <= 0000000000000008000000001fffff44000000 +[RFile] wr_ 1: r 70 <= 0000000020000f20000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 23150 : [doFinishMem] DTlbResp { resp: <'h00000000800014f8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014f8, check_high: 'h000000000800014fc, check_inclusive: True } }, specBits: 'h000 } + 23150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h00000000800014f8, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23150 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000000000006000000001fffff44000000 + 23150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 23150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 23150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 23150 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } + 23150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:230 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [0]] 2315 +instret:231 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [1]] 2315 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7c <= 0000000020000f28000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 23160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23160 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 0000000000000000000000001fffff44000000 + 23160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 23160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 23160 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 23160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 23160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +instret:232 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 2316 +instret:233 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [1]] 2316 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23170 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000019000000001fffff44000000 + 23170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 23170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 23170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 23170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 23170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:234 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [0]] 2317 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h00000000800014f8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23180 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8346 } + 23180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23180 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 05 <= 0000000000000000800000001fffff44000000 + 23180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 23180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cb0 +After delta: vaddr = 0x80003cb0 + 23180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 23190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000064 o: 'h0000000000000064 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cb0 o: 'h0000000080003cb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cb0, write: True, capStore: False, potentialCapLoad: False } + 23190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 23190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 23190 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } + 23190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 23190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 78 <= 0000000020000f20000000001fffff44000000 + 23200 : [doFinishMem] DTlbResp { resp: <'h0000000080003cb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cb0 o: 'h0000000080003cb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cb0, check_high: 'h00000000080003cb4, check_inclusive: True } }, specBits: 'h000 } + 23200 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0b <= 0000000000000005000000001fffff44000000 + 23200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 23200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 23200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 23200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 73 <= 0000000000000010000000001fffff44000000 + 23210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h834c } + 23210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23210 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000000000000800000001fffff44000000 + 23210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cc8 +After delta: vaddr = 0x80003cc8 + 23210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hb78, localHist: 'h3aa, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 71 <= 0000000020000f30000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cc8 o: 'h0000000080003cc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cc8, write: True, capStore: False, potentialCapLoad: False } + 23220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 23220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 23220 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 23220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } +calling cycle +calling cycle + 23240 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 23240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } + 23240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 23240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 23250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +calling cycle + 23260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 23260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 23260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h5bc, localHist: 'h3aa, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 23310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +calling cycle + 23320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[RFile] wr_ 1: r 5b <= 0000000000000000c00000001fffff44000000 + 23330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 23330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 23340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 23340 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } + 23340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23350 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 55 <= 0000000000000000800000001fffff44000000 + 23350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +instret:235 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 2337 +instret:236 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 2337 +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000204; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } + 23380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 23380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 23400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 23400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 23400 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } + 23400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:237 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2340 +calling cycle + 23410 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 23460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 23470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 41 <= 0000000020000484000000001fffff44000000 + 23480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 23480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 23480 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 23480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:238 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2348 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 68 <= 000000002000053d000000001fffff44000000 + 23490 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000000800000001fffff44000000 + 23490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 23510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 23510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:239 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2351 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 56 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 5c <= 0000000000000002000000001fffff44000000 + 23520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 23520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 23520 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 23520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014fc +After delta: vaddr = 0x800014fc + 23520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6b <= 000000002000053f000000001fffff44000000 + 23530 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6e <= 0000000000000000000000001fffff44000000 + 23530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014fc, write: False, capStore: False, potentialCapLoad: False } + 23530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 23530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:240 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 2353 +instret:241 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2353 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 72 <= 0000000020000f20000000001fffff44000000 + 23540 : [doFinishMem] DTlbResp { resp: <'h00000000800014fc,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014fc, check_high: 'h00000000080001500, check_inclusive: True } }, specBits: 'h000 } + 23540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h00000000800014fc, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 23540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 23540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:242 PC:0x1ffff0000000000000000000080000214 instr:0x2e458693 iType:Alu [doCommitNormalInst [0]] 2354 +instret:243 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 2354 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7a <= 0000000000000010000000001fffff44000000 + 23550 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 23550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 23550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 23550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 23550 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 23550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 23550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6f <= 0000000000000000000000001fffff44000000 + 23560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 23560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23560 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000064000000001fffff44000000 + 23560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 23560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 23560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 23560 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 23560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 70 <= 0000000020000f20000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h00000000800014fc, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 23570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23570 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000000000006000000001fffff44000000 + 23570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 23570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 23570 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } + 23570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cd0 +After delta: vaddr = 0x80003cd0 + 23570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7c <= 0000000020000f30000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23580 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 0000000000000000000000001fffff44000000 + 23580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000190 o: 'h0000000000000190 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cd0 o: 'h0000000080003cd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cd0, write: True, capStore: False, potentialCapLoad: False } + 23580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 23580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 23580 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } + 23580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 23580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23580 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h000000008000153c, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:244 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2358 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23590 : [doFinishMem] DTlbResp { resp: <'h0000000080003cd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cd0 o: 'h0000000080003cd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cd0, check_high: 'h00000000080003cd4, check_inclusive: True } }, specBits: 'h000 } + 23590 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 05 <= 0000000000000000800000001fffff44000000 + 23590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 23590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h000000008000153c, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h000000008000153c, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 23590 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h000000008000157c, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:245 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 2359 +instret:246 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 2359 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23600 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 23600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 23600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h000000008000157c, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 23600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:247 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 2360 +instret:248 PC:0x1ffff0000000000000000000080000228 instr:0xa5c58593 iType:Alu [doCommitNormalInst [1]] 2360 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 23610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 23610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 23610 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } + 23610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 23610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:249 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 2361 +instret:250 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2361 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23620 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h000000008000157c, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h000000008000157c, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[RFile] wr_ 1: r 78 <= 0000000020000f20000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23620 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0b <= 0000000000000005000000001fffff44000000 + 23620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 23620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 23620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 23620 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 23620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:251 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2362 +instret:252 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 2362 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 73 <= 0000000000000010000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003cd0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 23630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23630 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000000000000800000001fffff44000000 + 23630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cc8 +After delta: vaddr = 0x80003cc8 + 23630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:253 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2363 +instret:254 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 2363 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hade, localHist: 'h3aa, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 71 <= 0000000020000f30000000001fffff44000000 + 23640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cc8 o: 'h0000000080003cc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cc8, write: True, capStore: False, potentialCapLoad: False } + 23640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 23640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 23640 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 23640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003cd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:255 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 2364 +instret:256 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 2364 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23650 : [doFinishMem] DTlbResp { resp: <'h0000000080003cc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cc8 o: 'h0000000080003cc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cc8, check_high: 'h00000000080003cd0, check_inclusive: True } }, specBits: 'h000 } + 23650 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 0000000000000000000000001fffff44000000 + 23650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003cd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 23650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 23650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 23650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:257 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2365 +instret:258 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2365 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 44 <= 0000000000000002000000001fffff44000000 +[RFile] wr_ 1: r 4e <= 0000000000000010000000001fffff44000000 + 23660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 23660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014fc +After delta: vaddr = 0x800014fc + 23660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:259 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2366 +instret:260 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 2366 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 23670 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003cd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080003cd0, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[RFile] wr_ 0: r 7f <= 000000002000053f000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 23670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014fc, write: False, capStore: False, potentialCapLoad: False } + 23670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 23670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0a <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23680 : [doFinishMem] DTlbResp { resp: <'h00000000800014fc,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014fc, check_high: 'h00000000080001500, check_inclusive: True } }, specBits: 'h000 } + 23680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h00000000800014fc, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 23680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 23680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 23680 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } + 23680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:261 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2368 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h56f, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 77 <= 0000000020000f20000000001fffff44000000 + 23690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 23690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23690 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000000000000001fffff44000000 + 23690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 23690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 23690 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } } + 23690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 23690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:262 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 2369 +instret:263 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 2369 +calling cycle +[RFile] wr_ 0: r 02 <= 0000000020000f30000000001fffff44000000 + 23700 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0d <= 0000000000000064000000001fffff44000000 + 23700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 23700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 23700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 23700 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 23700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23700 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003d10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:264 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 2370 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, paddr: 'h00000000800014fc, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 23710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23710 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000000800000001fffff44000000 + 23710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003d10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 23710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[ALU redirect - 1] 'h1ffff0000000000000000000080000276; 'h0; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } + 23720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 23720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 23720 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } + 23720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23720 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080003d50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:265 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 2372 +calling cycle + 23730 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003d10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080003d10, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 23730 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h000000008000153c, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 23740 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 23740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080003d50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +calling cycle + 23750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h000000008000153c, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h000000008000153c, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23750 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h000000008000157c, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +calling cycle + 23760 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080003d50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080003d50, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 23760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h000000008000157c, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff9fe }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 23810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h827a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + 23820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + 23820 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } + 23820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000008c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 49 <= 00000000200010a0800000001fffff44000000 + 23830 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000000000000800000001fffff44000000 + 23830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 50 <= 0000000020000f20000000001fffff44000000 + 23840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4d <= 00000000200000a4000000001fffff44000000 + 23850 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 23850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h828c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0c <= 0000000000000010000000001fffff44000000 +[RFile] wr_ 1: r 54 <= 00000000200000a6000000001fffff44000000 + 23860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + 23860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + 23860 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } + 23860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 53 <= 0000000020000f30000000001fffff44000000 + 23870 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4b <= 0000000000000000000000001fffff44000000 + 23870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 23870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4c <= 00000000200003cc000000001fffff44000000 + 23880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000298 o: 'h0000000080000298 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 23880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 23880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 52 <= 00000000200003e4000000001fffff44000000 + 23890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 23890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 23890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 23890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 23900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 23900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 23900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 23900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 23910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 23910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 23910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 2: r 46 <= 0000000000000000000000001fffff44000000 + 23920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 23920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 23920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 23930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 23930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h832c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 23930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:266 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 2393 +instret:267 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 2393 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 23940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8336 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23940 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 45 <= 0000000020000f30000000001fffff44000000 + 23940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cc0 +After delta: vaddr = 0x80003cc0 + 23940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:268 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 2394 +instret:269 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 2394 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23950 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6c <= 0000000020000f30000000001fffff44000000 + 23950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cc0, write: True, capStore: False, potentialCapLoad: False } + 23950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cc0 +After delta: vaddr = 0x80003cc0 + 23950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:270 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 2395 +instret:271 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 2395 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 23960 : [doFinishMem] DTlbResp { resp: <'h0000000080003cc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cc0, check_high: 'h00000000080003cc8, check_inclusive: True } }, specBits: 'h000 } + 23960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cc0, write: False, capStore: False, potentialCapLoad: False } + 23960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cc8 +After delta: vaddr = 0x80003cc8 + 23960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23970 : [doFinishMem] DTlbResp { resp: <'h0000000080003cc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cc0, check_high: 'h00000000080003cc8, check_inclusive: True } }, specBits: 'h000 } + 23970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080003cc0, shiftedBE: tagged DataMemAccess , pcHash: 'h8330 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cc8 o: 'h0000000080003cc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cc8, write: False, capStore: False, potentialCapLoad: False } + 23970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 23970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:272 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2397 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23980 : [doFinishMem] DTlbResp { resp: <'h0000000080003cc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cc8 o: 'h0000000080003cc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cc8, check_high: 'h00000000080003cd0, check_inclusive: True } }, specBits: 'h000 } + 23980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080003cc8, shiftedBE: tagged DataMemAccess , pcHash: 'h833a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23980 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 0000000000000000000000001fffff44000000 + 23980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 23980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 23980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hd6f, localHist: 'h0aa, globalTaken: True, localTaken: False, pcIndex: 'h1ae }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 65 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 23990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8340 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23990 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 60 <= 0000000000000006000000001fffff44000000 + 23990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } + 23990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 23990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:273 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 2399 +instret:274 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 2399 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000015a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 24000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 24000 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 42 <= 0000000020000f30000000001fffff44000000 + 24000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 24000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 24000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:275 PC:0x1ffff0000000000000000000080000276 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2400 +instret:276 PC:0x1ffff000000000000000000008000027a instr:0xfc842503 iType:Ld [doCommitNormalInst [1]] 2400 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 24010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } + 24010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cd0 +After delta: vaddr = 0x80003cd0 + 24010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:277 PC:0x1ffff000000000000000000008000027e instr:0x00551593 iType:Alu [doCommitNormalInst [0]] 2401 +instret:278 PC:0x1ffff0000000000000000000080000282 instr:0x00004517 iType:Auipc [doCommitNormalInst [1]] 2401 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } + 24020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cd0 o: 'h0000000080003cd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cd0, write: False, capStore: False, potentialCapLoad: False } + 24020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 24020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:279 PC:0x1ffff0000000000000000000080000286 instr:0x9fe50513 iType:Alu [doCommitNormalInst [0]] 2402 +instret:280 PC:0x1ffff000000000000000000008000028a instr:0x0000952e iType:Alu [doCommitNormalInst [1]] 2402 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24030 : [doFinishMem] DTlbResp { resp: <'h0000000080003cd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cd0 o: 'h0000000080003cd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cd0, check_high: 'h00000000080003cd4, check_inclusive: True } }, specBits: 'h000 } + 24030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080003cd0, shiftedBE: tagged DataMemAccess , pcHash: 'h8344 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 24030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 24030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:281 PC:0x1ffff000000000000000000008000028c instr:0xfd04258f iType:Ld [doCommitNormalInst [0]] 2403 +instret:282 PC:0x1ffff0000000000000000000080000290 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2403 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6b <= 00000000200003e4000000001fffff44000000 + 24040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 24040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8354 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24040 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5d <= 0000000000000064000000001fffff44000000 + 24040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 24040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 24040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:283 PC:0x1ffff0000000000000000000080000294 instr:0x08c080e7 iType:Jr [doCommitNormalInst [0]] 2404 +instret:284 PC:0x1ffff000000000000000000008000031c instr:0x0000711d iType:Alu [doCommitNormalInst [1]] 2404 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 24050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8358 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24050 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6a <= 0000000000000000000000001fffff44000000 + 24050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 24050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffbc, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f4c +After delta: vaddr = 0x80000f4c + 24050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:285 PC:0x1ffff000000000000000000008000031e instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2405 +instret:286 PC:0x1ffff0000000000000000000080000320 instr:0x0000e8a2 iType:St [doCommitNormalInst [1]] 2405 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080003cc0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } + 24060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h84ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24060 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 + 24060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffbc, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000190 o: 'h0000000000000190 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } + 24060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 +instret:287 PC:0x1ffff0000000000000000000080000322 instr:0x00001080 iType:Alu [doCommitNormalInst [0]] 2406 +instret:288 PC:0x1ffff0000000000000000000080000324 instr:0xfea43423 iType:St [doCommitNormalInst [1]] 2406 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h6b7, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 24070 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 67 <= 00000000200000a6000000001fffff44000000 + 24070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +instret:289 PC:0x1ffff0000000000000000000080000328 instr:0xfcb44823 iType:St [doCommitNormalInst [0]] 2407 +instret:290 PC:0x1ffff000000000000000000008000032c instr:0xfe843503 iType:Ld [doCommitNormalInst [1]] 2407 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h002 } + 24080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h84bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, data: TaggedData { tag: False, data: } } +instret:291 PC:0x1ffff0000000000000000000080000330 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2408 +instret:292 PC:0x1ffff0000000000000000000080000332 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 2408 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080003cc8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24090 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5c <= 00000000200003f4000000001fffff44000000 + 24090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:293 PC:0x1ffff0000000000000000000080000336 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2409 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 24100 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h000000008000157c, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 24100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:294 PC:0x1ffff000000000000000000008000033a instr:0x00006508 iType:Ld [doCommitNormalInst [0]] 2410 +instret:295 PC:0x1ffff000000000000000000008000033c instr:0xfca43023 iType:St [doCommitNormalInst [1]] 2410 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h03d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 59 <= 0000000000000000c00000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h000000008000157c, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h35b, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03a, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080003cd0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 24120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 24120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 24120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:296 PC:0x1ffff0000000000000000000080000340 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2412 +calling cycle + 24130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 24130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 24130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 24130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 24130 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } + 24130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h032 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 24130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } +instret:297 PC:0x1ffff0000000000000000000080000344 instr:0x00004908 iType:Ld [doCommitNormalInst [0]] 2413 +instret:298 PC:0x1ffff0000000000000000000080000346 instr:0xfaa42e23 iType:St [doCommitNormalInst [1]] 2413 +calling cycle + 24140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h020 } + 24140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24140 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 56 <= 0000000000000000800000001fffff44000000 + 24140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h022 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 24140 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } + 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +instret:299 PC:0x1ffff000000000000000000008000034a instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 2414 +instret:300 PC:0x1ffff000000000000000000008000034c instr:0xfaa42c23 iType:St [doCommitNormalInst [1]] 2414 +calling cycle +[RFile] wr_ 1: r 71 <= 0000000000000000800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h020 } + 24150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24150 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 66 <= 0000000000000000800000001fffff44000000 + 24150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 24150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 24150 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 24150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } +instret:301 PC:0x1ffff0000000000000000000080000350 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2415 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h023, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h021, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24160 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 0000000000000000000000001fffff44000000 + 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 24160 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:302 PC:0x1ffff0000000000000000000080000354 instr:0xfb842503 iType:Ld [doCommitNormalInst [0]] 2416 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h023, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h023, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6f <= 0000000000000000c00000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24170 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000000000000000000001fffff44000000 + 24170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 24170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:303 PC:0x1ffff0000000000000000000080000358 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2417 +instret:304 PC:0x1ffff000000000000000000008000035c instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2417 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h027, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h027, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h5; InstTag { way: 'h1, ptr: 'h09, t: 'h13 } + 24180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 24180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h020 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 24180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h023, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:305 PC:0x1ffff0000000000000000000080000360 instr:0x15a0006f iType:J [doCommitNormalInst [0]] 2418 +instret:306 PC:0x1ffff00000000000000000000800004ba instr:0x000060e6 iType:Ld [doCommitNormalInst [1]] 2418 +calling cycle +[ROB incorrectSpec] 'h5 ; InstTag { way: 'h1, ptr: 'h09, t: 'h13 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h0 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:307 PC:0x1ffff00000000000000000000800004bc instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2420 +instret:308 PC:0x1ffff00000000000000000000800004be instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2420 +calling cycle +instret:309 PC:0x1ffff00000000000000000000800004c0 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2421 +instret:310 PC:0x1ffff0000000000000000000080000298 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2421 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } +instret:311 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [0]] 2422 +instret:312 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [1]] 2422 +calling cycle +instret:313 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 2423 +instret:314 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [1]] 2423 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:315 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [0]] 2424 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 24260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 24270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, data: TaggedData { tag: False, data: } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 05 <= 0000000020000484000000001fffff44000000 + 24280 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 79 <= 0000000000000000c00000001fffff44000000 + 24280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 78 <= 000000002000053d000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 24300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7a <= 0000000000000003000000001fffff44000000 + 24310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 24310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001500 +After delta: vaddr = 0x80001500 + 24310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 68 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 7e <= 0000000020000540000000001fffff44000000 + 24320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001500, write: False, capStore: False, potentialCapLoad: False } + 24320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 24320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 24320 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } + 24320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7f <= 0000000020000f20000000001fffff44000000 + 24330 : [doFinishMem] DTlbResp { resp: <'h0000000080001500,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001500, check_high: 'h00000000080001504, check_inclusive: True } }, specBits: 'h000 } + 24330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080001500, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24330 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000000000000000000001fffff44000000 + 24330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 24330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0d <= 0000000000000018000000001fffff44000000 + 24340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 24340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 24340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 24340 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 24340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 24340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24350 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 24350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24350 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000000000190000000001fffff44000000 + 24350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 24350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 73 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080001500, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 24360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 24360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 24360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 24360 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 24360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0b <= 0000000020000f20000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 24370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24370 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000000000006000000001fffff44000000 + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 24370 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cf0 +After delta: vaddr = 0x80003cf0 + 24370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24370 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 51 <= 0000000020000f38000000001fffff44000000 + 24380 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000000000000000000001fffff44000000 + 24380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000640 o: 'h0000000000000640 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cf0 o: 'h0000000080003cf0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cf0, write: True, capStore: False, potentialCapLoad: False } + 24380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 24380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 24380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24390 : [doFinishMem] DTlbResp { resp: <'h0000000080003cf0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cf0 o: 'h0000000080003cf0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cf0, check_high: 'h00000000080003cf4, check_inclusive: True } }, specBits: 'h000 } + 24390 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7d <= 0000000000000000c00000001fffff44000000 + 24390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 24390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24400 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001580, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 24400 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 24400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 24400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24410 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080003cd0, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +[RFile] wr_ 1: r 76 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 24410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 24410 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 46 <= 0000000020000f20000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24420 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000000000005000000001fffff44000000 + 24420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003cd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003cc8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 24430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003cc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +calling cycle + 24440 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 24440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003cc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 24440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003cc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003cc0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 24450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003cc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +calling cycle + 24460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003cc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 24460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003cc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24460 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080003d08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h831e } + 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080003d08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 24470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } +calling cycle + 24480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } + 24480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24480 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080003d48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8320 } + 24490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080003d48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 24490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } + 24500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24500 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080003d00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h5ad, localHist: 'h3d5, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8324 } + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080003d00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 24510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } +calling cycle + 24520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 24520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } + 24520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24520 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080003d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +calling cycle +[RFile] wr_ 1: r 59 <= 0000000000000000c00000001fffff44000000 + 24530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8328 } + 24530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080003d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 24530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24540 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 66 <= 0000000000000000c00000001fffff44000000 + 24540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } + 24540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8332 } + 24550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 24560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } + 24560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +instret:316 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 2456 +instret:317 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 2456 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000204; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h833c } + 24570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 24570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 24590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 24590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:318 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2459 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8346 } + 24600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } +calling cycle + 24610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 24610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h834c } + 24620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } + 24630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 24640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 24650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 24650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 24650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 24660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 05 <= 0000000020000484000000001fffff44000000 + 24670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 24670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 24670 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } + 24670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:319 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2467 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 78 <= 000000002000053d000000001fffff44000000 + 24680 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 79 <= 0000000000000000c00000001fffff44000000 + 24680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 24700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 24700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:320 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2470 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 68 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 7a <= 0000000000000003000000001fffff44000000 + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 24710 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001500 +After delta: vaddr = 0x80001500 + 24710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24720 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080003d10, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +[RFile] wr_ 1: r 7e <= 0000000020000540000000001fffff44000000 + 24720 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000000000000000000001fffff44000000 + 24720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001500, write: False, capStore: False, potentialCapLoad: False } + 24720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 24720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:321 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 2472 +instret:322 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2472 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7f <= 0000000020000f20000000001fffff44000000 + 24730 : [doFinishMem] DTlbResp { resp: <'h0000000080001500,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001500, check_high: 'h00000000080001504, check_inclusive: True } }, specBits: 'h000 } + 24730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080001500, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 24730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24730 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 24730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003d10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 24730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:323 PC:0x1ffff0000000000000000000080000214 instr:0x2e458693 iType:Alu [doCommitNormalInst [0]] 2473 +instret:324 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 2473 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0d <= 0000000000000018000000001fffff44000000 + 24740 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 24740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 24740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 24740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 24740 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 24740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 73 <= 0000000000000000000000001fffff44000000 + 24750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 24750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24750 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000000000190000000001fffff44000000 + 24750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 24750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 24750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 24750 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 24750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0b <= 0000000020000f20000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080001500, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 24760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24760 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000000000006000000001fffff44000000 + 24760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 24760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 24760 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 24760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cf0 +After delta: vaddr = 0x80003cf0 + 24760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 51 <= 0000000020000f38000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24770 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000000000000000000001fffff44000000 + 24770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000640 o: 'h0000000000000640 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cf0 o: 'h0000000080003cf0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cf0, write: True, capStore: False, potentialCapLoad: False } + 24770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 24770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 24770 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } + 24770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 24770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:325 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2477 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24780 : [doFinishMem] DTlbResp { resp: <'h0000000080003cf0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cf0 o: 'h0000000080003cf0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cf0, check_high: 'h00000000080003cf4, check_inclusive: True } }, specBits: 'h000 } + 24780 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7d <= 0000000000000000c00000001fffff44000000 + 24780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 24780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:326 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 2478 +instret:327 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 2478 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24790 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 24790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 24790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:328 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 2479 +instret:329 PC:0x1ffff0000000000000000000080000228 instr:0xa5c58593 iType:Alu [doCommitNormalInst [1]] 2479 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 76 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 24800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 24800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 24800 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } + 24800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 24800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:330 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 2480 +instret:331 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2480 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 46 <= 0000000020000f20000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24810 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000000000005000000001fffff44000000 + 24810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 24810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 24810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 24810 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } + 24810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:332 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2481 +instret:333 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 2481 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 08 <= 0000000000000018000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003cf0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 24820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24820 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 0000000000000000c00000001fffff44000000 + 24820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ce8 +After delta: vaddr = 0x80003ce8 + 24820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:334 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2482 +instret:335 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 2482 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'had6, localHist: 'h3d5, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 40 <= 0000000020000f38000000001fffff44000000 + 24830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ce8 o: 'h0000000080003ce8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ce8, write: True, capStore: False, potentialCapLoad: False } + 24830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 24830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 24830 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } + 24830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003cf0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:336 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 2483 +instret:337 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 2483 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24840 : [doFinishMem] DTlbResp { resp: <'h0000000080003ce8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ce8 o: 'h0000000080003ce8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ce8, check_high: 'h00000000080003cf0, check_inclusive: True } }, specBits: 'h000 } + 24840 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 0000000000000000000000001fffff44000000 + 24840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003cf0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 24840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003cf0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 24840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:338 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2484 +instret:339 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2484 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 50 <= 0000000000000003000000001fffff44000000 +[RFile] wr_ 1: r 57 <= 0000000000000018000000001fffff44000000 + 24850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 24850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001500 +After delta: vaddr = 0x80001500 + 24850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:340 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2485 +instret:341 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 2485 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0c <= 0000000020000540000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003ce8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 24860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001500, write: False, capStore: False, potentialCapLoad: False } + 24860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0e <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24870 : [doFinishMem] DTlbResp { resp: <'h0000000080001500,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001500, check_high: 'h00000000080001504, check_inclusive: True } }, specBits: 'h000 } + 24870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080001500, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 24870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 24870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 24870 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 24870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:342 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2487 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h56b, localHist: 'h3aa, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 47 <= 0000000020000f20000000001fffff44000000 + 24880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 24880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24880 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000000000000001fffff44000000 + 24880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 24880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 24880 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } + 24880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:343 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 2488 +instret:344 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 2488 +calling cycle +[RFile] wr_ 0: r 5a <= 0000000020000f38000000001fffff44000000 + 24890 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 69 <= 0000000000000190000000001fffff44000000 + 24890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 24890 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } + 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003ce8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +instret:345 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 2489 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080001500, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 24900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24900 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6c <= 0000000000000000c00000001fffff44000000 + 24900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003ce8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 24900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003ce8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[ALU redirect - 1] 'h1ffff0000000000000000000080000276; 'h0; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } + 24910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 24910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 24910 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 24910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24910 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:346 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 2491 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 24930 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff9fe }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 25000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h827a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + 25010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + 25010 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 25010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000008c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4f <= 00000000200010a0800000001fffff44000000 + 25020 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 0000000000000000c00000001fffff44000000 + 25020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25030 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080003d50, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +[RFile] wr_ 1: r 60 <= 0000000020000f20000000001fffff44000000 + 25030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5d <= 00000000200000a4000000001fffff44000000 + 25040 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 25040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h828c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25040 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 25040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080003d50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 25040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6c <= 0000000000000018000000001fffff44000000 +[RFile] wr_ 1: r 5e <= 00000000200000a6000000001fffff44000000 + 25050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + 25050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + 25050 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 25050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 42 <= 0000000020000f38000000001fffff44000000 + 25060 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000000000000001fffff44000000 + 25060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 25060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 61 <= 00000000200003cc000000001fffff44000000 + 25070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000298 o: 'h0000000080000298 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 25070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 25070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5b <= 00000000200003e4000000001fffff44000000 + 25080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 25080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 25080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 25080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 25090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 25090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 25090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 25100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 25100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 25100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 2: r 4d <= 0000000000000000000000001fffff44000000 + 25110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 25110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 25110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 25120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h832c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 25120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:347 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 2512 +instret:348 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 2512 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 25130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8336 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25130 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 0000000020000f38000000001fffff44000000 + 25130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ce0 +After delta: vaddr = 0x80003ce0 + 25130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:349 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 2513 +instret:350 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 2513 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25140 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7b <= 0000000020000f38000000001fffff44000000 + 25140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ce0, write: True, capStore: False, potentialCapLoad: False } + 25140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ce0 +After delta: vaddr = 0x80003ce0 + 25140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:351 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 2514 +instret:352 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 2514 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25150 : [doFinishMem] DTlbResp { resp: <'h0000000080003ce0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ce0, check_high: 'h00000000080003ce8, check_inclusive: True } }, specBits: 'h000 } + 25150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ce0, write: False, capStore: False, potentialCapLoad: False } + 25150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ce8 +After delta: vaddr = 0x80003ce8 + 25150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25160 : [doFinishMem] DTlbResp { resp: <'h0000000080003ce0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ce0, check_high: 'h00000000080003ce8, check_inclusive: True } }, specBits: 'h000 } + 25160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080003ce0, shiftedBE: tagged DataMemAccess , pcHash: 'h8330 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ce8 o: 'h0000000080003ce8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ce8, write: False, capStore: False, potentialCapLoad: False } + 25160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 25160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:353 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2516 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25170 : [doFinishMem] DTlbResp { resp: <'h0000000080003ce8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ce8 o: 'h0000000080003ce8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ce8, check_high: 'h00000000080003cf0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003ce0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 25170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080003ce8, shiftedBE: tagged DataMemAccess , pcHash: 'h833a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25170 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4c <= 0000000000000000000000001fffff44000000 + 25170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 25170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 25170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080003ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hd6b, localHist: 'h055, globalTaken: True, localTaken: False, pcIndex: 'h1ae }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 75 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 25180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8340 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } + 25180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080003ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + 25180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080003ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + 25180 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 25180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 25180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003ce0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +instret:354 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 2518 +instret:355 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 2518 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000015a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 25190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 25190 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6e <= 0000000000000006000000001fffff44000000 + 25190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 25190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003ce0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 25190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003ce0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 25190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:356 PC:0x1ffff0000000000000000000080000276 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2519 +instret:357 PC:0x1ffff000000000000000000008000027a instr:0xfc842503 iType:Ld [doCommitNormalInst [1]] 2519 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 25200 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 56 <= 0000000020000f38000000001fffff44000000 + 25200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 25200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 25200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:358 PC:0x1ffff000000000000000000008000027e instr:0x00551593 iType:Alu [doCommitNormalInst [0]] 2520 +instret:359 PC:0x1ffff0000000000000000000080000282 instr:0x00004517 iType:Auipc [doCommitNormalInst [1]] 2520 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 25210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8354 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } + 25210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cf0 +After delta: vaddr = 0x80003cf0 + 25210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:360 PC:0x1ffff0000000000000000000080000286 instr:0x9fe50513 iType:Alu [doCommitNormalInst [0]] 2521 +instret:361 PC:0x1ffff000000000000000000008000028a instr:0x0000952e iType:Alu [doCommitNormalInst [1]] 2521 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } + 25220 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 0000000000000000000000001fffff44000000 + 25220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cf0 o: 'h0000000080003cf0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cf0, write: False, capStore: False, potentialCapLoad: False } + 25220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 25220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:362 PC:0x1ffff000000000000000000008000028c instr:0xfd04258f iType:Ld [doCommitNormalInst [0]] 2522 +instret:363 PC:0x1ffff0000000000000000000080000290 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2522 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7e <= 00000000200003e4000000001fffff44000000 + 25230 : [doFinishMem] DTlbResp { resp: <'h0000000080003cf0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cf0 o: 'h0000000080003cf0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cf0, check_high: 'h00000000080003cf4, check_inclusive: True } }, specBits: 'h000 } + 25230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080003cf0, shiftedBE: tagged DataMemAccess , pcHash: 'h8344 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 25230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 25230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080003cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } +instret:364 PC:0x1ffff0000000000000000000080000294 instr:0x08c080e7 iType:Jr [doCommitNormalInst [0]] 2523 +instret:365 PC:0x1ffff000000000000000000008000031c instr:0x0000711d iType:Alu [doCommitNormalInst [1]] 2523 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 25240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8358 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 25240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080003cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + 25240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080003cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + 25240 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 25240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 +instret:366 PC:0x1ffff000000000000000000008000031e instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2524 +instret:367 PC:0x1ffff0000000000000000000080000320 instr:0x0000e8a2 iType:St [doCommitNormalInst [1]] 2524 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080003ce0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h831e } + 25250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h84ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25250 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000190000000001fffff44000000 + 25250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + 25250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } +instret:368 PC:0x1ffff0000000000000000000080000322 instr:0x00001080 iType:Alu [doCommitNormalInst [0]] 2525 +instret:369 PC:0x1ffff0000000000000000000080000324 instr:0xfea43423 iType:St [doCommitNormalInst [1]] 2525 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h6b5, localHist: 'h3aa, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h002 } + 25260 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000000000000000000001fffff44000000 + 25260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } + 25260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffbc, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f4c +After delta: vaddr = 0x80000f4c +instret:370 PC:0x1ffff0000000000000000000080000328 instr:0xfcb44823 iType:St [doCommitNormalInst [0]] 2526 +instret:371 PC:0x1ffff000000000000000000008000032c instr:0xfe843503 iType:Ld [doCommitNormalInst [1]] 2526 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8320 } + 25270 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h84bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25270 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 00000000200000a6000000001fffff44000000 + 25270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffbc, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000640 o: 'h0000000000000640 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } + 25270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } +instret:372 PC:0x1ffff0000000000000000000080000330 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2527 +instret:373 PC:0x1ffff0000000000000000000080000332 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 2527 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080003ce8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 25280 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 00000000200003f4000000001fffff44000000 + 25280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } + 25280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:374 PC:0x1ffff0000000000000000000080000336 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2528 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8324 } + 25290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 25290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } +instret:375 PC:0x1ffff000000000000000000008000033a instr:0x00006508 iType:Ld [doCommitNormalInst [0]] 2529 +instret:376 PC:0x1ffff000000000000000000008000033c instr:0xfca43023 iType:St [doCommitNormalInst [1]] 2529 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } + 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 25300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h35a, localHist: 'h355, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h07d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 74 <= 0000000000000000c00000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080003cf0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8328 } + 25310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 25310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 25310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:377 PC:0x1ffff0000000000000000000080000340 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2531 +calling cycle + 25320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 25320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 25320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 25320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 25320 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } + 25320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h078 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 25320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } +instret:378 PC:0x1ffff0000000000000000000080000344 instr:0x00004908 iType:Ld [doCommitNormalInst [0]] 2532 +instret:379 PC:0x1ffff0000000000000000000080000346 instr:0xfaa42e23 iType:St [doCommitNormalInst [1]] 2532 +calling cycle + 25330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h030 } + 25330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25330 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 68 <= 0000000000000000c00000001fffff44000000 + 25330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h070 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 25330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 25330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 25330 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } + 25330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +instret:380 PC:0x1ffff000000000000000000008000034a instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 2533 +instret:381 PC:0x1ffff000000000000000000008000034c instr:0xfaa42c23 iType:St [doCommitNormalInst [1]] 2533 +calling cycle + 25340 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001580, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +[RFile] wr_ 0: r 40 <= 0000000000000000800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h020 } + 25340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25340 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 72 <= 0000000000000000c00000001fffff44000000 + 25340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 25340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 25340 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } } + 25340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:382 PC:0x1ffff0000000000000000000080000350 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2534 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h023, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h022, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25350 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0d <= 0000000000000000000000001fffff44000000 + 25350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25350 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 25350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 25350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 25350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } +instret:383 PC:0x1ffff0000000000000000000080000354 instr:0xfb842503 iType:Ld [doCommitNormalInst [0]] 2535 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h023, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h023, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 73 <= 0000000000000001000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 25360 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } +instret:384 PC:0x1ffff0000000000000000000080000358 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2536 +instret:385 PC:0x1ffff000000000000000000008000035c instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2536 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h027, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h027, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h5; InstTag { way: 'h1, ptr: 'h09, t: 'h13 } + 25370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 25370 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000000000000000000001fffff44000000 + 25370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } + 25370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h020 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 25370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h023, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:386 PC:0x1ffff0000000000000000000080000360 instr:0x15a0006f iType:J [doCommitNormalInst [0]] 2537 +instret:387 PC:0x1ffff00000000000000000000800004ba instr:0x000060e6 iType:Ld [doCommitNormalInst [1]] 2537 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8332 } + 25380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } +[ROB incorrectSpec] 'h5 ; InstTag { way: 'h1, ptr: 'h09, t: 'h13 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h0 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } + 25390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:388 PC:0x1ffff00000000000000000000800004bc instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2539 +instret:389 PC:0x1ffff00000000000000000000800004be instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2539 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h833c } + 25400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +instret:390 PC:0x1ffff00000000000000000000800004c0 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2540 +instret:391 PC:0x1ffff0000000000000000000080000298 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2540 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:392 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [0]] 2541 +instret:393 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [1]] 2541 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8346 } + 25420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } +instret:394 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 2542 +instret:395 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [1]] 2542 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 25430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:396 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [0]] 2543 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h834c } + 25440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 25440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 25450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 25450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } + 25450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 25460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7d <= 0000000020000484000000001fffff44000000 + 25470 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000001000000001fffff44000000 + 25470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 25470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 46 <= 000000002000053d000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 25490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0d <= 0000000000000004000000001fffff44000000 + 25500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 25500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001504 +After delta: vaddr = 0x80001504 + 25500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 78 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 02 <= 0000000020000541000000001fffff44000000 + 25510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080001504 o: 'h0000000080001504 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001504 o: 'h0000000080001504 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001504, write: False, capStore: False, potentialCapLoad: False } + 25510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 25510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 25510 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } + 25510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0c <= 0000000020000f20000000001fffff44000000 + 25520 : [doFinishMem] DTlbResp { resp: <'h0000000080001504,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001504 o: 'h0000000080001504 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001504, check_high: 'h00000000080001508, check_inclusive: True } }, specBits: 'h000 } + 25520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080001504, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25520 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000000000000001fffff44000000 + 25520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 25520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080001504, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 69 <= 0000000000000020000000001fffff44000000 + 25530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 25530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080001504, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 25530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080001504, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 25530 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 25530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 25530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25540 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 25540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25540 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000000000000000000001fffff44000000 + 25540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 25540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 25540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 08 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080001504, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 25550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 25550 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } + 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 63 <= 0000000020000f20000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 25560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25560 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 0000000000000006000000001fffff44000000 + 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 25560 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d10 +After delta: vaddr = 0x80003d10 + 25560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 58 <= 0000000020000f40000000001fffff44000000 + 25570 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 0000000000000000000000001fffff44000000 + 25570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d10 o: 'h0000000080003d10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d10, write: True, capStore: False, potentialCapLoad: False } + 25570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 25570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 25570 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } } + 25570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 25570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25580 : [doFinishMem] DTlbResp { resp: <'h0000000080003d10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d10 o: 'h0000000080003d10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d10, check_high: 'h00000000080003d14, check_inclusive: True } }, specBits: 'h000 } + 25580 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 45 <= 0000000000000001000000001fffff44000000 + 25580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 25580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25590 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 25590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 25590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 43 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 25600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 25600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 25600 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 25600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 25600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4d <= 0000000020000f20000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25610 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 0000000000000005000000001fffff44000000 + 25610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 25610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 25610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 25610 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 25610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5f <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 25620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25620 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000001000000001fffff44000000 + 25620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d08 +After delta: vaddr = 0x80003d08 + 25620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hb5a, localHist: 'h3ea, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 53 <= 0000000020000f40000000001fffff44000000 + 25630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d08 o: 'h0000000080003d08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d08, write: True, capStore: False, potentialCapLoad: False } + 25630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 25630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 25630 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } + 25630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle + 25650 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h5ad, localHist: 'h3ea, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +calling cycle + 25730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[RFile] wr_ 1: r 74 <= 0000000000000000c00000001fffff44000000 + 25740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 25740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 25750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 25750 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } + 25750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25760 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 72 <= 0000000000000001000000001fffff44000000 + 25760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +instret:397 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 2578 +instret:398 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 2578 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 25790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h2d6, localHist: 'h355, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 25800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 25800 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } } + 25800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +instret:399 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2580 +instret:400 PC:0x1ffff0000000000000000000080000200 instr:0x0ae0006f iType:J [doCommitNormalInst [1]] 2580 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00a, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25810 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0d <= 0000000000000000000000001fffff44000000 + 25810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +instret:401 PC:0x1ffff00000000000000000000800002ae instr:0x0040006f iType:J [doCommitNormalInst [0]] 2581 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 40 <= 0000000000000000800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 25820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 25830 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 25830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:402 PC:0x1ffff00000000000000000000800002b2 instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 2583 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h96b, localHist: 'h1f5, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0c <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 7d <= 0000000000000000400000001fffff44000000 + 25840 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000000000000000000001fffff44000000 + 25840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: True, capStore: False, potentialCapLoad: False } + 25840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 25840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 25850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 25850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:403 PC:0x1ffff00000000000000000000800002b6 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 2585 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h002 } + 25860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 25860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:404 PC:0x1ffff00000000000000000000800002b8 instr:0xfca42623 iType:St [doCommitNormalInst [0]] 2586 +instret:405 PC:0x1ffff00000000000000000000800002bc instr:0xf1fff06f iType:J [doCommitNormalInst [1]] 2586 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7f <= 0000000000000000c00000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 25870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82b8 } + 25870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 25870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h03a, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25880 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 0000000000000000000000001fffff44000000 + 25880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 25880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } + 25880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h4b5, localHist: 'h355, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h028 } + 25890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h029 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 25890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h02b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 25900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 25900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 25900 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 25900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h3; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } + 25910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h009 } + 25910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25910 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 0000000000000000400000001fffff44000000 + 25910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } +calling cycle +[ROB incorrectSpec] 'h3 ; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 25930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 25930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 25930 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } + 25930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle + 25950 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hcb5, localHist: 'h3aa, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 26020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 40 <= 0000000000000000800000001fffff44000000 + 26040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 26040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 26050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 26050 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 26050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 26050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'he5a, localHist: 'h2fa, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0c <= 0000000000000000000000001fffff44000000 + 26060 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000000000000400000001fffff44000000 + 26060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 26060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 26070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[RFile] wr_ 0: r 7f <= 0000000000000000c00000001fffff44000000 + 26080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 26080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, data: TaggedData { tag: False, data: } } +instret:406 PC:0x1ffff00000000000000000000800001da instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 2608 +instret:407 PC:0x1ffff00000000000000000000800001de instr:0x00004509 iType:Alu [doCommitNormalInst [1]] 2608 +calling cycle + 26090 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 0000000000000000000000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h009, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:408 PC:0x1ffff00000000000000000000800001e0 instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2610 +instret:409 PC:0x1ffff00000000000000000000800001e8 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2610 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00a, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:410 PC:0x1ffff00000000000000000000800001ec instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 2611 +instret:411 PC:0x1ffff00000000000000000000800001ee instr:0xfca42423 iType:St [doCommitNormalInst [1]] 2611 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000204; 'h3; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81ee } + 26120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00b } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 26120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ee } +instret:412 PC:0x1ffff00000000000000000000800001f2 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2612 +instret:413 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [1]] 2612 +calling cycle +[ROB incorrectSpec] 'h3 ; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 26140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ee } + 26140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ee } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 26140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:414 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [0]] 2614 +instret:415 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [1]] 2614 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 26190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 26200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 26210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 26210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 45 <= 0000000020000484000000001fffff44000000 + 26220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 26220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 26220 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } + 26220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:416 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2622 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5f <= 000000002000053d000000001fffff44000000 + 26230 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 43 <= 0000000000000000000000001fffff44000000 + 26230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 26250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 26250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:417 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2625 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 60 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 4d <= 0000000000000000000000001fffff44000000 + 26260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 26260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 26260 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 26260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014f4 +After delta: vaddr = 0x800014f4 + 26260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 53 <= 000000002000053d000000001fffff44000000 + 26270 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 0000000000000000400000001fffff44000000 + 26270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h00000000800014f4 o: 'h00000000800014f4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014f4 o: 'h00000000800014f4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014f4, write: False, capStore: False, potentialCapLoad: False } + 26270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 26270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:418 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 2627 +instret:419 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2627 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6c <= 0000000020000f20000000001fffff44000000 + 26280 : [doFinishMem] DTlbResp { resp: <'h00000000800014f4,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014f4 o: 'h00000000800014f4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014f4, check_high: 'h000000000800014f8, check_inclusive: True } }, specBits: 'h000 } + 26280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h00000000800014f4, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 26280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 26280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0f, addr: 'h00000000800014f4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:420 PC:0x1ffff0000000000000000000080000214 instr:0x2e458693 iType:Alu [doCommitNormalInst [0]] 2628 +instret:421 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 2628 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5d <= 0000000000000000000000001fffff44000000 + 26290 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 26290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 26290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h00000000800014f4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 26290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0f, addr: 'h00000000800014f4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 26290 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } + 26290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 26290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4f <= 0000000000000020000000001fffff44000000 + 26300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 26300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26300 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5a <= 0000000000000006400000001fffff44000000 + 26300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 26300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 26300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 26300 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } + 26300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 67 <= 0000000020000f40000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h00000000800014f4, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 26310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26310 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4b <= 0000000000000006000000001fffff44000000 + 26310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 26310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 26310 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } + 26310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d10 +After delta: vaddr = 0x80003d10 + 26310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6b <= 0000000020000f40000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26320 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5c <= 0000000000000000400000001fffff44000000 + 26320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000019 o: 'h0000000000000019 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d10 o: 'h0000000080003d10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d10, write: True, capStore: False, potentialCapLoad: False } + 26320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 26320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 26320 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } + 26320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 26320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:422 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2632 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 26330 : [doFinishMem] DTlbResp { resp: <'h0000000080003d10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d10 o: 'h0000000080003d10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d10, check_high: 'h00000000080003d14, check_inclusive: True } }, specBits: 'h000 } + 26330 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 42 <= 0000000000000000000000001fffff44000000 + 26330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 26330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:423 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 2633 +instret:424 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 2633 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26340 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 26340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 26340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:425 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 2634 +instret:426 PC:0x1ffff0000000000000000000080000228 instr:0xa5c58593 iType:Alu [doCommitNormalInst [1]] 2634 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 55 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 26350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 26350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 26350 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } + 26350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 26350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:427 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 2635 +instret:428 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2635 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 54 <= 0000000020000f40000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26360 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7b <= 0000000000000005000000001fffff44000000 + 26360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 26360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 26360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 26360 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } + 26360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:429 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2636 +instret:430 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 2636 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 52 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d10, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 26370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26370 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6a <= 0000000000000000000000001fffff44000000 + 26370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d08 +After delta: vaddr = 0x80003d08 + 26370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:431 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2637 +instret:432 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 2637 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf2d, localHist: 'h3ea, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 41 <= 0000000020000f40000000001fffff44000000 + 26380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d08 o: 'h0000000080003d08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d08, write: True, capStore: False, potentialCapLoad: False } + 26380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 26380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 26380 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } + 26380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080003d10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:433 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 2638 +instret:434 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 2638 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26390 : [doFinishMem] DTlbResp { resp: <'h0000000080003d08,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d08 o: 'h0000000080003d08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d08, check_high: 'h00000000080003d10, check_inclusive: True } }, specBits: 'h000 } + 26390 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6f <= 0000000000000000400000001fffff44000000 + 26390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080003d10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 26390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080003d10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 26390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 26390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:435 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2639 +instret:436 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2639 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6e <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 62 <= 0000000000000000000000001fffff44000000 + 26400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 26400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014f4 +After delta: vaddr = 0x800014f4 + 26400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:437 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2640 +instret:438 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 2640 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 56 <= 000000002000053d000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d08, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 26410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h00000000800014f4 o: 'h00000000800014f4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014f4 o: 'h00000000800014f4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014f4, write: False, capStore: False, potentialCapLoad: False } + 26410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 26410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7c <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26420 : [doFinishMem] DTlbResp { resp: <'h00000000800014f4,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014f4 o: 'h00000000800014f4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014f4, check_high: 'h000000000800014f8, check_inclusive: True } }, specBits: 'h000 } + 26420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h00000000800014f4, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 26420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 26420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 26420 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } + 26420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h00000000800014f4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:439 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2642 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h796, localHist: 'h3d5, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 75 <= 0000000020000f40000000001fffff44000000 + 26430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 26430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26430 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5e <= 0000000000000000400000001fffff44000000 + 26430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h00000000800014f4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 26430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h00000000800014f4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 26430 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } + 26430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 26430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:440 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 2643 +instret:441 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 2643 +calling cycle +[RFile] wr_ 0: r 59 <= 0000000020000f40000000001fffff44000000 + 26440 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000000000006400000001fffff44000000 + 26440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 26440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 26440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 26440 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } + 26440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003d08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +instret:442 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 2644 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h00000000800014f4, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 26450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26450 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4e <= 0000000000000000000000001fffff44000000 + 26450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003d08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 26450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003d08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 26450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 26460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 26460 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } + 26460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26460 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003d90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:443 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 2646 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0b <= 0000000000000000c00000001fffff44000000 + 26470 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 79 <= 0000000000000000000000001fffff44000000 + 26470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003d90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 26470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 26470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26470 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080003d88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 71 <= 0000000000000000400000001fffff44000000 + 26480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 26480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080003d88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 26480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26490 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003d90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080003d90, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 26490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 26490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 26490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h3cb, localHist: 'h3d5, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h4; InstTag { way: 'h1, ptr: 'h1b, t: 'h37 } + 26500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h010 } + 26500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h011 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 26500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +calling cycle +[ROB incorrectSpec] 'h4 ; InstTag { way: 'h1, ptr: 'h1b, t: 'h37 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 26520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 26520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 26520 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 26520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 26530 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 26570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 26580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 26590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 26590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, data: TaggedData { tag: False, data: } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 76 <= 0000000020000484000000001fffff44000000 + 26600 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 0000000000000000400000001fffff44000000 + 26600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 74 <= 000000002000053d000000001fffff44000000 + 26610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 26620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 77 <= 0000000000000001000000001fffff44000000 + 26630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 26630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014f8 +After delta: vaddr = 0x800014f8 + 26630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7d <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 0d <= 000000002000053e000000001fffff44000000 + 26640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014f8, write: False, capStore: False, potentialCapLoad: False } + 26640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 26640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 26640 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } + 26640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 08 <= 0000000020000f20000000001fffff44000000 + 26650 : [doFinishMem] DTlbResp { resp: <'h00000000800014f8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014f8, check_high: 'h000000000800014fc, check_inclusive: True } }, specBits: 'h000 } + 26650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h00000000800014f8, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26650 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 02 <= 0000000000000000400000001fffff44000000 + 26650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 26650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 40 <= 0000000000000008000000001fffff44000000 +[RFile] wr_ 2: r 6d <= 0000000000000000000000001fffff44000000 + 26660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 26660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 26660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 26660 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 26660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 26660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 26670 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 26670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26670 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 0000000000000019000000001fffff44000000 + 26670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 26670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 26670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } +instret:444 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 2667 +instret:445 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 2667 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 72 <= 0000000000000020000000001fffff44000000 + 26680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 26680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 26680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 26680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 26680 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 26680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d00 +After delta: vaddr = 0x80003d00 + 26680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } +instret:446 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 2668 +instret:447 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 2668 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 78 <= 0000000020000f40000000001fffff44000000 + 26690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 26690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 26690 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000000000006000000001fffff44000000 + 26690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d00, write: True, capStore: False, potentialCapLoad: False } + 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 26690 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d30 +After delta: vaddr = 0x80003d30 + 26690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26690 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001538, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:448 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 2669 +instret:449 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 2669 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 63 <= 0000000020000f48000000001fffff44000000 + 26700 : [doFinishMem] DTlbResp { resp: <'h0000000080003d00,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d00, check_high: 'h00000000080003d08, check_inclusive: True } }, specBits: 'h000 } + 26700 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000000400000001fffff44000000 + 26700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000064 o: 'h0000000000000064 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d30 o: 'h0000000080003d30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d30, write: True, capStore: False, potentialCapLoad: False } + 26700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001538, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001538, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 26700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26700 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 26710 : [doFinishMem] DTlbResp { resp: <'h0000000080003d30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d30 o: 'h0000000080003d30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d30, check_high: 'h00000000080003d34, check_inclusive: True } }, specBits: 'h000 } + 26710 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 0000000000000000400000001fffff44000000 + 26710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 26710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:450 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2671 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26720 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d00, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 26720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 26720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 49 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 26730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 26730 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 26730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003d00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +instret:451 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 2673 +instret:452 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 2673 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 47 <= 0000000020000f40000000001fffff44000000 + 26740 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 0000000000000005000000001fffff44000000 + 26740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 26740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003d00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 26740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003d00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 26740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:453 PC:0x1ffff0000000000000000000080000272 instr:0x02a0006f iType:J [doCommitNormalInst [0]] 2674 +instret:454 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [1]] 2674 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7f <= 0000000000000008000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 26750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 26750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26750 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000000400000001fffff44000000 + 26750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d28 +After delta: vaddr = 0x80003d28 + 26750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:455 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [0]] 2675 +instret:456 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [1]] 2675 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbcb, localHist: 'h1f5, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 58 <= 0000000020000f48000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d28 o: 'h0000000080003d28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d28, write: True, capStore: False, potentialCapLoad: False } + 26760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 26760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 26760 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 26760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26760 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080003d80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:457 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [0]] 2676 +instret:458 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [1]] 2676 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h00000000800014f8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26770 : [doFinishMem] DTlbResp { resp: <'h0000000080003d28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d28 o: 'h0000000080003d28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d28, check_high: 'h00000000080003d30, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 26770 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000000400000001fffff44000000 + 26770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080003d80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 26770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 26770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 45 <= 0000000000000001000000001fffff44000000 +[RFile] wr_ 1: r 65 <= 0000000000000008000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 26780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 26780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 26780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014f8 +After delta: vaddr = 0x800014f8 + 26780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 57 <= 000000002000053e000000001fffff44000000 + 26790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 26790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014f8, write: False, capStore: False, potentialCapLoad: False } + 26790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 26790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 43 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26800 : [doFinishMem] DTlbResp { resp: <'h00000000800014f8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014f8, check_high: 'h000000000800014fc, check_inclusive: True } }, specBits: 'h000 } + 26800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h00000000800014f8, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 26800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 26800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 26800 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } + 26800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h5e5, localHist: 'h3ea, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 67 <= 0000000020000f40000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 26810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26810 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5c <= 0000000000000000400000001fffff44000000 + 26810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 26810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 26810 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 26810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 26810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +calling cycle +calling cycle + 26830 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 26830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 26830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 26830 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } + 26830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26830 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001538, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +calling cycle + 26840 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 26840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001538, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001538, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26840 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +calling cycle + 26850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h2f2, localHist: 'h37d, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 26900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0b <= 0000000000000000c00000001fffff44000000 + 26920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 26920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 26930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 26930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 26930 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } + 26930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26940 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 79 <= 0000000000000000400000001fffff44000000 + 26940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 26950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h179, localHist: 'h3d5, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 26960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 26960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 26960 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 26960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +instret:459 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 2696 +instret:460 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 2696 +calling cycle + 26970 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080003d90, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +[ALU redirect - 1] 'h1ffff0000000000000000000080000204; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } + 26970 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000000000000400000001fffff44000000 + 26970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 26990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26990 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 26990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003d90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:461 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2699 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 27050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 27060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 76 <= 0000000020000484000000001fffff44000000 + 27070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 27070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 27070 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 27070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:462 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2707 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 74 <= 000000002000053d000000001fffff44000000 + 27080 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 0000000000000000400000001fffff44000000 + 27080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 27100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 27100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:463 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2710 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7d <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 77 <= 0000000000000001000000001fffff44000000 + 27110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 27110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 27110 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } + 27110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014f8 +After delta: vaddr = 0x800014f8 + 27110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0d <= 000000002000053e000000001fffff44000000 + 27120 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 02 <= 0000000000000000400000001fffff44000000 + 27120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014f8, write: False, capStore: False, potentialCapLoad: False } + 27120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 27120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:464 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 2712 +instret:465 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2712 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 08 <= 0000000020000f20000000001fffff44000000 + 27130 : [doFinishMem] DTlbResp { resp: <'h00000000800014f8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014f8, check_high: 'h000000000800014fc, check_inclusive: True } }, specBits: 'h000 } + 27130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h00000000800014f8, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 27130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 27130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:466 PC:0x1ffff0000000000000000000080000214 instr:0x2e458693 iType:Alu [doCommitNormalInst [0]] 2713 +instret:467 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 2713 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 40 <= 0000000000000008000000001fffff44000000 + 27140 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 27140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 27140 : [Ld resp] 'h0a; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 27140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 72 <= 0000000000000020000000001fffff44000000 + 27150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 27150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27150 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 0000000000000019000000001fffff44000000 + 27150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 27150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 27150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 27150 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 27150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 78 <= 0000000020000f40000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h00000000800014f8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 27160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27160 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000000000006000000001fffff44000000 + 27160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 27160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 27160 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 27160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d30 +After delta: vaddr = 0x80003d30 + 27160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 63 <= 0000000020000f48000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27170 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000000400000001fffff44000000 + 27170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000064 o: 'h0000000000000064 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d30 o: 'h0000000080003d30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d30, write: True, capStore: False, potentialCapLoad: False } + 27170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 27170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 27170 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } + 27170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 27170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:468 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2717 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27180 : [doFinishMem] DTlbResp { resp: <'h0000000080003d30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d30 o: 'h0000000080003d30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d30, check_high: 'h00000000080003d34, check_inclusive: True } }, specBits: 'h000 } + 27180 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 0000000000000000400000001fffff44000000 + 27180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 27180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:469 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 2718 +instret:470 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 2718 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27190 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 27190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 27190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:471 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 2719 +instret:472 PC:0x1ffff0000000000000000000080000228 instr:0xa5c58593 iType:Alu [doCommitNormalInst [1]] 2719 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 49 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 27200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 27200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 27200 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 27200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 27200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:473 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 2720 +instret:474 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2720 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 47 <= 0000000020000f40000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27210 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 0000000000000005000000001fffff44000000 + 27210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 27210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 27210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 27210 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 27210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:475 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2721 +instret:476 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 2721 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7f <= 0000000000000008000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d30, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 27220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27220 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000000400000001fffff44000000 + 27220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d28 +After delta: vaddr = 0x80003d28 + 27220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:477 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2722 +instret:478 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 2722 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h979, localHist: 'h1f5, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 58 <= 0000000020000f48000000001fffff44000000 + 27230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d28 o: 'h0000000080003d28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d28, write: True, capStore: False, potentialCapLoad: False } + 27230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 27230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 27230 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 27230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003d30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:479 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 2723 +instret:480 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 2723 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27240 : [doFinishMem] DTlbResp { resp: <'h0000000080003d28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d28 o: 'h0000000080003d28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d28, check_high: 'h00000000080003d30, check_inclusive: True } }, specBits: 'h000 } + 27240 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000000400000001fffff44000000 + 27240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003d30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 27240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003d30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 27240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:481 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2724 +instret:482 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2724 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 45 <= 0000000000000001000000001fffff44000000 +[RFile] wr_ 1: r 65 <= 0000000000000008000000001fffff44000000 + 27250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 27250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014f8 +After delta: vaddr = 0x800014f8 + 27250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:483 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2725 +instret:484 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 2725 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 57 <= 000000002000053e000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d28, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 27260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014f8, write: False, capStore: False, potentialCapLoad: False } + 27260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 27260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 43 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27270 : [doFinishMem] DTlbResp { resp: <'h00000000800014f8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014f8, check_high: 'h000000000800014fc, check_inclusive: True } }, specBits: 'h000 } + 27270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h00000000800014f8, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 27270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 27270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 27270 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } + 27270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:485 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2727 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h4bc, localHist: 'h3ea, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 67 <= 0000000020000f40000000001fffff44000000 + 27280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 27280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27280 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5c <= 0000000000000000400000001fffff44000000 + 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 27280 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 27280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:486 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 2728 +instret:487 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 2728 +calling cycle +[RFile] wr_ 0: r 5a <= 0000000020000f48000000001fffff44000000 + 27290 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 0000000000000019000000001fffff44000000 + 27290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 27290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 27290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 27290 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } + 27290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003d28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +instret:488 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 2729 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h00000000800014f8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 27300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27300 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 54 <= 0000000000000000400000001fffff44000000 + 27300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003d28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 27300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003d28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 27310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 27310 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } + 27310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:489 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 2731 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5f <= 0000000000000000c00000001fffff44000000 + 27320 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 0000000000000000400000001fffff44000000 + 27320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 27320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4c <= 0000000000000000800000001fffff44000000 + 27330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 27330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 27340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 27340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h25e, localHist: 'h3d5, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h4; InstTag { way: 'h0, ptr: 'h18, t: 'h30 } + 27350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h010 } + 27350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h011 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 27350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +calling cycle +[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h18, t: 'h30 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 27370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 27370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 27370 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } + 27370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 27380 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 27430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 27440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, data: TaggedData { tag: False, data: } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6c <= 0000000020000484000000001fffff44000000 + 27450 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000000000000800000001fffff44000000 + 27450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6a <= 000000002000053d000000001fffff44000000 + 27460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 27470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6f <= 0000000000000002000000001fffff44000000 + 27480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 27480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014fc +After delta: vaddr = 0x800014fc + 27480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 61 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 75 <= 000000002000053f000000001fffff44000000 + 27490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014fc, write: False, capStore: False, potentialCapLoad: False } + 27490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 27490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 27490 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 27490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 05 <= 0000000020000f20000000001fffff44000000 + 27500 : [doFinishMem] DTlbResp { resp: <'h00000000800014fc,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014fc, check_high: 'h00000000080001500, check_inclusive: True } }, specBits: 'h000 } + 27500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h00000000800014fc, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27500 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000000400000001fffff44000000 + 27500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 27500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4e <= 0000000000000010000000001fffff44000000 +[RFile] wr_ 2: r 60 <= 0000000000000000000000001fffff44000000 + 27510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 27510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 27510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 27510 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } + 27510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 27510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27520 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 27520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27520 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 66 <= 0000000000000064000000001fffff44000000 + 27520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 27520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 27520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } +instret:490 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 2752 +instret:491 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 2752 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5b <= 0000000000000020000000001fffff44000000 + 27530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 27530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 27530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 27530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 27530 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 27530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d20 +After delta: vaddr = 0x80003d20 + 27530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } +instret:492 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 2753 +instret:493 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 2753 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5e <= 0000000020000f40000000001fffff44000000 + 27540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 27540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 27540 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000006000000001fffff44000000 + 27540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d20, write: True, capStore: False, potentialCapLoad: False } + 27540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 27540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 27540 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } + 27540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d50 +After delta: vaddr = 0x80003d50 + 27540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:494 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 2754 +instret:495 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 2754 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 64 <= 0000000020000f50000000001fffff44000000 + 27550 : [doFinishMem] DTlbResp { resp: <'h0000000080003d20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d20, check_high: 'h00000000080003d28, check_inclusive: True } }, specBits: 'h000 } + 27550 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000000000000400000001fffff44000000 + 27550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080003d40 o: 'h0000000080003d40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000190 o: 'h0000000000000190 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d50 o: 'h0000000080003d50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d50, write: True, capStore: False, potentialCapLoad: False } + 27550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 27550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27560 : [doFinishMem] DTlbResp { resp: <'h0000000080003d50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d50 o: 'h0000000080003d50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d50, check_high: 'h00000000080003d54, check_inclusive: True } }, specBits: 'h000 } + 27560 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6e <= 0000000000000000800000001fffff44000000 + 27560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 27560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:496 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2756 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27570 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d20, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 27570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 27570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 44 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 27580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 27580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 27580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 27580 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 27580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 27580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003d20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +instret:497 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 2758 +instret:498 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 2758 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 73 <= 0000000020000f40000000001fffff44000000 + 27590 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000000000005000000001fffff44000000 + 27590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 27590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003d20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 27590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003d20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:499 PC:0x1ffff0000000000000000000080000272 instr:0x02a0006f iType:J [doCommitNormalInst [0]] 2759 +instret:500 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [1]] 2759 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0b <= 0000000000000010000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 27600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 27600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27600 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0d <= 0000000000000000800000001fffff44000000 + 27600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d48 +After delta: vaddr = 0x80003d48 + 27600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:501 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [0]] 2760 +instret:502 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [1]] 2760 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'ha5e, localHist: 'h0fa, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 79 <= 0000000020000f50000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080003d40 o: 'h0000000080003d40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d48 o: 'h0000000080003d48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d48, write: True, capStore: False, potentialCapLoad: False } + 27610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 27610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 27610 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } + 27610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:503 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [0]] 2761 +instret:504 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [1]] 2761 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h00000000800014fc, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27620 : [doFinishMem] DTlbResp { resp: <'h0000000080003d48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d48 o: 'h0000000080003d48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d48, check_high: 'h00000000080003d50, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 27620 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 72 <= 0000000000000000400000001fffff44000000 + 27620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 27620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 76 <= 0000000000000002000000001fffff44000000 +[RFile] wr_ 1: r 69 <= 0000000000000010000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014fc +After delta: vaddr = 0x800014fc + 27630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 62 <= 000000002000053f000000001fffff44000000 + 27640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 27640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014fc, write: False, capStore: False, potentialCapLoad: False } + 27640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 27640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 51 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27650 : [doFinishMem] DTlbResp { resp: <'h00000000800014fc,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014fc, check_high: 'h00000000080001500, check_inclusive: True } }, specBits: 'h000 } + 27650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h00000000800014fc, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 27650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 27650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 27650 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 27650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h52f, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 78 <= 0000000020000f40000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 27660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27660 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000000400000001fffff44000000 + 27660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 27660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 27660 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } + 27660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 27660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +calling cycle +calling cycle + 27680 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 27680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 27680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 27680 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 27680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 27690 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h297, localHist: 'h3be, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 27750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5f <= 0000000000000000c00000001fffff44000000 + 27770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 27770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 27780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 27780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 27780 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } + 27780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27790 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 0000000000000000800000001fffff44000000 + 27790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 27800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h14b, localHist: 'h3d5, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 27810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 27810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 27810 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } + 27810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +instret:505 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 2781 +instret:506 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 2781 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000204; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } + 27820 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6f <= 0000000000000000400000001fffff44000000 + 27820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:507 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2784 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 27900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 27910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6c <= 0000000020000484000000001fffff44000000 + 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 27920 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } + 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:508 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2792 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6a <= 000000002000053d000000001fffff44000000 + 27930 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000000000000800000001fffff44000000 + 27930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 27950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 27950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:509 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2795 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 61 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 6f <= 0000000000000002000000001fffff44000000 + 27960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 27960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 27960 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 27960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014fc +After delta: vaddr = 0x800014fc + 27960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 75 <= 000000002000053f000000001fffff44000000 + 27970 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000000400000001fffff44000000 + 27970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014fc, write: False, capStore: False, potentialCapLoad: False } + 27970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 27970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:510 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 2797 +instret:511 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2797 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 05 <= 0000000020000f20000000001fffff44000000 + 27980 : [doFinishMem] DTlbResp { resp: <'h00000000800014fc,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014fc, check_high: 'h00000000080001500, check_inclusive: True } }, specBits: 'h000 } + 27980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h00000000800014fc, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 27980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 27980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:512 PC:0x1ffff0000000000000000000080000214 instr:0x2e458693 iType:Alu [doCommitNormalInst [0]] 2798 +instret:513 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 2798 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4e <= 0000000000000010000000001fffff44000000 + 27990 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 27990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 27990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 27990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 27990 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } + 27990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 27990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5b <= 0000000000000020000000001fffff44000000 + 28000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 28000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28000 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 66 <= 0000000000000064000000001fffff44000000 + 28000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 28000 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5e <= 0000000020000f40000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h00000000800014fc, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 28010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28010 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000006000000001fffff44000000 + 28010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 28010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 28010 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } + 28010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d50 +After delta: vaddr = 0x80003d50 + 28010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 64 <= 0000000020000f50000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28020 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000000000000400000001fffff44000000 + 28020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080003d40 o: 'h0000000080003d40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000190 o: 'h0000000000000190 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d50 o: 'h0000000080003d50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d50, write: True, capStore: False, potentialCapLoad: False } + 28020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 28020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 28020 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 28020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 28020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:514 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2802 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28030 : [doFinishMem] DTlbResp { resp: <'h0000000080003d50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d50 o: 'h0000000080003d50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d50, check_high: 'h00000000080003d54, check_inclusive: True } }, specBits: 'h000 } + 28030 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6e <= 0000000000000000800000001fffff44000000 + 28030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 28030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:515 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 2803 +instret:516 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 2803 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28040 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 28040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 28040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:517 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 2804 +instret:518 PC:0x1ffff0000000000000000000080000228 instr:0xa5c58593 iType:Alu [doCommitNormalInst [1]] 2804 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 44 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 28050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 28050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 28050 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 28050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 28050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:519 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 2805 +instret:520 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2805 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 73 <= 0000000020000f40000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28060 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000000000005000000001fffff44000000 + 28060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 28060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 28060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 28060 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } } + 28060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:521 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2806 +instret:522 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 2806 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0b <= 0000000000000010000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 28070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28070 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0d <= 0000000000000000800000001fffff44000000 + 28070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d48 +After delta: vaddr = 0x80003d48 + 28070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:523 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2807 +instret:524 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 2807 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h94b, localHist: 'h0fa, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 79 <= 0000000020000f50000000001fffff44000000 + 28080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080003d40 o: 'h0000000080003d40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d48 o: 'h0000000080003d48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d48, write: True, capStore: False, potentialCapLoad: False } + 28080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 28080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 28080 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } + 28080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003d50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:525 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 2808 +instret:526 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 2808 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28090 : [doFinishMem] DTlbResp { resp: <'h0000000080003d48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d48 o: 'h0000000080003d48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d48, check_high: 'h00000000080003d50, check_inclusive: True } }, specBits: 'h000 } + 28090 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 72 <= 0000000000000000400000001fffff44000000 + 28090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003d50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 28090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003d50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 28090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 28090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:527 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2809 +instret:528 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2809 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 76 <= 0000000000000002000000001fffff44000000 +[RFile] wr_ 1: r 69 <= 0000000000000010000000001fffff44000000 + 28100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 28100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014fc +After delta: vaddr = 0x800014fc + 28100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:529 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2810 +instret:530 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 2810 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 62 <= 000000002000053f000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 28110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014fc, write: False, capStore: False, potentialCapLoad: False } + 28110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 51 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28120 : [doFinishMem] DTlbResp { resp: <'h00000000800014fc,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014fc, check_high: 'h00000000080001500, check_inclusive: True } }, specBits: 'h000 } + 28120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h00000000800014fc, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 28120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 28120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 28120 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 28120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:531 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2812 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h4a5, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 78 <= 0000000020000f40000000001fffff44000000 + 28130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 28130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28130 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000000400000001fffff44000000 + 28130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 28130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 28130 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } + 28130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:532 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 2813 +instret:533 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 2813 +calling cycle +[RFile] wr_ 0: r 46 <= 0000000020000f50000000001fffff44000000 + 28140 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 02 <= 0000000000000064000000001fffff44000000 + 28140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 28140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 28140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 28140 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 28140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080003d48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +instret:534 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 2814 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h00000000800014fc, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 28150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28150 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 0000000000000000800000001fffff44000000 + 28150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080003d48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 28150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080003d48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 28150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 28160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 28160 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } + 28160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28160 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080003dd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:535 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 2816 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 74 <= 0000000000000000c00000001fffff44000000 + 28170 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000000000000800000001fffff44000000 + 28170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080003dd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 28170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28170 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080003dc8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0e <= 0000000000000000c00000001fffff44000000 + 28180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080003dc8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 28180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28190 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080003dd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080003dd0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 28190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 28190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 28190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h252, localHist: 'h3d5, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h4; InstTag { way: 'h0, ptr: 'h18, t: 'h30 } + 28200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h010 } + 28200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h011 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 28200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +calling cycle +[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h18, t: 'h30 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 28220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 28220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 28220 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 28220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 28230 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 28280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 28290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 08 <= 0000000020000484000000001fffff44000000 + 28300 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 0000000000000000c00000001fffff44000000 + 28300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 53 <= 000000002000053d000000001fffff44000000 + 28310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 28320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4f <= 0000000000000003000000001fffff44000000 + 28330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 28330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001500 +After delta: vaddr = 0x80001500 + 28330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5d <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 67 <= 0000000020000540000000001fffff44000000 + 28340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001500, write: False, capStore: False, potentialCapLoad: False } + 28340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 28340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 28340 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } + 28340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 42 <= 0000000020000f20000000001fffff44000000 + 28350 : [doFinishMem] DTlbResp { resp: <'h0000000080001500,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001500, check_high: 'h00000000080001504, check_inclusive: True } }, specBits: 'h000 } + 28350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080001500, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28350 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 60 <= 0000000000000000400000001fffff44000000 + 28350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 28350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 54 <= 0000000000000018000000001fffff44000000 +[RFile] wr_ 2: r 7d <= 0000000000000000000000001fffff44000000 + 28360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 28360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 28360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 28360 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } + 28360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 28360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28370 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 28370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28370 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6b <= 0000000000000190000000001fffff44000000 + 28370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 28370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } +instret:536 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 2837 +instret:537 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 2837 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 55 <= 0000000000000020000000001fffff44000000 + 28380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 28380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 28380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 28380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 28380 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } + 28380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d40 +After delta: vaddr = 0x80003d40 + 28380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } +instret:538 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 2838 +instret:539 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 2838 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5c <= 0000000020000f40000000001fffff44000000 + 28390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 28390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 28390 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5a <= 0000000000000006000000001fffff44000000 + 28390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080003d40 o: 'h0000000080003d40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d40 o: 'h0000000080003d40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d40, write: True, capStore: False, potentialCapLoad: False } + 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 28390 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } + 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d70 +After delta: vaddr = 0x80003d70 + 28390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28390 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:540 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 2839 +instret:541 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 2839 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4b <= 0000000020000f58000000001fffff44000000 + 28400 : [doFinishMem] DTlbResp { resp: <'h0000000080003d40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d40 o: 'h0000000080003d40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d40, check_high: 'h00000000080003d48, check_inclusive: True } }, specBits: 'h000 } + 28400 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4c <= 0000000000000000400000001fffff44000000 + 28400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080003d60 o: 'h0000000080003d60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000640 o: 'h0000000000000640 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d70 o: 'h0000000080003d70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d70, write: True, capStore: False, potentialCapLoad: False } + 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 28400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28410 : [doFinishMem] DTlbResp { resp: <'h0000000080003d70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d70 o: 'h0000000080003d70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d70, check_high: 'h00000000080003d74, check_inclusive: True } }, specBits: 'h000 } + 28410 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 45 <= 0000000000000000c00000001fffff44000000 + 28410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 28410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:542 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2841 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28420 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 28420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 28420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 56 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 28430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 28430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 28430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 28430 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } + 28430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 28430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003d40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +instret:543 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 2843 +instret:544 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 2843 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7b <= 0000000020000f40000000001fffff44000000 + 28440 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6f <= 0000000000000005000000001fffff44000000 + 28440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 28440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003d40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 28440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003d40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 28440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:545 PC:0x1ffff0000000000000000000080000272 instr:0x02a0006f iType:J [doCommitNormalInst [0]] 2844 +instret:546 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [1]] 2844 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5f <= 0000000000000018000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 28450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 28450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28450 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000000c00000001fffff44000000 + 28450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d68 +After delta: vaddr = 0x80003d68 + 28450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:547 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [0]] 2845 +instret:548 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [1]] 2845 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'ha52, localHist: 'h07d, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 52 <= 0000000020000f58000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080003d60 o: 'h0000000080003d60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d68 o: 'h0000000080003d68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d68, write: True, capStore: False, potentialCapLoad: False } + 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 28460 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28460 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080003dc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:549 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [0]] 2846 +instret:550 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [1]] 2846 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080001500, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28470 : [doFinishMem] DTlbResp { resp: <'h0000000080003d68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d68 o: 'h0000000080003d68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d68, check_high: 'h00000000080003d70, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 28470 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000000000000400000001fffff44000000 + 28470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080003dc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 28470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 28470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6c <= 0000000000000003000000001fffff44000000 +[RFile] wr_ 1: r 68 <= 0000000000000018000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 28480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 28480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 28480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001500 +After delta: vaddr = 0x80001500 + 28480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 65 <= 0000000020000540000000001fffff44000000 + 28490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 28490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001500, write: False, capStore: False, potentialCapLoad: False } + 28490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 70 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28500 : [doFinishMem] DTlbResp { resp: <'h0000000080001500,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001500, check_high: 'h00000000080001504, check_inclusive: True } }, specBits: 'h000 } + 28500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080001500, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 28500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 28500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 28500 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } + 28500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h529, localHist: 'h3fa, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5e <= 0000000020000f40000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 28510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28510 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000000000000400000001fffff44000000 + 28510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 28510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 28510 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 28510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +calling cycle +calling cycle + 28530 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 28530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 28530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 28530 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } + 28530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28530 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +calling cycle + 28540 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 28540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h294, localHist: 'h3df, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 28600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 74 <= 0000000000000000c00000001fffff44000000 + 28620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 28620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 28630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 28630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 28630 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } + 28630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28640 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000000000000c00000001fffff44000000 + 28640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 28650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h14a, localHist: 'h3d5, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 28660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 28660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 28660 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 28660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +instret:551 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 2866 +instret:552 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 2866 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28670 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080003dd0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +[ALU redirect - 1] 'h1ffff0000000000000000000080000204; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } + 28670 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000000400000001fffff44000000 + 28670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 28690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28690 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 28690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080003dd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:553 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2869 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 28750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 28760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 08 <= 0000000020000484000000001fffff44000000 + 28770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 28770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 28770 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 28770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:554 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2877 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 53 <= 000000002000053d000000001fffff44000000 + 28780 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 0000000000000000c00000001fffff44000000 + 28780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 28800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 28800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:555 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2880 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5d <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 4f <= 0000000000000003000000001fffff44000000 + 28810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 28810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 28810 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } + 28810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001500 +After delta: vaddr = 0x80001500 + 28810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 67 <= 0000000020000540000000001fffff44000000 + 28820 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 60 <= 0000000000000000400000001fffff44000000 + 28820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001500, write: False, capStore: False, potentialCapLoad: False } + 28820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 28820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:556 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 2882 +instret:557 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2882 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 42 <= 0000000020000f20000000001fffff44000000 + 28830 : [doFinishMem] DTlbResp { resp: <'h0000000080001500,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001500, check_high: 'h00000000080001504, check_inclusive: True } }, specBits: 'h000 } + 28830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080001500, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 28830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 28830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:558 PC:0x1ffff0000000000000000000080000214 instr:0x2e458693 iType:Alu [doCommitNormalInst [0]] 2883 +instret:559 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 2883 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 54 <= 0000000000000018000000001fffff44000000 + 28840 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 28840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 28840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 28840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 28840 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } + 28840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 55 <= 0000000000000020000000001fffff44000000 + 28850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 28850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28850 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6b <= 0000000000000190000000001fffff44000000 + 28850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 28850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 28850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 28850 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } + 28850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5c <= 0000000020000f40000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080001500, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 28860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28860 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5a <= 0000000000000006000000001fffff44000000 + 28860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 28860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 28860 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } + 28860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d70 +After delta: vaddr = 0x80003d70 + 28860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4b <= 0000000020000f58000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28870 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4c <= 0000000000000000400000001fffff44000000 + 28870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080003d60 o: 'h0000000080003d60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000640 o: 'h0000000000000640 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d70 o: 'h0000000080003d70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d70, write: True, capStore: False, potentialCapLoad: False } + 28870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 28870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 28870 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } } + 28870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 28870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:560 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2887 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28880 : [doFinishMem] DTlbResp { resp: <'h0000000080003d70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d70 o: 'h0000000080003d70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d70, check_high: 'h00000000080003d74, check_inclusive: True } }, specBits: 'h000 } + 28880 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 45 <= 0000000000000000c00000001fffff44000000 + 28880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 28880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:561 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 2888 +instret:562 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 2888 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28890 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 28890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 28890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:563 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 2889 +instret:564 PC:0x1ffff0000000000000000000080000228 instr:0xa5c58593 iType:Alu [doCommitNormalInst [1]] 2889 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 56 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 28900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 28900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 28900 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } + 28900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 28900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:565 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 2890 +instret:566 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2890 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7b <= 0000000020000f40000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28910 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6f <= 0000000000000005000000001fffff44000000 + 28910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 28910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 28910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 28910 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } + 28910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:567 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2891 +instret:568 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 2891 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5f <= 0000000000000018000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d70, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 28920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28920 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000000c00000001fffff44000000 + 28920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d68 +After delta: vaddr = 0x80003d68 + 28920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:569 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2892 +instret:570 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 2892 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h94a, localHist: 'h07d, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 52 <= 0000000020000f58000000001fffff44000000 + 28930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080003d60 o: 'h0000000080003d60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d68 o: 'h0000000080003d68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d68, write: True, capStore: False, potentialCapLoad: False } + 28930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 28930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 28930 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 28930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080003d70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:571 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 2893 +instret:572 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 2893 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28940 : [doFinishMem] DTlbResp { resp: <'h0000000080003d68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d68 o: 'h0000000080003d68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d68, check_high: 'h00000000080003d70, check_inclusive: True } }, specBits: 'h000 } + 28940 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000000000000400000001fffff44000000 + 28940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080003d70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 28940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080003d70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 28940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 28940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:573 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2894 +instret:574 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2894 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6c <= 0000000000000003000000001fffff44000000 +[RFile] wr_ 1: r 68 <= 0000000000000018000000001fffff44000000 + 28950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 28950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001500 +After delta: vaddr = 0x80001500 + 28950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:575 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2895 +instret:576 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 2895 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 65 <= 0000000020000540000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d68, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 28960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001500, write: False, capStore: False, potentialCapLoad: False } + 28960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 70 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28970 : [doFinishMem] DTlbResp { resp: <'h0000000080001500,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001500, check_high: 'h00000000080001504, check_inclusive: True } }, specBits: 'h000 } + 28970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080001500, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 28970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 28970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 28970 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } + 28970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:577 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2897 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h4a5, localHist: 'h3fa, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5e <= 0000000020000f40000000001fffff44000000 + 28980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 28980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28980 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000000000000400000001fffff44000000 + 28980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 28980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 28980 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 28980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:578 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 2898 +instret:579 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 2898 +calling cycle +[RFile] wr_ 0: r 66 <= 0000000020000f58000000001fffff44000000 + 28990 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000190000000001fffff44000000 + 28990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 28990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 28990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 28990 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } + 28990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003d68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +instret:580 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 2899 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080001500, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 29000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29000 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000000000000000c00000001fffff44000000 + 29000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003d68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 29000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003d68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 29000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 29010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 29010 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } + 29010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:581 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 2901 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6a <= 0000000000000000c00000001fffff44000000 + 29020 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0b <= 0000000000000000c00000001fffff44000000 + 29020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 29020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7c <= 0000000000000001000000001fffff44000000 + 29030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 29030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 29040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 29040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h252, localHist: 'h3d5, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h4; InstTag { way: 'h0, ptr: 'h18, t: 'h30 } + 29050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h010 } + 29050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h011 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 29050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +calling cycle +[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h18, t: 'h30 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 29070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 29070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 29070 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } + 29070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 29080 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 29120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 29130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 29140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 29140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: False, data: } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 05 <= 0000000020000484000000001fffff44000000 + 29150 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 02 <= 0000000000000001000000001fffff44000000 + 29150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0d <= 000000002000053d000000001fffff44000000 + 29160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 29170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 72 <= 0000000000000004000000001fffff44000000 + 29180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 29180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001504 +After delta: vaddr = 0x80001504 + 29180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 40 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 78 <= 0000000020000541000000001fffff44000000 + 29190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080001504 o: 'h0000000080001504 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001504 o: 'h0000000080001504 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001504, write: False, capStore: False, potentialCapLoad: False } + 29190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 29190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 29190 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } + 29190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 50 <= 0000000020000f20000000001fffff44000000 + 29200 : [doFinishMem] DTlbResp { resp: <'h0000000080001504,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001504 o: 'h0000000080001504 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001504, check_high: 'h00000000080001508, check_inclusive: True } }, specBits: 'h000 } + 29200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080001504, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29200 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7d <= 0000000000000000400000001fffff44000000 + 29200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 29200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080001504, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 47 <= 0000000000000020000000001fffff44000000 +[RFile] wr_ 2: r 61 <= 0000000000000000000000001fffff44000000 + 29210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 29210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080001504, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 29210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080001504, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 29210 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } + 29210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 29210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 29220 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 29220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29220 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000000000000000000001fffff44000000 + 29220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 29220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 29220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } +instret:582 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 2922 +instret:583 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 2922 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 49 <= 0000000000000020000000001fffff44000000 + 29230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 29230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 29230 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d60 +After delta: vaddr = 0x80003d60 + 29230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } +instret:584 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 2923 +instret:585 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 2923 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0c <= 0000000020000f40000000001fffff44000000 + 29240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 29240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 29240 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 0000000000000006000000001fffff44000000 + 29240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080003d60 o: 'h0000000080003d60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d60 o: 'h0000000080003d60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d60, write: True, capStore: False, potentialCapLoad: False } + 29240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 29240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 29240 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } } + 29240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d90 +After delta: vaddr = 0x80003d90 + 29240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:586 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 2924 +instret:587 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 2924 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 01 <= 0000000020000f60000000001fffff44000000 + 29250 : [doFinishMem] DTlbResp { resp: <'h0000000080003d60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d60 o: 'h0000000080003d60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d60, check_high: 'h00000000080003d68, check_inclusive: True } }, specBits: 'h000 } + 29250 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0e <= 0000000000000000400000001fffff44000000 + 29250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080003d80 o: 'h0000000080003d80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d90 o: 'h0000000080003d90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d90, write: True, capStore: False, potentialCapLoad: False } + 29250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 29250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 29260 : [doFinishMem] DTlbResp { resp: <'h0000000080003d90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d90 o: 'h0000000080003d90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d90, check_high: 'h00000000080003d94, check_inclusive: True } }, specBits: 'h000 } + 29260 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000001000000001fffff44000000 + 29260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 29260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:588 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2926 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29270 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 29270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 29270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 57 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 29280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 29280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 29280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 29280 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 29280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 29280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003d60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +instret:589 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 2928 +instret:590 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 2928 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4d <= 0000000020000f40000000001fffff44000000 + 29290 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000005000000001fffff44000000 + 29290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 29290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003d60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 29290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003d60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 29290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:591 PC:0x1ffff0000000000000000000080000272 instr:0x02a0006f iType:J [doCommitNormalInst [0]] 2929 +instret:592 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [1]] 2929 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 74 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 29300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 29300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29300 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 67 <= 0000000000000001000000001fffff44000000 + 29300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d88 +After delta: vaddr = 0x80003d88 + 29300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:593 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [0]] 2930 +instret:594 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [1]] 2930 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'ha52, localHist: 'h03e, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7f <= 0000000020000f60000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080003d80 o: 'h0000000080003d80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d88 o: 'h0000000080003d88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d88, write: True, capStore: False, potentialCapLoad: False } + 29310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 29310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 29310 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } + 29310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:595 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [0]] 2931 +instret:596 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [1]] 2931 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080001504, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29320 : [doFinishMem] DTlbResp { resp: <'h0000000080003d88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d88 o: 'h0000000080003d88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d88, check_high: 'h00000000080003d90, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 29320 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 55 <= 0000000000000000400000001fffff44000000 + 29320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 29320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 08 <= 0000000000000004000000001fffff44000000 +[RFile] wr_ 1: r 41 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 29330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 29330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 29330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001504 +After delta: vaddr = 0x80001504 + 29330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 69 <= 0000000020000541000000001fffff44000000 + 29340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 29340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080001504 o: 'h0000000080001504 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001504 o: 'h0000000080001504 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001504, write: False, capStore: False, potentialCapLoad: False } + 29340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 29340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4a <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29350 : [doFinishMem] DTlbResp { resp: <'h0000000080001504,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001504 o: 'h0000000080001504 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001504, check_high: 'h00000000080001508, check_inclusive: True } }, specBits: 'h000 } + 29350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080001504, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 29350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 29350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 29350 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } + 29350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080001504, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h529, localHist: 'h3fd, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5c <= 0000000020000f40000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 29360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29360 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4c <= 0000000000000000400000001fffff44000000 + 29360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080001504, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 29360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080001504, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 29360 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } + 29360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 29360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +calling cycle +calling cycle + 29380 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 29380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 29380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 29380 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } + 29380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 29390 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h294, localHist: 'h3ef, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 29450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6a <= 0000000000000000c00000001fffff44000000 + 29470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 29470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 29480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 29480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 29480 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } + 29480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29490 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0b <= 0000000000000001000000001fffff44000000 + 29490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 29500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h14a, localHist: 'h3d5, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 29510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 29510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 29510 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } + 29510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +instret:597 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 2951 +instret:598 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 2951 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29520 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 72 <= 0000000000000000400000001fffff44000000 + 29520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7d <= 0000000000000000800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h008 } + 29530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } +instret:599 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2953 +instret:600 PC:0x1ffff0000000000000000000080000200 instr:0x0ae0006f iType:J [doCommitNormalInst [1]] 2953 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 29540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 29540 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } + 29540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 29540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:601 PC:0x1ffff00000000000000000000800002ae instr:0x0040006f iType:J [doCommitNormalInst [0]] 2954 +instret:602 PC:0x1ffff00000000000000000000800002b2 instr:0xfcc42503 iType:Ld [doCommitNormalInst [1]] 2954 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h8a5, localHist: 'h3ef, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 05 <= 0000000000000000800000001fffff44000000 + 29550 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000000000000400000001fffff44000000 + 29550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: True, capStore: False, potentialCapLoad: False } + 29550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 29550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 50 <= 0000000000000000000000001fffff44000000 + 29560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 29560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 29560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h012 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:603 PC:0x1ffff00000000000000000000800002b6 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 2956 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h002 } + 29570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 29570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:604 PC:0x1ffff00000000000000000000800002b8 instr:0xfca42623 iType:St [doCommitNormalInst [0]] 2957 +instret:605 PC:0x1ffff00000000000000000000800002bc instr:0xf1fff06f iType:J [doCommitNormalInst [1]] 2957 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 58 <= 0000000000000000c00000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 29580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82b8 } + 29580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 29580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 29580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29590 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000000000000000000001fffff44000000 + 29590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 29590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } + 29590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 29590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h452, localHist: 'h3d5, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 29600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 29600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h011 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 29610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 29610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 29610 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 29610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h0; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } + 29620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h011 } + 29620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29620 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 0000000000000000800000001fffff44000000 + 29620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 29640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 29640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 29640 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 29640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle + 29660 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hc52, localHist: 'h3ea, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 29730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +calling cycle + 29740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[RFile] wr_ 1: r 7d <= 0000000000000000800000001fffff44000000 + 29750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 29750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 29760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 29760 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } + 29760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 29770 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000000000000800000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h629, localHist: 'h2aa, globalTaken: True, localTaken: True, pcIndex: 'h169 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 29790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:606 PC:0x1ffff00000000000000000000800001da instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 2979 +instret:607 PC:0x1ffff00000000000000000000800001de instr:0x00004509 iType:Alu [doCommitNormalInst [1]] 2979 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 50 <= 0000000000000000000000001fffff44000000 +[ALU redirect - 1] 'h1ffff00000000000000000000800001e8; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } + 29800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: True, capStore: False, potentialCapLoad: False } + 29800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 29800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:608 PC:0x1ffff00000000000000000000800001e0 instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2982 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 29880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'he29, localHist: 'h3f7, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 50 <= 0000000000000000000000001fffff44000000 + 29890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 29890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +calling cycle + 29900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 29900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +instret:609 PC:0x1ffff00000000000000000000800001e8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2990 +instret:610 PC:0x1ffff00000000000000000000800001ec instr:0x00004501 iType:Alu [doCommitNormalInst [1]] 2990 +calling cycle +[RFile] wr_ 1: r 58 <= 0000000000000000c00000001fffff44000000 + 29910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 29910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, data: TaggedData { tag: False, data: } } +instret:611 PC:0x1ffff00000000000000000000800001ee instr:0xfca42423 iType:St [doCommitNormalInst [0]] 2991 +instret:612 PC:0x1ffff00000000000000000000800001f2 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2991 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81ee } + 29920 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000000000000000000001fffff44000000 + 29920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ee } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ee } + 29930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ee } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 29930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:613 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 2994 +instret:614 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 2994 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h2; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } + 29950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +calling cycle +[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:615 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2997 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 30020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 30030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 30040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 30040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 76 <= 0000000020000484000000001fffff44000000 + 30050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 30050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 30050 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } + 30050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:616 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3005 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 74 <= 000000002000053d000000001fffff44000000 + 30060 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 57 <= 0000000000000000000000001fffff44000000 + 30060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 30080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 30080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:617 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 3008 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 08 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 4d <= 0000000000000000000000001fffff44000000 + 30090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 30090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 30090 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 30090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014f4 +After delta: vaddr = 0x800014f4 + 30090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7f <= 000000002000053d000000001fffff44000000 + 30100 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000000800000001fffff44000000 + 30100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h00000000800014f4 o: 'h00000000800014f4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014f4 o: 'h00000000800014f4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014f4, write: False, capStore: False, potentialCapLoad: False } + 30100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 30100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:618 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 3010 +instret:619 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 3010 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 69 <= 0000000020000f20000000001fffff44000000 + 30110 : [doFinishMem] DTlbResp { resp: <'h00000000800014f4,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014f4 o: 'h00000000800014f4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014f4, check_high: 'h000000000800014f8, check_inclusive: True } }, specBits: 'h000 } + 30110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h00000000800014f4, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 30110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 30110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800014f4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:620 PC:0x1ffff0000000000000000000080000214 instr:0x2e458693 iType:Alu [doCommitNormalInst [0]] 3011 +instret:621 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 3011 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5d <= 0000000000000000000000001fffff44000000 + 30120 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 30120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 30120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800014f4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 30120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800014f4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 30120 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 30120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 30120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 67 <= 0000000000000040000000001fffff44000000 + 30130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 30130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30130 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 0000000000000006400000001fffff44000000 + 30130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 30130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 30130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 30130 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } + 30130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 60 <= 0000000020000f60000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h00000000800014f4, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 30140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30140 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5c <= 0000000000000006000000001fffff44000000 + 30140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 30140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 30140 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } + 30140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d90 +After delta: vaddr = 0x80003d90 + 30140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 55 <= 0000000020000f60000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30150 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 41 <= 0000000000000000800000001fffff44000000 + 30150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080003d80 o: 'h0000000080003d80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000019 o: 'h0000000000000019 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d90 o: 'h0000000080003d90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d90, write: True, capStore: False, potentialCapLoad: False } + 30150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 30150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 30150 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } + 30150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 30150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:622 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 3015 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 30160 : [doFinishMem] DTlbResp { resp: <'h0000000080003d90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d90 o: 'h0000000080003d90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d90, check_high: 'h00000000080003d94, check_inclusive: True } }, specBits: 'h000 } + 30160 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4c <= 0000000000000000000000001fffff44000000 + 30160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 30160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:623 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 3016 +instret:624 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 3016 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30170 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 30170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 30170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:625 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 3017 +instret:626 PC:0x1ffff0000000000000000000080000228 instr:0xa5c58593 iType:Alu [doCommitNormalInst [1]] 3017 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6b <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 30180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 30180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 30180 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } + 30180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 30180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:627 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 3018 +instret:628 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 3018 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4b <= 0000000020000f60000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30190 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7b <= 0000000000000005000000001fffff44000000 + 30190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 30190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 30190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 30190 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } + 30190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:629 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 3019 +instret:630 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 3019 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 56 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 30200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30200 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 43 <= 0000000000000000000000001fffff44000000 + 30200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d88 +After delta: vaddr = 0x80003d88 + 30200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:631 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3020 +instret:632 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 3020 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf14, localHist: 'h03e, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 54 <= 0000000020000f60000000001fffff44000000 + 30210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080003d80 o: 'h0000000080003d80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d88 o: 'h0000000080003d88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d88, write: True, capStore: False, potentialCapLoad: False } + 30210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 30210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 30210 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } + 30210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003d90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:633 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 3021 +instret:634 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 3021 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30220 : [doFinishMem] DTlbResp { resp: <'h0000000080003d88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d88 o: 'h0000000080003d88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d88, check_high: 'h00000000080003d90, check_inclusive: True } }, specBits: 'h000 } + 30220 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 65 <= 0000000000000000800000001fffff44000000 + 30220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003d90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 30220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003d90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 30220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 30220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:635 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 3022 +instret:636 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 3022 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5a <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 5b <= 0000000000000000000000001fffff44000000 + 30230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 30230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014f4 +After delta: vaddr = 0x800014f4 + 30230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:637 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 3023 +instret:638 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 3023 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 52 <= 000000002000053d000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 30240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h00000000800014f4 o: 'h00000000800014f4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014f4 o: 'h00000000800014f4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014f4, write: False, capStore: False, potentialCapLoad: False } + 30240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 30240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6f <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30250 : [doFinishMem] DTlbResp { resp: <'h00000000800014f4,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014f4 o: 'h00000000800014f4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014f4, check_high: 'h000000000800014f8, check_inclusive: True } }, specBits: 'h000 } + 30250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h00000000800014f4, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 30250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 30250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 30250 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } + 30250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h00000000800014f4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:639 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 3025 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h78a, localHist: 'h3fd, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6d <= 0000000020000f60000000001fffff44000000 + 30260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 30260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30260 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5e <= 0000000000000000800000001fffff44000000 + 30260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h00000000800014f4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 30260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h00000000800014f4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 30260 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } + 30260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 30260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:640 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 3026 +instret:641 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 3026 +calling cycle +[RFile] wr_ 0: r 42 <= 0000000020000f60000000001fffff44000000 + 30270 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5f <= 0000000000000006400000001fffff44000000 + 30270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 30270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 30270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 30270 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } + 30270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003d88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +instret:642 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 3027 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h00000000800014f4, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 30280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30280 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4e <= 0000000000000000000000001fffff44000000 + 30280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003d88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 30280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003d88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 30280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 30290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 30290 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 30290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30290 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080003e10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:643 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 3029 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 0000000000000000c00000001fffff44000000 + 30300 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000000000000001fffff44000000 + 30300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080003e10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 30300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 30300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30300 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080003e08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6e <= 0000000000000000400000001fffff44000000 + 30310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 30310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080003e08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 30310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30320 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080003e10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080003e10, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 30320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 30320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 30320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h3c5, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h4; InstTag { way: 'h1, ptr: 'h1b, t: 'h37 } + 30330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h010 } + 30330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h011 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 30330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +calling cycle +[ROB incorrectSpec] 'h4 ; InstTag { way: 'h1, ptr: 'h1b, t: 'h37 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 30350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 30350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 30350 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 30350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 30360 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 30400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 30410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 30420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 30420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: False, data: } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 02 <= 0000000020000484000000001fffff44000000 + 30430 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000000400000001fffff44000000 + 30430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6a <= 000000002000053d000000001fffff44000000 + 30440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 30450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 77 <= 0000000000000001000000001fffff44000000 + 30460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 30460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014f8 +After delta: vaddr = 0x800014f8 + 30460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 05 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 72 <= 000000002000053e000000001fffff44000000 + 30470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014f8, write: False, capStore: False, potentialCapLoad: False } + 30470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 30470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 30470 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 30470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 49 <= 0000000020000f20000000001fffff44000000 + 30480 : [doFinishMem] DTlbResp { resp: <'h00000000800014f8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014f8, check_high: 'h000000000800014fc, check_inclusive: True } }, specBits: 'h000 } + 30480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h00000000800014f8, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30480 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000000000000800000001fffff44000000 + 30480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 30480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7d <= 0000000000000008000000001fffff44000000 +[RFile] wr_ 2: r 53 <= 0000000000000000000000001fffff44000000 + 30490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 30490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 30490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 30490 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } } + 30490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 30490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 30500 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 30500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30500 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0d <= 0000000000000019000000001fffff44000000 + 30500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 30500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 30500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } +instret:644 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 3050 +instret:645 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 3050 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0b <= 0000000000000040000000001fffff44000000 + 30510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 30510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 30510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 30510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 30510 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } + 30510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d80 +After delta: vaddr = 0x80003d80 + 30510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } +instret:646 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 3051 +instret:647 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 3051 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 40 <= 0000000020000f60000000001fffff44000000 + 30520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 30520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 30520 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000000000006000000001fffff44000000 + 30520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080003d80 o: 'h0000000080003d80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d80 o: 'h0000000080003d80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d80, write: True, capStore: False, potentialCapLoad: False } + 30520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 30520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 30520 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } + 30520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003db0 +After delta: vaddr = 0x80003db0 + 30520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30520 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080001538, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:648 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 3052 +instret:649 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 3052 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0c <= 0000000020000f68000000001fffff44000000 + 30530 : [doFinishMem] DTlbResp { resp: <'h0000000080003d80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d80 o: 'h0000000080003d80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d80, check_high: 'h00000000080003d88, check_inclusive: True } }, specBits: 'h000 } + 30530 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 0000000000000000800000001fffff44000000 + 30530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080003da0 o: 'h0000000080003da0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000064 o: 'h0000000000000064 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003db0 o: 'h0000000080003db0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003db0, write: True, capStore: False, potentialCapLoad: False } + 30530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080001538, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080001538, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 30530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30530 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 30540 : [doFinishMem] DTlbResp { resp: <'h0000000080003db0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003db0 o: 'h0000000080003db0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003db0, check_high: 'h00000000080003db4, check_inclusive: True } }, specBits: 'h000 } + 30540 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6c <= 0000000000000000400000001fffff44000000 + 30540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 30540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:650 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 3054 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30550 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 30550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 30550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 46 <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 30560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 30560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 30560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 30560 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 30560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 30560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003d80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +instret:651 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 3056 +instret:652 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 3056 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0e <= 0000000020000f60000000001fffff44000000 + 30570 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 0000000000000005000000001fffff44000000 + 30570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 30570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003d80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 30570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003d80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 30570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:653 PC:0x1ffff0000000000000000000080000272 instr:0x02a0006f iType:J [doCommitNormalInst [0]] 3057 +instret:654 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [1]] 3057 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 58 <= 0000000000000008000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 30580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 30580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30580 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000000000000400000001fffff44000000 + 30580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003da8 +After delta: vaddr = 0x80003da8 + 30580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:655 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [0]] 3058 +instret:656 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [1]] 3058 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbc5, localHist: 'h01f, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 01 <= 0000000020000f68000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080003da0 o: 'h0000000080003da0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003da8 o: 'h0000000080003da8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003da8, write: True, capStore: False, potentialCapLoad: False } + 30590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 30590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 30590 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } + 30590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30590 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080003e00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:657 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [0]] 3059 +instret:658 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [1]] 3059 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, paddr: 'h00000000800014f8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30600 : [doFinishMem] DTlbResp { resp: <'h0000000080003da8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003da8 o: 'h0000000080003da8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003da8, check_high: 'h00000000080003db0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 30600 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 67 <= 0000000000000000800000001fffff44000000 + 30600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080003e00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 30600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 30600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 76 <= 0000000000000001000000001fffff44000000 +[RFile] wr_ 1: r 4a <= 0000000000000008000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 30610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 30610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 30610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014f8 +After delta: vaddr = 0x800014f8 + 30610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 68 <= 000000002000053e000000001fffff44000000 + 30620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 30620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014f8, write: False, capStore: False, potentialCapLoad: False } + 30620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 30620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 57 <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30630 : [doFinishMem] DTlbResp { resp: <'h00000000800014f8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014f8, check_high: 'h000000000800014fc, check_inclusive: True } }, specBits: 'h000 } + 30630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h00000000800014f8, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 30630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 30630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 30630 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } + 30630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h5e2, localHist: 'h3fe, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 60 <= 0000000020000f60000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 30640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30640 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 41 <= 0000000000000000800000001fffff44000000 + 30640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 30640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 30640 : [Ld resp] 'h14; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 30640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 30640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +calling cycle +calling cycle + 30660 : [doRespLdMem] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 30660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 30660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 30660 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } + 30660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30660 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080001538, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +calling cycle + 30670 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 30670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080001538, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080001538, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30670 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +calling cycle + 30680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h2f1, localHist: 'h3fb, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 30730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 0000000000000000c00000001fffff44000000 + 30750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 30750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 30760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 30760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 30760 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 30760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30770 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000000400000001fffff44000000 + 30770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 30780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h178, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 30790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 30790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 30790 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 30790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +instret:659 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 3079 +instret:660 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 3079 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30800 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080003e10, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +[ALU redirect - 1] 'h1ffff0000000000000000000080000204; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } + 30800 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000000000000800000001fffff44000000 + 30800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 30820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30820 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 30820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080003e10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:661 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 3082 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 30870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 30880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 30890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 30890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 02 <= 0000000020000484000000001fffff44000000 + 30900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 30900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 30900 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 30900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:662 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3090 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6a <= 000000002000053d000000001fffff44000000 + 30910 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000000400000001fffff44000000 + 30910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 30930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 30930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:663 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 3093 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 05 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 77 <= 0000000000000001000000001fffff44000000 + 30940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 30940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 30940 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 30940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014f8 +After delta: vaddr = 0x800014f8 + 30940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 72 <= 000000002000053e000000001fffff44000000 + 30950 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000000000000800000001fffff44000000 + 30950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014f8, write: False, capStore: False, potentialCapLoad: False } + 30950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 30950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:664 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 3095 +instret:665 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 3095 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 49 <= 0000000020000f20000000001fffff44000000 + 30960 : [doFinishMem] DTlbResp { resp: <'h00000000800014f8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014f8, check_high: 'h000000000800014fc, check_inclusive: True } }, specBits: 'h000 } + 30960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h00000000800014f8, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 30960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 30960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:666 PC:0x1ffff0000000000000000000080000214 instr:0x2e458693 iType:Alu [doCommitNormalInst [0]] 3096 +instret:667 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 3096 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7d <= 0000000000000008000000001fffff44000000 + 30970 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 30970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 30970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 30970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 30970 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } } + 30970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 30970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0b <= 0000000000000040000000001fffff44000000 + 30980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 30980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30980 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0d <= 0000000000000019000000001fffff44000000 + 30980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 30980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 30980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 30980 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } + 30980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 40 <= 0000000020000f60000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, paddr: 'h00000000800014f8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 30990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30990 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000000000006000000001fffff44000000 + 30990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 30990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 30990 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } + 30990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003db0 +After delta: vaddr = 0x80003db0 + 30990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0c <= 0000000020000f68000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31000 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 0000000000000000800000001fffff44000000 + 31000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080003da0 o: 'h0000000080003da0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000064 o: 'h0000000000000064 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003db0 o: 'h0000000080003db0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003db0, write: True, capStore: False, potentialCapLoad: False } + 31000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 31000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 31000 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } + 31000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 31000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:668 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 3100 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 31010 : [doFinishMem] DTlbResp { resp: <'h0000000080003db0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003db0 o: 'h0000000080003db0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003db0, check_high: 'h00000000080003db4, check_inclusive: True } }, specBits: 'h000 } + 31010 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6c <= 0000000000000000400000001fffff44000000 + 31010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 31010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:669 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 3101 +instret:670 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 3101 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31020 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 31020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 31020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:671 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 3102 +instret:672 PC:0x1ffff0000000000000000000080000228 instr:0xa5c58593 iType:Alu [doCommitNormalInst [1]] 3102 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 46 <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 31030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 31030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 31030 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 31030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 31030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:673 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 3103 +instret:674 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 3103 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0e <= 0000000020000f60000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31040 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 0000000000000005000000001fffff44000000 + 31040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 31040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 31040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 31040 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } + 31040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:675 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 3104 +instret:676 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 3104 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 58 <= 0000000000000008000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003db0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 31050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31050 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000000000000400000001fffff44000000 + 31050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003da8 +After delta: vaddr = 0x80003da8 + 31050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:677 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3105 +instret:678 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 3105 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h978, localHist: 'h01f, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 01 <= 0000000020000f68000000001fffff44000000 + 31060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080003da0 o: 'h0000000080003da0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003da8 o: 'h0000000080003da8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003da8, write: True, capStore: False, potentialCapLoad: False } + 31060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 31060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 31060 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } + 31060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003db0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:679 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 3106 +instret:680 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 3106 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31070 : [doFinishMem] DTlbResp { resp: <'h0000000080003da8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003da8 o: 'h0000000080003da8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003da8, check_high: 'h00000000080003db0, check_inclusive: True } }, specBits: 'h000 } + 31070 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 67 <= 0000000000000000800000001fffff44000000 + 31070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003db0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 31070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003db0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 31070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 31070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:681 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 3107 +instret:682 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 3107 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 76 <= 0000000000000001000000001fffff44000000 +[RFile] wr_ 1: r 4a <= 0000000000000008000000001fffff44000000 + 31080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 31080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014f8 +After delta: vaddr = 0x800014f8 + 31080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:683 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 3108 +instret:684 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 3108 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 68 <= 000000002000053e000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003da8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 31090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014f8, write: False, capStore: False, potentialCapLoad: False } + 31090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 31090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 57 <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31100 : [doFinishMem] DTlbResp { resp: <'h00000000800014f8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014f8 o: 'h00000000800014f8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014f8, check_high: 'h000000000800014fc, check_inclusive: True } }, specBits: 'h000 } + 31100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h00000000800014f8, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 31100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 31100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 31100 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } + 31100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:685 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 3110 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h4bc, localHist: 'h3fe, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 60 <= 0000000020000f60000000001fffff44000000 + 31110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 31110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31110 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 41 <= 0000000000000000800000001fffff44000000 + 31110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 31110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h00000000800014f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 31110 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 31110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 31110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:686 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 3111 +instret:687 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 3111 +calling cycle +[RFile] wr_ 0: r 51 <= 0000000020000f68000000001fffff44000000 + 31120 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000019000000001fffff44000000 + 31120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 31120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 31120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 31120 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } + 31120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003da8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +instret:688 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 3112 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h00000000800014f8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 31130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31130 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4b <= 0000000000000000400000001fffff44000000 + 31130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003da8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 31130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003da8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 31130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 31140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 31140 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } + 31140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:689 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 3114 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 74 <= 0000000000000000c00000001fffff44000000 + 31150 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 56 <= 0000000000000000400000001fffff44000000 + 31150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 31150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 45 <= 0000000000000000800000001fffff44000000 + 31160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 31160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 31170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 31170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h25e, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h4; InstTag { way: 'h0, ptr: 'h18, t: 'h30 } + 31180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h010 } + 31180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h011 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 31180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +calling cycle +[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h18, t: 'h30 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 31200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 31200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 31200 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } + 31200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 31210 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 31250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 31260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 31270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 31270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 69 <= 0000000020000484000000001fffff44000000 + 31280 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5f <= 0000000000000000800000001fffff44000000 + 31280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 43 <= 000000002000053d000000001fffff44000000 + 31290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 31300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 65 <= 0000000000000002000000001fffff44000000 + 31310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 31310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014fc +After delta: vaddr = 0x800014fc + 31310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 61 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 6d <= 000000002000053f000000001fffff44000000 + 31320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014fc, write: False, capStore: False, potentialCapLoad: False } + 31320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 31320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 31320 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 31320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 44 <= 0000000020000f20000000001fffff44000000 + 31330 : [doFinishMem] DTlbResp { resp: <'h00000000800014fc,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014fc, check_high: 'h00000000080001500, check_inclusive: True } }, specBits: 'h000 } + 31330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h00000000800014fc, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31330 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000000800000001fffff44000000 + 31330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 31330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4e <= 0000000000000010000000001fffff44000000 +[RFile] wr_ 2: r 08 <= 0000000000000000000000001fffff44000000 + 31340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 31340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 31340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 31340 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } + 31340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 31340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 31350 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 31350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31350 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000064000000001fffff44000000 + 31350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 31350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 31350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } +instret:690 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 3135 +instret:691 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 3135 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 64 <= 0000000000000040000000001fffff44000000 + 31360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 31360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 31360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 31360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 31360 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } + 31360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003da0 +After delta: vaddr = 0x80003da0 + 31360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } +instret:692 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 3136 +instret:693 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 3136 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5e <= 0000000020000f60000000001fffff44000000 + 31370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 31370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 31370 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 42 <= 0000000000000006000000001fffff44000000 + 31370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080003da0 o: 'h0000000080003da0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003da0 o: 'h0000000080003da0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003da0, write: True, capStore: False, potentialCapLoad: False } + 31370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 31370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 31370 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 31370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003dd0 +After delta: vaddr = 0x80003dd0 + 31370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:694 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 3137 +instret:695 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 3137 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 71 <= 0000000020000f70000000001fffff44000000 + 31380 : [doFinishMem] DTlbResp { resp: <'h0000000080003da0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003da0 o: 'h0000000080003da0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003da0, check_high: 'h00000000080003da8, check_inclusive: True } }, specBits: 'h000 } + 31380 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6e <= 0000000000000000800000001fffff44000000 + 31380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080003dc0 o: 'h0000000080003dc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000190 o: 'h0000000000000190 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003dd0 o: 'h0000000080003dd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003dd0, write: True, capStore: False, potentialCapLoad: False } + 31380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 31380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 31390 : [doFinishMem] DTlbResp { resp: <'h0000000080003dd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003dd0 o: 'h0000000080003dd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003dd0, check_high: 'h00000000080003dd4, check_inclusive: True } }, specBits: 'h000 } + 31390 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5a <= 0000000000000000800000001fffff44000000 + 31390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 31390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:696 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 3139 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31400 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003da0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 31400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 31400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 66 <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 31410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 31410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 31410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 31410 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 31410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 31410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003da0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +instret:697 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 3141 +instret:698 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 3141 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7c <= 0000000020000f60000000001fffff44000000 + 31420 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000000000005000000001fffff44000000 + 31420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 31420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003da0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 31420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003da0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 31420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:699 PC:0x1ffff0000000000000000000080000272 instr:0x02a0006f iType:J [doCommitNormalInst [0]] 3142 +instret:700 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [1]] 3142 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 0000000000000010000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 31430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 31430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31430 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 72 <= 0000000000000000800000001fffff44000000 + 31430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003dc8 +After delta: vaddr = 0x80003dc8 + 31430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:701 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [0]] 3143 +instret:702 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [1]] 3143 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'ha5e, localHist: 'h00f, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 59 <= 0000000020000f70000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080003dc0 o: 'h0000000080003dc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003dc8 o: 'h0000000080003dc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003dc8, write: True, capStore: False, potentialCapLoad: False } + 31440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 31440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 31440 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } + 31440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:703 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [0]] 3144 +instret:704 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [1]] 3144 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h00000000800014fc, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31450 : [doFinishMem] DTlbResp { resp: <'h0000000080003dc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003dc8 o: 'h0000000080003dc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003dc8, check_high: 'h00000000080003dd0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 31450 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0b <= 0000000000000000800000001fffff44000000 + 31450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 31450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 02 <= 0000000000000002000000001fffff44000000 +[RFile] wr_ 1: r 47 <= 0000000000000010000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 31460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 31460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 31460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014fc +After delta: vaddr = 0x800014fc + 31460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5b <= 000000002000053f000000001fffff44000000 + 31470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 31470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014fc, write: False, capStore: False, potentialCapLoad: False } + 31470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 31470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 62 <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31480 : [doFinishMem] DTlbResp { resp: <'h00000000800014fc,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014fc, check_high: 'h00000000080001500, check_inclusive: True } }, specBits: 'h000 } + 31480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h00000000800014fc, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 31480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 31480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 31480 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } + 31480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h52f, localHist: 'h3ff, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 40 <= 0000000020000f60000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 31490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31490 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 0000000000000000800000001fffff44000000 + 31490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 31490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 31490 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 31490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 31490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +calling cycle +calling cycle + 31510 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 31510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 31510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 31510 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } } + 31510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 31520 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h297, localHist: 'h3fd, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 31580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 74 <= 0000000000000000c00000001fffff44000000 + 31600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 31600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 31610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 31610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 31610 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } + 31610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31620 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 56 <= 0000000000000000800000001fffff44000000 + 31620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 31630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h14b, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 31640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 31640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 31640 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } + 31640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +instret:705 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 3164 +instret:706 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 3164 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000204; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } + 31650 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 65 <= 0000000000000000800000001fffff44000000 + 31650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:707 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 3167 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 31720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 31730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 31740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 31740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 69 <= 0000000020000484000000001fffff44000000 + 31750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 31750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 31750 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } + 31750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:708 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3175 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 43 <= 000000002000053d000000001fffff44000000 + 31760 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5f <= 0000000000000000800000001fffff44000000 + 31760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 31780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 31780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:709 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 3178 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 61 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 65 <= 0000000000000002000000001fffff44000000 + 31790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 31790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 31790 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 31790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014fc +After delta: vaddr = 0x800014fc + 31790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6d <= 000000002000053f000000001fffff44000000 + 31800 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000000800000001fffff44000000 + 31800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014fc, write: False, capStore: False, potentialCapLoad: False } + 31800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 31800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:710 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 3180 +instret:711 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 3180 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 44 <= 0000000020000f20000000001fffff44000000 + 31810 : [doFinishMem] DTlbResp { resp: <'h00000000800014fc,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014fc, check_high: 'h00000000080001500, check_inclusive: True } }, specBits: 'h000 } + 31810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h00000000800014fc, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 31810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 31810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:712 PC:0x1ffff0000000000000000000080000214 instr:0x2e458693 iType:Alu [doCommitNormalInst [0]] 3181 +instret:713 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 3181 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4e <= 0000000000000010000000001fffff44000000 + 31820 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 31820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 31820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 31820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 31820 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } + 31820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 31820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 64 <= 0000000000000040000000001fffff44000000 + 31830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 31830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31830 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000064000000001fffff44000000 + 31830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 31830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 31830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 31830 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } + 31830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5e <= 0000000020000f60000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h00000000800014fc, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 31840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31840 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 42 <= 0000000000000006000000001fffff44000000 + 31840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 31840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 31840 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 31840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003dd0 +After delta: vaddr = 0x80003dd0 + 31840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 71 <= 0000000020000f70000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31850 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6e <= 0000000000000000800000001fffff44000000 + 31850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080003dc0 o: 'h0000000080003dc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000190 o: 'h0000000000000190 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003dd0 o: 'h0000000080003dd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003dd0, write: True, capStore: False, potentialCapLoad: False } + 31850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 31850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 31850 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } + 31850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 31850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:714 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 3185 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 31860 : [doFinishMem] DTlbResp { resp: <'h0000000080003dd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003dd0 o: 'h0000000080003dd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003dd0, check_high: 'h00000000080003dd4, check_inclusive: True } }, specBits: 'h000 } + 31860 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5a <= 0000000000000000800000001fffff44000000 + 31860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 31860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:715 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 3186 +instret:716 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 3186 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31870 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 31870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 31870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:717 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 3187 +instret:718 PC:0x1ffff0000000000000000000080000228 instr:0xa5c58593 iType:Alu [doCommitNormalInst [1]] 3187 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 66 <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 31880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 31880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 31880 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 31880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 31880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:719 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 3188 +instret:720 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 3188 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7c <= 0000000020000f60000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31890 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000000000005000000001fffff44000000 + 31890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 31890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 31890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 31890 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } + 31890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:721 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 3189 +instret:722 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 3189 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 0000000000000010000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003dd0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 31900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31900 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 72 <= 0000000000000000800000001fffff44000000 + 31900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003dc8 +After delta: vaddr = 0x80003dc8 + 31900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:723 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3190 +instret:724 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 3190 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h94b, localHist: 'h00f, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 59 <= 0000000020000f70000000001fffff44000000 + 31910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080003dc0 o: 'h0000000080003dc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003dc8 o: 'h0000000080003dc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003dc8, write: True, capStore: False, potentialCapLoad: False } + 31910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 31910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 31910 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } + 31910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003dd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:725 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 3191 +instret:726 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 3191 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31920 : [doFinishMem] DTlbResp { resp: <'h0000000080003dc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003dc8 o: 'h0000000080003dc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003dc8, check_high: 'h00000000080003dd0, check_inclusive: True } }, specBits: 'h000 } + 31920 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0b <= 0000000000000000800000001fffff44000000 + 31920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003dd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 31920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003dd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 31920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 31920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:727 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 3192 +instret:728 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 3192 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 02 <= 0000000000000002000000001fffff44000000 +[RFile] wr_ 1: r 47 <= 0000000000000010000000001fffff44000000 + 31930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 31930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014fc +After delta: vaddr = 0x800014fc + 31930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:729 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 3193 +instret:730 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 3193 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5b <= 000000002000053f000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003dc8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 31940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014fc, write: False, capStore: False, potentialCapLoad: False } + 31940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 31940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 62 <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31950 : [doFinishMem] DTlbResp { resp: <'h00000000800014fc,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014fc, check_high: 'h00000000080001500, check_inclusive: True } }, specBits: 'h000 } + 31950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h00000000800014fc, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 31950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 31950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 31950 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } + 31950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:731 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 3195 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h4a5, localHist: 'h3ff, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 40 <= 0000000020000f60000000001fffff44000000 + 31960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 31960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31960 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 0000000000000000800000001fffff44000000 + 31960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 31960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 31960 : [Ld resp] 'h15; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 31960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 31960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:732 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 3196 +instret:733 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 3196 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0d <= 0000000020000f70000000001fffff44000000 + 31970 : [doRespLdMem] 'h15; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000000000064000000001fffff44000000 + 31970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 31970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 31970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 31970 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } } + 31970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003dc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +instret:734 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 3197 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h00000000800014fc, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 31980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31980 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0e <= 0000000000000000800000001fffff44000000 + 31980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003dc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 31980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003dc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 31980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 31980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h031 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 31990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 31990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 31990 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } + 31990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31990 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080003e50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:735 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 3199 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h031, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6a <= 0000000000000000c00000001fffff44000000 + 32000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h030 } + 32000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32000 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 0000000000000000800000001fffff44000000 + 32000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080003e50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 32000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 32000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 32000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 70 <= 0000000000000000c00000001fffff44000000 + 32010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 32010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 32010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 32010 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 32010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32010 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080003e48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32020 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080003e50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080003e50, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[RFile] wr_ 0: r 49 <= 0000000020000484000000001fffff44000000 + 32020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 32020 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000000800000001fffff44000000 + 32020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080003e48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 32020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 32020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7f <= 000000002000053d000000001fffff44000000 + 32030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 32040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 32040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 67 <= 0000000000000002000000001fffff44000000 + 32050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 32050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 32050 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } + 32050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800014fc +After delta: vaddr = 0x800014fc + 32050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 60 <= 000000002000053f000000001fffff44000000 +[RFile] wr_ 1: r 5d <= 0000000020001089000000001fffff44000000 + 32060 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 0000000000000000800000001fffff44000000 + 32060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014fc, write: False, capStore: False, potentialCapLoad: False } + 32060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 32060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4c <= 0000000020000f20000000001fffff44000000 +[RFile] wr_ 1: r 4b <= 0000000000000010000000001fffff44000000 + 32070 : [doFinishMem] DTlbResp { resp: <'h00000000800014fc,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014fc o: 'h00000000800014fc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800014fc, check_high: 'h00000000080001500, check_inclusive: True } }, specBits: 'h000 } + 32070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h00000000800014fc, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 32070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 32070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 32080 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 32080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 32080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 32080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h00000000800014fc, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 32080 : [Ld resp] 'h03; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } + 32080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 32080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6b <= 0000000000000040000000001fffff44000000 + 32090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 32090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32090 : [doRespLdMem] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 55 <= 0000000000000064000000001fffff44000000 + 32090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 32090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 32090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 32090 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 32090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 41 <= 0000000020000f60000000001fffff44000000 + 32100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 32100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 32100 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 0000000000000006000000001fffff44000000 + 32100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 32100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 32100 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } } + 32100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003dd0 +After delta: vaddr = 0x80003dd0 + 32100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5c <= 0000000020000f70000000001fffff44000000 + 32110 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 45 <= 0000000000000000800000001fffff44000000 + 32110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080003dc0 o: 'h0000000080003dc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000190 o: 'h0000000000000190 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003dd0 o: 'h0000000080003dd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003dd0, write: True, capStore: False, potentialCapLoad: False } + 32110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 32110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 32120 : [doFinishMem] DTlbResp { resp: <'h0000000080003dd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003dd0 o: 'h0000000080003dd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003dd0, check_high: 'h00000000080003dd4, check_inclusive: True } }, specBits: 'h000 } + 32120 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000000c00000001fffff44000000 + 32120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 32120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32130 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 32130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 32130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 52 <= 0000000000000040000000001fffff44000000 + 32140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 32140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 32140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 32140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 32140 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } + 32140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7b <= 0000000020000f60000000001fffff44000000 + 32150 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 65 <= 0000000000000005000000001fffff44000000 + 32150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 32150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 74 <= 0000000000000018000000001fffff44000000 + 32160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 32160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32160 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000000c00000001fffff44000000 + 32160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003de8 +After delta: vaddr = 0x80003de8 + 32160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'ha52, localHist: 'h007, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 56 <= 0000000020000f78000000001fffff44000000 + 32170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080003de0 o: 'h0000000080003de0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003de8 o: 'h0000000080003de8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003de8, write: True, capStore: False, potentialCapLoad: False } + 32170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 32170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 32170 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } + 32170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32180 : [doFinishMem] DTlbResp { resp: <'h0000000080003de8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003de8 o: 'h0000000080003de8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003de8, check_high: 'h00000000080003df0, check_inclusive: True } }, specBits: 'h000 } + 32180 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 0000000000000000800000001fffff44000000 + 32180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 32180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 69 <= 0000000000000003000000001fffff44000000 +[RFile] wr_ 1: r 73 <= 0000000000000018000000001fffff44000000 +[RFile] wr_ 2: r 05 <= 0000000000000000000000001fffff44000000 + 32190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 32190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001500 +After delta: vaddr = 0x80001500 + 32190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4a <= 0000000020000540000000001fffff44000000 + 32200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 32200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001500, write: False, capStore: False, potentialCapLoad: False } + 32200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 32200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } +instret:736 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 3220 +instret:737 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 3220 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5f <= 0000000000000040000000001fffff44000000 + 32210 : [doFinishMem] DTlbResp { resp: <'h0000000080001500,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001500, check_high: 'h00000000080001504, check_inclusive: True } }, specBits: 'h000 } + 32210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080001500, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 32210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 32210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 32210 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 32210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003dc0 +After delta: vaddr = 0x80003dc0 + 32210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:738 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 3221 +instret:739 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 3221 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h529, localHist: 'h3ff, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5e <= 0000000020000f60000000001fffff44000000 + 32220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 32220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 32220 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6e <= 0000000000000000800000001fffff44000000 + 32220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080003dc0 o: 'h0000000080003dc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003dc0 o: 'h0000000080003dc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003dc0, write: True, capStore: False, potentialCapLoad: False } + 32220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 32220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 32220 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 32220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:740 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 3222 +instret:741 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 3222 +calling cycle +[RFile] wr_ 0: r 75 <= 0000000020000f78000000001fffff44000000 + 32230 : [doFinishMem] DTlbResp { resp: <'h0000000080003dc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003dc0 o: 'h0000000080003dc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003dc0, check_high: 'h00000000080003dc8, check_inclusive: True } }, specBits: 'h000 } + 32230 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000190000000001fffff44000000 + 32230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 32240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 32240 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7c <= 0000000000000000c00000001fffff44000000 + 32240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32240 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:742 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 3224 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003dc0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 32250 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 79 <= 0000000000000000c00000001fffff44000000 + 32250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 32250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 32250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003dc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 43 <= 0000000000000000c00000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003dc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 32260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003dc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 32260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 32260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:743 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 3226 +instret:744 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 3226 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6f <= 0000000000000001000000001fffff44000000 + 32270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 32270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +instret:745 PC:0x1ffff0000000000000000000080000272 instr:0x02a0006f iType:J [doCommitNormalInst [0]] 3227 +instret:746 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [1]] 3227 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h4; InstTag { way: 'h0, ptr: 'h0f, t: 'h1e } + 32280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 32280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 32280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32280 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080003e40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:747 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [0]] 3228 +instret:748 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [1]] 3228 +calling cycle +[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h0f, t: 'h1e } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080003e40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 32300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +instret:749 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [0]] 3230 +instret:750 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [1]] 3230 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h00000000800014fc, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 32310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +calling cycle +calling cycle + 32330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 32330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 32330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'ha94, localHist: 'h3fe, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 32400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +calling cycle + 32410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[RFile] wr_ 1: r 6a <= 0000000000000000c00000001fffff44000000 + 32420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 32420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 32430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 32430 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } + 32430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32440 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 0000000000000000c00000001fffff44000000 + 32440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +instret:751 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 3246 +instret:752 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 3246 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000204; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } + 32470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 32470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 32490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 32490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 32490 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } + 32490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:753 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 3249 +calling cycle + 32500 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080003e50, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 32500 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle + 32510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32510 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 32510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080003e50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 32510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 32540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002e4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 32550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 32560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 32560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 49 <= 0000000020000484000000001fffff44000000 + 32570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 32570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 32570 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 32570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:754 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3257 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa5c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7f <= 000000002000053d000000001fffff44000000 + 32580 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000000c00000001fffff44000000 + 32580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 32600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 32600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:755 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 3260 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5d <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 67 <= 0000000000000003000000001fffff44000000 + 32610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 32610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 32610 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } + 32610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001500 +After delta: vaddr = 0x80001500 + 32610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 60 <= 0000000020000540000000001fffff44000000 + 32620 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 0000000000000000800000001fffff44000000 + 32620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001500, write: False, capStore: False, potentialCapLoad: False } + 32620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 32620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:756 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 3262 +instret:757 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 3262 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4c <= 0000000020000f20000000001fffff44000000 + 32630 : [doFinishMem] DTlbResp { resp: <'h0000000080001500,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001500, check_high: 'h00000000080001504, check_inclusive: True } }, specBits: 'h000 } + 32630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080001500, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 32630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 32630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:758 PC:0x1ffff0000000000000000000080000214 instr:0x2e458693 iType:Alu [doCommitNormalInst [0]] 3263 +instret:759 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 3263 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4b <= 0000000000000018000000001fffff44000000 + 32640 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 32640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 32640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 32640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 32640 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } + 32640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 32640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6b <= 0000000000000040000000001fffff44000000 + 32650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 32650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32650 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 55 <= 0000000000000190000000001fffff44000000 + 32650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 32650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 32650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 32650 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 32650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 41 <= 0000000020000f60000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080001500, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 32660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32660 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 0000000000000006000000001fffff44000000 + 32660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 32660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 32660 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } } + 32660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003df0 +After delta: vaddr = 0x80003df0 + 32660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5c <= 0000000020000f78000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32670 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 45 <= 0000000000000000800000001fffff44000000 + 32670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080003de0 o: 'h0000000080003de0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000640 o: 'h0000000000000640 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003df0 o: 'h0000000080003df0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003df0, write: True, capStore: False, potentialCapLoad: False } + 32670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 32670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 32670 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 32670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 32670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32670 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:760 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 3267 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 32680 : [doFinishMem] DTlbResp { resp: <'h0000000080003df0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003df0 o: 'h0000000080003df0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003df0, check_high: 'h00000000080003df4, check_inclusive: True } }, specBits: 'h000 } + 32680 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000000c00000001fffff44000000 + 32680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 32680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 32680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 32680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:761 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 3268 +instret:762 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 3268 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32690 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 32690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 32690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:763 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 3269 +instret:764 PC:0x1ffff0000000000000000000080000228 instr:0xa5c58593 iType:Alu [doCommitNormalInst [1]] 3269 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 52 <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 32700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 32700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 32700 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } + 32700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 32700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:765 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 3270 +instret:766 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 3270 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7b <= 0000000020000f60000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32710 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 65 <= 0000000000000005000000001fffff44000000 + 32710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 32710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 32710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 32710 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 32710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:767 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 3271 +instret:768 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 3271 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 74 <= 0000000000000018000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003df0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 32720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32720 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000000c00000001fffff44000000 + 32720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003de8 +After delta: vaddr = 0x80003de8 + 32720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:769 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3272 +instret:770 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 3272 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hd4a, localHist: 'h003, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 56 <= 0000000020000f78000000001fffff44000000 + 32730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080003de0 o: 'h0000000080003de0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003de8 o: 'h0000000080003de8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003de8, write: True, capStore: False, potentialCapLoad: False } + 32730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 32730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 32730 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } + 32730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003df0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:771 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 3273 +instret:772 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 3273 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32740 : [doFinishMem] DTlbResp { resp: <'h0000000080003de8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003de8 o: 'h0000000080003de8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003de8, check_high: 'h00000000080003df0, check_inclusive: True } }, specBits: 'h000 } + 32740 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 0000000000000000800000001fffff44000000 + 32740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003df0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 32740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003df0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 32740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 32740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:773 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 3274 +instret:774 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 3274 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 69 <= 0000000000000003000000001fffff44000000 +[RFile] wr_ 1: r 73 <= 0000000000000018000000001fffff44000000 + 32750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 32750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001500 +After delta: vaddr = 0x80001500 + 32750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:775 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 3275 +instret:776 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 3275 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4a <= 0000000020000540000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003de8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 32760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001500, write: False, capStore: False, potentialCapLoad: False } + 32760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 32760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5f <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32770 : [doFinishMem] DTlbResp { resp: <'h0000000080001500,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001500 o: 'h0000000080001500 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001500, check_high: 'h00000000080001504, check_inclusive: True } }, specBits: 'h000 } + 32770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080001500, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 32770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 32770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 32770 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 32770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:777 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 3277 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h6a5, localHist: 'h3ff, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5e <= 0000000020000f60000000001fffff44000000 + 32780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 32780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32780 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6e <= 0000000000000000800000001fffff44000000 + 32780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 32780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080001500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 32780 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 32780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 32780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:778 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 3278 +instret:779 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 3278 +calling cycle +[RFile] wr_ 0: r 75 <= 0000000020000f78000000001fffff44000000 + 32790 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000190000000001fffff44000000 + 32790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 32790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 32790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 32790 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } + 32790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003de8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +instret:780 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 3279 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080001500, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 32800 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7c <= 0000000000000000c00000001fffff44000000 + 32800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003de8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 32800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003de8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 32800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:781 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 3281 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 43 <= 0000000000000000c00000001fffff44000000 + 32820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 32820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6f <= 0000000000000001000000001fffff44000000 + 32830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 32830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 32840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 32840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h352, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 32850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h010 } + 32850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h011 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 32850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h013, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h011 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 32860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 32860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 32860 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } + 32860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 05 <= 0000000000000000800000001fffff44000000 + 32870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h010 } + 32870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32870 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0b <= 0000000000000000800000001fffff44000000 + 32870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 32880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 32880 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 32880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 32880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h1a9, localHist: 'h2aa, globalTaken: True, localTaken: True, pcIndex: 'h169 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6c <= 0000000000000000000000001fffff44000000 + 32890 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000000800000001fffff44000000 + 32890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: True, capStore: False, potentialCapLoad: False } + 32890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 32890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 44 <= 0000000000000000c00000001fffff44000000 + 32900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h012 } + 32900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: True, capStore: False, potentialCapLoad: False } + 32900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01a } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 32900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 32910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h010 } + 32910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01a } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 32910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03b } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff99c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 01 <= 0000000000000000c00000001fffff44000000 +[ALU redirect - 0] 'h1ffff00000000000000000000800001e8; 'h1; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } + 32920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h012 } + 32920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 32920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h033 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[ROB incorrectSpec] 'h1 ; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 32940 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +[RFile] wr_ 2: r 61 <= 0000000000000000000000001fffff44000000 +calling cycle + 33020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:782 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 3302 +instret:783 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 3302 +calling cycle + 33030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003de0 +After delta: vaddr = 0x80003de0 +instret:784 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 3303 +instret:785 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 3303 +calling cycle + 33040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080003de0 o: 'h0000000080003de0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003de0 o: 'h0000000080003de0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003de0, write: True, capStore: False, potentialCapLoad: False } +instret:786 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 3304 +instret:787 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 3304 +calling cycle + 33050 : [doFinishMem] DTlbResp { resp: <'h0000000080003de0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003de0 o: 'h0000000080003de0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003de0, check_high: 'h00000000080003de8, check_inclusive: True } }, specBits: 'h000 } +calling cycle +instret:788 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 3306 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003de0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 33070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080003de0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080003de0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 33080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080003de0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:789 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 3308 +instret:790 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 3308 +calling cycle +instret:791 PC:0x1ffff0000000000000000000080000272 instr:0x02a0006f iType:J [doCommitNormalInst [0]] 3309 +instret:792 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [1]] 3309 +calling cycle +instret:793 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [0]] 3310 +instret:794 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [1]] 3310 +calling cycle +instret:795 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [0]] 3311 +instret:796 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [1]] 3311 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 33120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +calling cycle + 33130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 33130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 33140 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } +calling cycle + 33150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 33150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 33150 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } + 33150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 33160 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 79 <= 0000000000000001000000001fffff44000000 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:797 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 3318 +instret:798 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 3318 +calling cycle +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } +instret:799 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 3320 +instret:800 PC:0x1ffff0000000000000000000080000200 instr:0x0ae0006f iType:J [doCommitNormalInst [1]] 3320 +calling cycle +instret:801 PC:0x1ffff00000000000000000000800002ae instr:0x0040006f iType:J [doCommitNormalInst [0]] 3321 +instret:802 PC:0x1ffff00000000000000000000800002b2 instr:0xfcc42503 iType:Ld [doCommitNormalInst [1]] 3321 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +instret:803 PC:0x1ffff00000000000000000000800002b6 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 3322 +instret:804 PC:0x1ffff00000000000000000000800002b8 instr:0xfca42623 iType:St [doCommitNormalInst [1]] 3322 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82b8 } + 33230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } +instret:805 PC:0x1ffff00000000000000000000800002bc instr:0xf1fff06f iType:J [doCommitNormalInst [0]] 3323 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } + 33240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 33240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h9a9, localHist: 'h3ff, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6c <= 0000000000000000000000001fffff44000000 + 33250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 33250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 33260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 01 <= 0000000000000000c00000001fffff44000000 + 33270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 33270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 33280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 33290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h4d4, localHist: 'h3fa, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 33300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 33300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +calling cycle +calling cycle + 33320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 33320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 33320 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 33320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 33330 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h26a, localHist: 'h3fa, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 33390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 05 <= 0000000000000000800000001fffff44000000 + 33410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 33410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 33420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 33420 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 33420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 33420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h135, localHist: 'h2aa, globalTaken: True, localTaken: True, pcIndex: 'h169 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6c <= 0000000000000000000000001fffff44000000 + 33430 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000000c00000001fffff44000000 + 33430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: True, capStore: False, potentialCapLoad: False } + 33430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h001 } + 33440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 33440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 01 <= 0000000000000000c00000001fffff44000000 + 33450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h001 } + 33450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 33450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 +instret:806 PC:0x1ffff00000000000000000000800001da instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 3345 +instret:807 PC:0x1ffff00000000000000000000800001de instr:0x00004509 iType:Alu [doCommitNormalInst [1]] 3345 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff99c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 33460 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000000000000000000001fffff44000000 + 33460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h018 } + 33470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 33470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:808 PC:0x1ffff00000000000000000000800001e0 instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 3347 +instret:809 PC:0x1ffff00000000000000000000800001e4 instr:0x0dc0006f iType:J [doCommitNormalInst [1]] 3347 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h018, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 02 <= 00000000200010b9000000001fffff44000000 + 33480 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 68 <= 0000000000000000000000001fffff44000000 + 33480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 +instret:810 PC:0x1ffff00000000000000000000800002c0 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 3348 +instret:811 PC:0x1ffff00000000000000000000800002c2 instr:0xfca42223 iType:St [doCommitNormalInst [1]] 3348 +calling cycle +[RFile] wr_ 0: r 6a <= 0000000020000f20000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82c2 } + 33490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } + 33490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82c2 } +instret:812 PC:0x1ffff00000000000000000000800002c6 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3349 +instret:813 PC:0x1ffff00000000000000000000800002ca instr:0xfc442583 iType:Ld [doCommitNormalInst [1]] 3349 +calling cycle +[RFile] wr_ 0: r 67 <= 00000000200000bc800000001fffff44000000 + 33500 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 33500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h82ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82c2 } + 33500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82c2 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } +instret:814 PC:0x1ffff00000000000000000000800002ce instr:0x0000450d iType:Alu [doCommitNormalInst [0]] 3350 +instret:815 PC:0x1ffff00000000000000000000800002d0 instr:0x00b55463 iType:Br [doCommitNormalInst [1]] 3350 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4d <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 60 <= 00000000200000be800000001fffff44000000 +[ALU redirect - 1] 'h1ffff000000000000000000008000031c; 'h0; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } + 33510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 33510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 33510 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 33510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:816 PC:0x1ffff00000000000000000000800002d8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3351 +instret:817 PC:0x1ffff00000000000000000000800002dc instr:0xfc442503 iType:Ld [doCommitNormalInst [1]] 3351 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +[RFile] wr_ 1: r 58 <= 0000000020000f20000000001fffff44000000 + 33530 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000000000000001fffff44000000 +instret:818 PC:0x1ffff00000000000000000000800002e0 instr:0x00551593 iType:Alu [doCommitNormalInst [0]] 3353 +instret:819 PC:0x1ffff00000000000000000000800002e4 instr:0x00004517 iType:Auipc [doCommitNormalInst [1]] 3353 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } +instret:820 PC:0x1ffff00000000000000000000800002e8 instr:0x99c50513 iType:Alu [doCommitNormalInst [0]] 3354 +instret:821 PC:0x1ffff00000000000000000000800002ec instr:0x0000952e iType:Alu [doCommitNormalInst [1]] 3354 +calling cycle +instret:822 PC:0x1ffff00000000000000000000800002ee instr:0xfd04258f iType:Ld [doCommitNormalInst [0]] 3355 +instret:823 PC:0x1ffff00000000000000000000800002f2 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 3355 +calling cycle +instret:824 PC:0x1ffff00000000000000000000800002f6 instr:0x02a080e7 iType:Jr [doCommitNormalInst [0]] 3356 +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 33600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 49 <= 00000000200003cc000000001fffff44000000 + 33610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800002fa o: 'h00000000800002fa b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 33610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 33610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5d <= 00000000200003e4000000001fffff44000000 + 33620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 33620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 33620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 33620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:825 PC:0x1ffff000000000000000000008000031c instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 3362 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 33630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 33630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 33630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 33630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:826 PC:0x1ffff000000000000000000008000031e instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 3363 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 33640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h831e } + 33640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 33640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 33640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } +instret:827 PC:0x1ffff0000000000000000000080000320 instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 3364 +instret:828 PC:0x1ffff0000000000000000000080000322 instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 3364 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 33650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 33650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } + 33650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:829 PC:0x1ffff0000000000000000000080000324 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 3365 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 33660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8320 } + 33660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h832c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 33660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 33660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } +instret:830 PC:0x1ffff0000000000000000000080000328 instr:0xfcb44823 iType:St [doCommitNormalInst [0]] 3366 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 33670 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 41 <= 0000000020000f20000000001fffff44000000 + 33670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 33670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } + 33670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8324 } + 33680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8336 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 33680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003c80 +After delta: vaddr = 0x80003c80 + 33680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 33690 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5c <= 0000000020000f20000000001fffff44000000 + 33690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003c80, write: False, capStore: False, potentialCapLoad: False } + 33690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } + 33690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 33690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:831 PC:0x1ffff000000000000000000008000032c instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3369 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 33700 : [doFinishMem] DTlbResp { resp: <'h0000000080003c80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003c80, check_high: 'h00000000080003c88, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8328 } + 33700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080003c80, shiftedBE: tagged DataMemAccess , pcHash: 'h8330 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 33700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003c88 +After delta: vaddr = 0x80003c88 + 33700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080003c80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 33710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8340 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003c88 o: 'h0000000080003c88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003c88, write: False, capStore: False, potentialCapLoad: False } + 33710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080003c80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 33710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080003c80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 33710 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } + 33710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8340 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33720 : [doFinishMem] DTlbResp { resp: <'h0000000080003c88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003c88 o: 'h0000000080003c88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003c88, check_high: 'h00000000080003c90, check_inclusive: True } }, specBits: 'h000 } + 33720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080003c88, shiftedBE: tagged DataMemAccess , pcHash: 'h833a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33720 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 54 <= 0000000000000000000000001fffff44000000 + 33720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8340 } + 33720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8340 } + 33720 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } + 33720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 33720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080003c88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h89a, localHist: 'h02a, globalTaken: True, localTaken: False, pcIndex: 'h1ae }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 57 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080003c80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33730 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4b <= 0000000020000f20000000001fffff44000000 + 33730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } + 33730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080003c88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + 33730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080003c88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + 33730 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } } + 33730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 33730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000015a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 33740 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 45 <= 0000000000000006000000001fffff44000000 + 33740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 33740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } + 33740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003c90 +After delta: vaddr = 0x80003c90 + 33740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:832 PC:0x1ffff0000000000000000000080000330 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 3374 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 33750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003c90 o: 'h0000000080003c90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003c90, write: False, capStore: False, potentialCapLoad: False } + 33750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 33750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 33760 : [doFinishMem] DTlbResp { resp: <'h0000000080003c90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003c90 o: 'h0000000080003c90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003c90, check_high: 'h00000000080003c94, check_inclusive: True } }, specBits: 'h000 } + 33760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080003c90, shiftedBE: tagged DataMemAccess , pcHash: 'h8344 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } + 33760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 33760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080003c90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } +instret:833 PC:0x1ffff0000000000000000000080000332 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3376 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8332 } + 33770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 33770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080003c90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + 33770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080003c90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + 33770 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 33770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 33770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } +calling cycle +[RFile] wr_ 1: r 4c <= 00000000200003e4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080003c88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 33780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8354 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 33780 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000006400000001fffff44000000 + 33780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 33780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } + 33780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 33780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:834 PC:0x1ffff0000000000000000000080000336 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3378 +calling cycle + 33790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 33790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8358 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33790 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000000000000000000001fffff44000000 + 33790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 33790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffbc, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f4c +After delta: vaddr = 0x80000f4c + 33790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } +instret:835 PC:0x1ffff000000000000000000008000033a instr:0x00006508 iType:Ld [doCommitNormalInst [0]] 3379 +instret:836 PC:0x1ffff000000000000000000008000033c instr:0xfca43023 iType:St [doCommitNormalInst [1]] 3379 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h833c } + 33800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h84ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffbc, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000019 o: 'h0000000000000019 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } + 33800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } + 33800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } + 33800 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } + 33800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 33800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ba } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080003c90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 33810 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000000000000000000001fffff44000000 + 33810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + 33810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ba } + 33810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ba } + 33810 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 33810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +instret:837 PC:0x1ffff0000000000000000000080000340 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3381 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h03, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h002 } + 33820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h84bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33820 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 00000000200000be800000001fffff44000000 + 33820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 33820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84bc } +instret:838 PC:0x1ffff0000000000000000000080000344 instr:0x00004908 iType:Ld [doCommitNormalInst [0]] 3382 +instret:839 PC:0x1ffff0000000000000000000080000346 instr:0xfaa42e23 iType:St [doCommitNormalInst [1]] 3382 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8346 } + 33830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84bc } + 33830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84bc } + 33830 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } + 33830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } +instret:840 PC:0x1ffff000000000000000000008000034a instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 3383 +instret:841 PC:0x1ffff000000000000000000008000034c instr:0xfaa42c23 iType:St [doCommitNormalInst [1]] 3383 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33840 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 00000000200003f4000000001fffff44000000 + 33840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 33840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:842 PC:0x1ffff0000000000000000000080000350 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3384 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h834c } + 33850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 33850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } +instret:843 PC:0x1ffff0000000000000000000080000354 instr:0xfb842503 iType:Ld [doCommitNormalInst [0]] 3385 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 33860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } + 33860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:844 PC:0x1ffff0000000000000000000080000358 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 3386 +instret:845 PC:0x1ffff000000000000000000008000035c instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 3386 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h44d, localHist: 'h2aa, globalTaken: True, localTaken: True, pcIndex: 'h168 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 33870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82fe } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 33870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } +instret:846 PC:0x1ffff0000000000000000000080000360 instr:0x15a0006f iType:J [doCommitNormalInst [0]] 3387 +instret:847 PC:0x1ffff00000000000000000000800004ba instr:0x000060e6 iType:Ld [doCommitNormalInst [1]] 3387 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 33880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 33880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 33880 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } + 33880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:848 PC:0x1ffff00000000000000000000800004bc instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 3388 +instret:849 PC:0x1ffff00000000000000000000800004be instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 3388 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6e <= 0000000000000000c00000001fffff44000000 + 33890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 33890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33890 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000000000000000000001fffff44000000 + 33890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 33890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } +instret:850 PC:0x1ffff00000000000000000000800004c0 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 3389 +instret:851 PC:0x1ffff00000000000000000000800002fa instr:0x0040006f iType:J [doCommitNormalInst [1]] 3389 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff99c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 33900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 33900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 33900 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } + 33900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } + 33910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33910 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5a <= 0000000000000000000000001fffff44000000 + 33910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 33910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } +instret:852 PC:0x1ffff00000000000000000000800002fe instr:0xfc442503 iType:Ld [doCommitNormalInst [0]] 3391 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6f <= 00000000200010b9000000001fffff44000000 +[RFile] wr_ 1: r 61 <= 0000000000000000400000001fffff44000000 + 33920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: True, capStore: False, potentialCapLoad: False } + 33920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 33920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 33920 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 33920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5b <= 0000000020000f20000000001fffff44000000 + 33930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 33930 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000000000000001fffff44000000 + 33930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } + 33930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:853 PC:0x1ffff0000000000000000000080000302 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 3393 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 43 <= 00000000200000bc800000001fffff44000000 + 33940 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h001 } + 33940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h82ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 33940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } +instret:854 PC:0x1ffff0000000000000000000080000304 instr:0xfca42223 iType:St [doCommitNormalInst [0]] 3394 +instret:855 PC:0x1ffff0000000000000000000080000308 instr:0xfc3ff06f iType:J [doCommitNormalInst [1]] 3394 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 72 <= 00000000200003cc000000001fffff44000000 +[RFile] wr_ 1: r 0b <= 00000000200000be800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8304 } + 33950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800002fa o: 'h00000000800002fa b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 33950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 33950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 33950 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 33950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 33950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 75 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 33960 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000000000000000000001fffff44000000 + 33960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 33960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } + 33960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 33960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 44 <= 00000000200003e4000000001fffff44000000 +[RFile] wr_ 1: r 77 <= 0000000020000f20000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 33970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 33970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 33970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 33970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 33980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 33980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 33980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 33990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 33990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 34000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h832c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 34010 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 05 <= 0000000020000f20000000001fffff44000000 + 34010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 34010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 34020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003c80 +After delta: vaddr = 0x80003c80 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 34030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8336 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003c80, write: False, capStore: False, potentialCapLoad: False } + 34030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 34040 : [doFinishMem] DTlbResp { resp: <'h0000000080003c80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003c80, check_high: 'h00000000080003c88, check_inclusive: True } }, specBits: 'h000 } + 34040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080003c80, shiftedBE: tagged DataMemAccess , pcHash: 'h8330 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34040 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000020000f20000000001fffff44000000 + 34040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 34040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080003c80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 34050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 34050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080003c80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 34050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080003c80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 34050 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } + 34050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003c88 +After delta: vaddr = 0x80003c88 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 34060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8340 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34060 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 0000000000000000000000001fffff44000000 + 34060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003c88 o: 'h0000000080003c88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003c88, write: False, capStore: False, potentialCapLoad: False } + 34060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080003c80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34070 : [doFinishMem] DTlbResp { resp: <'h0000000080003c88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003c88 o: 'h0000000080003c88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003c88, check_high: 'h00000000080003c90, check_inclusive: True } }, specBits: 'h000 } + 34070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080003c88, shiftedBE: tagged DataMemAccess , pcHash: 'h833a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34070 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000020000f20000000001fffff44000000 + 34070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 34070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080003c88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'ha26, localHist: 'h015, globalTaken: True, localTaken: False, pcIndex: 'h1ae }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 68 <= 0000000000000000000000001fffff44000000 + 34080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 34080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080003c88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + 34080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080003c88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + 34080 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } + 34080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003c90 +After delta: vaddr = 0x80003c90 + 34080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000015a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 34090 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6c <= 0000000000000006000000001fffff44000000 + 34090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080003c80 o: 'h0000000080003c80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003c90 o: 'h0000000080003c90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003c90, write: False, capStore: False, potentialCapLoad: False } + 34090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 34090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34100 : [doFinishMem] DTlbResp { resp: <'h0000000080003c90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003c90 o: 'h0000000080003c90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003c90, check_high: 'h00000000080003c94, check_inclusive: True } }, specBits: 'h000 } + 34100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080003c90, shiftedBE: tagged DataMemAccess , pcHash: 'h8344 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } + 34100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 34100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080003c90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 34110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } + 34110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080003c90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + 34110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080003c90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + 34110 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 34110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 34110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080003c88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } + 34120 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000000000006400000001fffff44000000 + 34120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 34120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 34120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7a <= 00000000200003e4000000001fffff44000000 + 34130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 34130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8354 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 34130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffbc, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f4c +After delta: vaddr = 0x80000f4c + 34130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h03, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 34140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8358 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34140 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 0000000000000000000000001fffff44000000 + 34140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffbc, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000019 o: 'h0000000000000019 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } + 34140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 34140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h513, localHist: 'h355, globalTaken: True, localTaken: True, pcIndex: 'h169 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080003c90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 34150 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 0000000000000000000000001fffff44000000 + 34150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 34150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 34160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } + 34160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h84ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h002 } + 34170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h84bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34170 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 00000000200000be800000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff99c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34180 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 00000000200003f4000000001fffff44000000 + 34180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h033, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h033, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 52 <= 0000000000000000c00000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h031, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h033, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h011, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 51 <= 00000000200010b9000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 34210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82fe } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 56 <= 0000000020000f20000000001fffff44000000 + 34220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 34220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 34220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 34220 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } + 34220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 34220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4a <= 00000000200000bc800000001fffff44000000 +[RFile] wr_ 1: r 60 <= 00000000200003cc000000001fffff44000000 + 34230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h010 } + 34230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34230 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 0000000000000000400000001fffff44000000 + 34230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } + 34230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 34230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 34230 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } + 34230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h012 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 34230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 65 <= 00000000200000be800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34240 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h010 } + 34240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h82ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34240 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5c <= 0000000000000000400000001fffff44000000 + 34240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800002fa o: 'h00000000800002fa b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 34240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 34240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 34240 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } + 34240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h012 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 34240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6d <= 00000000200003e4000000001fffff44000000 + 34250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h010 } + 34250 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7b <= 0000000000000000400000001fffff44000000 + 34250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 34250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 34250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 34250 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 34250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 41 <= 0000000000000000800000001fffff44000000 + 34260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h010 } + 34260 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000000000000001fffff44000000 + 34260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: True, capStore: False, potentialCapLoad: False } + 34260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 34260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 34270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 34270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 34270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 34270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'ha89, localHist: 'h355, globalTaken: True, localTaken: True, pcIndex: 'h168 }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 34360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6e <= 0000000000000000c00000001fffff44000000 + 34380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 34380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff99c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 34390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 34390 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } + 34390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } + 34400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34400 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5a <= 0000000000000000400000001fffff44000000 + 34400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6f <= 00000000200010b9000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 34410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 34410 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 34410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5b <= 0000000020000f20000000001fffff44000000 + 34420 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000000400000001fffff44000000 + 34420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } +instret:856 PC:0x1ffff00000000000000000000800002ca instr:0xfc442583 iType:Ld [doCommitNormalInst [0]] 3442 +instret:857 PC:0x1ffff00000000000000000000800002ce instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 3442 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 43 <= 00000000200000bc800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34430 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h001 } + 34430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h82ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0b <= 00000000200000be800000001fffff44000000 + 34440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 34440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 34440 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 34440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 34440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:858 PC:0x1ffff00000000000000000000800002d0 instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 3444 +instret:859 PC:0x1ffff00000000000000000000800002d8 instr:0x0040006f iType:J [doCommitNormalInst [1]] 3444 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 75 <= 0000000000000008000000001fffff44000000 +[RFile] wr_ 1: r 72 <= 00000000200003cc000000001fffff44000000 + 34450 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000000000000000000001fffff44000000 + 34450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800002fa o: 'h00000000800002fa b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 34450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 34450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:860 PC:0x1ffff00000000000000000000800002dc instr:0xfc442503 iType:Ld [doCommitNormalInst [0]] 3445 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 77 <= 0000000020000f28000000001fffff44000000 +[RFile] wr_ 1: r 44 <= 00000000200003e4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 34460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 34460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 34460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 34460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:861 PC:0x1ffff00000000000000000000800002e0 instr:0x00551593 iType:Alu [doCommitNormalInst [0]] 3446 +instret:862 PC:0x1ffff00000000000000000000800002e4 instr:0x00004517 iType:Auipc [doCommitNormalInst [1]] 3446 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 34470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 34470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 34470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 34470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:863 PC:0x1ffff00000000000000000000800002e8 instr:0x99c50513 iType:Alu [doCommitNormalInst [0]] 3447 +instret:864 PC:0x1ffff00000000000000000000800002ec instr:0x0000952e iType:Alu [doCommitNormalInst [1]] 3447 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 34480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 34480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 34480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +instret:865 PC:0x1ffff00000000000000000000800002ee instr:0xfd04258f iType:Ld [doCommitNormalInst [0]] 3448 +instret:866 PC:0x1ffff00000000000000000000800002f2 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 3448 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 34490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 34490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:867 PC:0x1ffff00000000000000000000800002f6 instr:0x02a080e7 iType:Jr [doCommitNormalInst [0]] 3449 +instret:868 PC:0x1ffff000000000000000000008000031c instr:0x0000711d iType:Alu [doCommitNormalInst [1]] 3449 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 34500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 34500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h832c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +instret:869 PC:0x1ffff000000000000000000008000031e instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 3450 +instret:870 PC:0x1ffff0000000000000000000080000320 instr:0x0000e8a2 iType:St [doCommitNormalInst [1]] 3450 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h831e } + 34510 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 05 <= 0000000020000f28000000001fffff44000000 + 34510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 34510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } +instret:871 PC:0x1ffff0000000000000000000080000322 instr:0x00001080 iType:Alu [doCommitNormalInst [0]] 3451 +instret:872 PC:0x1ffff0000000000000000000080000324 instr:0xfea43423 iType:St [doCommitNormalInst [1]] 3451 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 34520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8336 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } + 34520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 34520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ca0 +After delta: vaddr = 0x80003ca0 + 34520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:873 PC:0x1ffff0000000000000000000080000328 instr:0xfcb44823 iType:St [doCommitNormalInst [0]] 3452 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8320 } + 34530 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000020000f28000000001fffff44000000 + 34530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ca0, write: False, capStore: False, potentialCapLoad: False } + 34530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 34530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } +instret:874 PC:0x1ffff000000000000000000008000032c instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3453 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 34540 : [doFinishMem] DTlbResp { resp: <'h0000000080003ca0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ca0, check_high: 'h00000000080003ca8, check_inclusive: True } }, specBits: 'h000 } + 34540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080003ca0, shiftedBE: tagged DataMemAccess , pcHash: 'h8330 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 34540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } + 34540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 34540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ca8 +After delta: vaddr = 0x80003ca8 + 34540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080003ca0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8324 } + 34550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8340 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ca8 o: 'h0000000080003ca8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ca8, write: False, capStore: False, potentialCapLoad: False } + 34550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080003ca0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 34550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080003ca0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 34550 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } + 34550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34560 : [doFinishMem] DTlbResp { resp: <'h0000000080003ca8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ca8 o: 'h0000000080003ca8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ca8, check_high: 'h00000000080003cb0, check_inclusive: True } }, specBits: 'h000 } + 34560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080003ca8, shiftedBE: tagged DataMemAccess , pcHash: 'h833a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34560 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 0000000000000000000000001fffff44000000 + 34560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } + 34560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 34560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 34560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080003ca8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hd44, localHist: 'h00a, globalTaken: True, localTaken: False, pcIndex: 'h1ae }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 68 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080003ca0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8328 } + 34570 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000020000f28000000001fffff44000000 + 34570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } + 34570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080003ca8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + 34570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080003ca8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + 34570 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } + 34570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 34570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000015a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 34580 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6c <= 0000000000000006000000001fffff44000000 + 34580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 34580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } + 34580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 34580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cb0 +After delta: vaddr = 0x80003cb0 + 34580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:875 PC:0x1ffff0000000000000000000080000330 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 3458 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 34590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cb0 o: 'h0000000080003cb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cb0, write: False, capStore: False, potentialCapLoad: False } + 34590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 34590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 34600 : [doFinishMem] DTlbResp { resp: <'h0000000080003cb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cb0 o: 'h0000000080003cb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cb0, check_high: 'h00000000080003cb4, check_inclusive: True } }, specBits: 'h000 } + 34600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080003cb0, shiftedBE: tagged DataMemAccess , pcHash: 'h8344 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } + 34600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 34600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080003cb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } +instret:876 PC:0x1ffff0000000000000000000080000332 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3460 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8332 } + 34610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 34610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080003cb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + 34610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080003cb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + 34610 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 34610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 34610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7a <= 00000000200003e4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080003ca8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 34620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8354 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34620 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000000000019000000001fffff44000000 + 34620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 34620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } + 34620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 34620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 34620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:877 PC:0x1ffff0000000000000000000080000336 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3462 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h03, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 34630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 34630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8358 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34630 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 0000000000000000000000001fffff44000000 + 34630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 34630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffbc, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f4c +After delta: vaddr = 0x80000f4c + 34630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } +instret:878 PC:0x1ffff000000000000000000008000033a instr:0x00006508 iType:Ld [doCommitNormalInst [0]] 3463 +instret:879 PC:0x1ffff000000000000000000008000033c instr:0xfca43023 iType:St [doCommitNormalInst [1]] 3463 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h6a2, localHist: 'h3aa, globalTaken: True, localTaken: True, pcIndex: 'h169 }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h833c } + 34640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h84ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffbc, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000064 o: 'h0000000000000064 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } + 34640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } + 34640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } + 34640 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 34640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 34640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ba } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080003cb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 34650 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 0000000000000000000000001fffff44000000 + 34650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + 34650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ba } + 34650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ba } + 34650 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 34650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +instret:880 PC:0x1ffff0000000000000000000080000340 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3465 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h002 } + 34660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h84bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34660 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 00000000200000be800000001fffff44000000 + 34660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 34660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 34660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84bc } +instret:881 PC:0x1ffff0000000000000000000080000344 instr:0x00004908 iType:Ld [doCommitNormalInst [0]] 3466 +instret:882 PC:0x1ffff0000000000000000000080000346 instr:0xfaa42e23 iType:St [doCommitNormalInst [1]] 3466 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff99c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 52 <= 0000000000000000c00000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8346 } + 34670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84bc } + 34670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84bc } + 34670 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } + 34670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } +instret:883 PC:0x1ffff000000000000000000008000034a instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 3467 +instret:884 PC:0x1ffff000000000000000000008000034c instr:0xfaa42c23 iType:St [doCommitNormalInst [1]] 3467 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h033, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h033, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34680 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 00000000200003f4000000001fffff44000000 + 34680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 34680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 34680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:885 PC:0x1ffff0000000000000000000080000350 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3468 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h033, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h834c } + 34690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } +instret:886 PC:0x1ffff0000000000000000000080000354 instr:0xfb842503 iType:Ld [doCommitNormalInst [0]] 3469 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 51 <= 00000000200010b9000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } + 34700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 34700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:887 PC:0x1ffff0000000000000000000080000358 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 3470 +instret:888 PC:0x1ffff000000000000000000008000035c instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 3470 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 56 <= 0000000020000f20000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 34710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82fe } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } +instret:889 PC:0x1ffff0000000000000000000080000360 instr:0x15a0006f iType:J [doCommitNormalInst [0]] 3471 +instret:890 PC:0x1ffff00000000000000000000800004ba instr:0x000060e6 iType:Ld [doCommitNormalInst [1]] 3471 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4a <= 00000000200000bc800000001fffff44000000 +[RFile] wr_ 1: r 60 <= 00000000200003cc000000001fffff44000000 + 34720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 34720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 34720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 34720 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } + 34720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 34720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } +instret:891 PC:0x1ffff00000000000000000000800004bc instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 3472 +instret:892 PC:0x1ffff00000000000000000000800004be instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 3472 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 65 <= 00000000200000be800000001fffff44000000 + 34730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h010 } + 34730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34730 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 0000000000000000400000001fffff44000000 + 34730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } + 34730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 34730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 34730 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } + 34730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 34730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } +instret:893 PC:0x1ffff00000000000000000000800004c0 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 3473 +instret:894 PC:0x1ffff00000000000000000000800002fa instr:0x0040006f iType:J [doCommitNormalInst [1]] 3473 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6d <= 00000000200003e4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34740 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h010 } + 34740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h82ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34740 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5c <= 0000000000000000400000001fffff44000000 + 34740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800002fa o: 'h00000000800002fa b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 34740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 34740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 34740 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } + 34740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 34740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 34750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h010 } + 34750 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7b <= 0000000000000000400000001fffff44000000 + 34750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 34750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 34750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 34750 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 34750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:895 PC:0x1ffff00000000000000000000800002fe instr:0xfc442503 iType:Ld [doCommitNormalInst [0]] 3475 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 41 <= 0000000000000000800000001fffff44000000 + 34760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h010 } + 34760 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000000000000001fffff44000000 + 34760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: True, capStore: False, potentialCapLoad: False } + 34760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 34760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 34770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 34770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 34770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:896 PC:0x1ffff0000000000000000000080000302 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 3477 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 76 <= 0000000000000008000000001fffff44000000 + 34780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 34780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h832c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 34780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 34780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } +instret:897 PC:0x1ffff0000000000000000000080000304 instr:0xfca42223 iType:St [doCommitNormalInst [0]] 3478 +instret:898 PC:0x1ffff0000000000000000000080000308 instr:0xfc3ff06f iType:J [doCommitNormalInst [1]] 3478 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 57 <= 0000000020000f28000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 34790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8304 } + 34790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 34790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } + 34790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } + 34790 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } + 34790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 34790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 34800 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000020000f28000000001fffff44000000 + 34800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 34800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } + 34800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 34800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 34810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 34810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8336 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ca0 +After delta: vaddr = 0x80003ca0 + 34810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 34820 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000020000f28000000001fffff44000000 + 34820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ca0, write: False, capStore: False, potentialCapLoad: False } + 34820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 34820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34830 : [doFinishMem] DTlbResp { resp: <'h0000000080003ca0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ca0, check_high: 'h00000000080003ca8, check_inclusive: True } }, specBits: 'h000 } + 34830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080003ca0, shiftedBE: tagged DataMemAccess , pcHash: 'h8330 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 34830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ca8 +After delta: vaddr = 0x80003ca8 + 34830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080003ca0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 34840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8340 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ca8 o: 'h0000000080003ca8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ca8, write: False, capStore: False, potentialCapLoad: False } + 34840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080003ca0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 34840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080003ca0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 34840 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } + 34840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 34840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hb51, localHist: 'h005, globalTaken: True, localTaken: False, pcIndex: 'h1ae }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 59 <= 0000000000000000000000001fffff44000000 + 34850 : [doFinishMem] DTlbResp { resp: <'h0000000080003ca8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ca8 o: 'h0000000080003ca8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ca8, check_high: 'h00000000080003cb0, check_inclusive: True } }, specBits: 'h000 } + 34850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080003ca8, shiftedBE: tagged DataMemAccess , pcHash: 'h833a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34850 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 66 <= 0000000000000000000000001fffff44000000 + 34850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } + 34850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 34850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080003ca8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000015a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 34860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 34860 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 42 <= 0000000020000f28000000001fffff44000000 + 34860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 34860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080003ca8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + 34860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080003ca8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + 34860 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } + 34860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 34860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080003ca0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 34870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8354 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34870 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 61 <= 0000000000000006000000001fffff44000000 + 34870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 34870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cb0 +After delta: vaddr = 0x80003cb0 + 34870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 34880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 34880 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 + 34880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080003ca0 o: 'h0000000080003ca0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cb0 o: 'h0000000080003cb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cb0, write: False, capStore: False, potentialCapLoad: False } + 34880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 34880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 34890 : [doFinishMem] DTlbResp { resp: <'h0000000080003cb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cb0 o: 'h0000000080003cb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cb0, check_high: 'h00000000080003cb4, check_inclusive: True } }, specBits: 'h000 } + 34890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080003cb0, shiftedBE: tagged DataMemAccess , pcHash: 'h8344 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } + 34890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 34890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080003cb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 64 <= 00000000200003e4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } + 34900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 34900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080003cb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + 34900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080003cb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + 34900 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 34900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 34900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h03, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080003ca8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 34910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8358 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34910 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6e <= 0000000000000019000000001fffff44000000 + 34910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 34910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 34910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h5a8, localHist: 'h3d5, globalTaken: True, localTaken: True, pcIndex: 'h169 }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 34920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } + 34920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h84ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34920 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000000000000001fffff44000000 + 34920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + 34920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffbc, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f4c +After delta: vaddr = 0x80000f4c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h002 } + 34930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h84bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34930 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 00000000200000be800000001fffff44000000 + 34930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffbc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000064 o: 'h0000000000000064 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080003cb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 34940 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 79 <= 00000000200003f4000000001fffff44000000 + 34940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff99c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 34950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h033, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h033, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0d <= 0000000000000000c00000001fffff44000000 + 34960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h031, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h031, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h033, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 34970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82fe } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h030 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h032, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 02 <= 00000000200010b9000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 34980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 34980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 34980 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 34980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 34980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6a <= 0000000020000f20000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h010 } + 34990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34990 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000000000000800000001fffff44000000 + 34990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } + 34990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 34990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 34990 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 34990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 67 <= 00000000200000bc800000001fffff44000000 +[RFile] wr_ 1: r 0b <= 00000000200003cc000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35000 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h010 } + 35000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h82ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35000 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000000800000001fffff44000000 + 35000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 35000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 35000 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } + 35000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h012 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 35000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7e <= 00000000200000be800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35010 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000000000000800000001fffff44000000 + 35010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800002fa o: 'h00000000800002fa b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 35010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 35010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 35010 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 35010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 35010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6b <= 00000000200003e4000000001fffff44000000 +[RFile] wr_ 1: r 05 <= 0000000000000000c00000001fffff44000000 + 35020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h010 } + 35020 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000000000000000000001fffff44000000 + 35020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: True, capStore: False, potentialCapLoad: False } + 35020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 35020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 35030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 35030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 35030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 35030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 01 <= 0000000000000010000000001fffff44000000 + 35040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 35040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 35040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 35040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'had4, localHist: 'h3aa, globalTaken: True, localTaken: True, pcIndex: 'h168 }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 35130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 35140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 52 <= 0000000000000000c00000001fffff44000000 + 35150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 35150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 35150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff99c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 35160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 35160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 35160 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } + 35160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } + 35170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35170 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5c <= 0000000000000000800000001fffff44000000 + 35170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 51 <= 00000000200010b9000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 35180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 35180 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } + 35180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 56 <= 0000000020000f20000000001fffff44000000 + 35190 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7b <= 0000000000000000800000001fffff44000000 + 35190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } +instret:899 PC:0x1ffff00000000000000000000800002ca instr:0xfc442583 iType:Ld [doCommitNormalInst [0]] 3519 +instret:900 PC:0x1ffff00000000000000000000800002ce instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 3519 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4a <= 00000000200000bc800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35200 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h001 } + 35200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h82ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 65 <= 00000000200000be800000001fffff44000000 + 35210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 35210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 35210 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 35210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 35210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:901 PC:0x1ffff00000000000000000000800002d0 instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 3521 +instret:902 PC:0x1ffff00000000000000000000800002d8 instr:0x0040006f iType:J [doCommitNormalInst [1]] 3521 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 76 <= 0000000000000010000000001fffff44000000 +[RFile] wr_ 1: r 60 <= 00000000200003cc000000001fffff44000000 + 35220 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000000000000001fffff44000000 + 35220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800002fa o: 'h00000000800002fa b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 35220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 35220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:903 PC:0x1ffff00000000000000000000800002dc instr:0xfc442503 iType:Ld [doCommitNormalInst [0]] 3522 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 57 <= 0000000020000f30000000001fffff44000000 +[RFile] wr_ 1: r 6d <= 00000000200003e4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 35230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 35230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 35230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 35230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:904 PC:0x1ffff00000000000000000000800002e0 instr:0x00551593 iType:Alu [doCommitNormalInst [0]] 3523 +instret:905 PC:0x1ffff00000000000000000000800002e4 instr:0x00004517 iType:Auipc [doCommitNormalInst [1]] 3523 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 35240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 35240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 35240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 35240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:906 PC:0x1ffff00000000000000000000800002e8 instr:0x99c50513 iType:Alu [doCommitNormalInst [0]] 3524 +instret:907 PC:0x1ffff00000000000000000000800002ec instr:0x0000952e iType:Alu [doCommitNormalInst [1]] 3524 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 35250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 35250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 35250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +instret:908 PC:0x1ffff00000000000000000000800002ee instr:0xfd04258f iType:Ld [doCommitNormalInst [0]] 3525 +instret:909 PC:0x1ffff00000000000000000000800002f2 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 3525 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 35260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 35260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:910 PC:0x1ffff00000000000000000000800002f6 instr:0x02a080e7 iType:Jr [doCommitNormalInst [0]] 3526 +instret:911 PC:0x1ffff000000000000000000008000031c instr:0x0000711d iType:Alu [doCommitNormalInst [1]] 3526 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 35270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 35270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h832c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 35270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +instret:912 PC:0x1ffff000000000000000000008000031e instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 3527 +instret:913 PC:0x1ffff0000000000000000000080000320 instr:0x0000e8a2 iType:St [doCommitNormalInst [1]] 3527 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h831e } + 35280 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000020000f30000000001fffff44000000 + 35280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 35280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } +instret:914 PC:0x1ffff0000000000000000000080000322 instr:0x00001080 iType:Alu [doCommitNormalInst [0]] 3528 +instret:915 PC:0x1ffff0000000000000000000080000324 instr:0xfea43423 iType:St [doCommitNormalInst [1]] 3528 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 35290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8336 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 35290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } + 35290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cc0 +After delta: vaddr = 0x80003cc0 + 35290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:916 PC:0x1ffff0000000000000000000080000328 instr:0xfcb44823 iType:St [doCommitNormalInst [0]] 3529 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8320 } + 35300 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000020000f30000000001fffff44000000 + 35300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cc0, write: False, capStore: False, potentialCapLoad: False } + 35300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 35300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } +instret:917 PC:0x1ffff000000000000000000008000032c instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3530 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 35310 : [doFinishMem] DTlbResp { resp: <'h0000000080003cc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cc0, check_high: 'h00000000080003cc8, check_inclusive: True } }, specBits: 'h000 } + 35310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080003cc0, shiftedBE: tagged DataMemAccess , pcHash: 'h8330 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 35310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } + 35310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cc8 +After delta: vaddr = 0x80003cc8 + 35310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080003cc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8324 } + 35320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8340 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 35320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cc8 o: 'h0000000080003cc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cc8, write: False, capStore: False, potentialCapLoad: False } + 35320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080003cc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 35320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080003cc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 35320 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } + 35320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35330 : [doFinishMem] DTlbResp { resp: <'h0000000080003cc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cc8 o: 'h0000000080003cc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cc8, check_high: 'h00000000080003cd0, check_inclusive: True } }, specBits: 'h000 } + 35330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080003cc8, shiftedBE: tagged DataMemAccess , pcHash: 'h833a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35330 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 66 <= 0000000000000000000000001fffff44000000 + 35330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } + 35330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 35330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080003cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hd6a, localHist: 'h002, globalTaken: True, localTaken: False, pcIndex: 'h1ae }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 59 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080003cc0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8328 } + 35340 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 42 <= 0000000020000f30000000001fffff44000000 + 35340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } + 35340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080003cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + 35340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080003cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + 35340 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } + 35340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 35340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000015a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 35350 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 61 <= 0000000000000006000000001fffff44000000 + 35350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 35350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } + 35350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cd0 +After delta: vaddr = 0x80003cd0 + 35350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35350 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080003d00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:918 PC:0x1ffff0000000000000000000080000330 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 3535 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 35360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cd0 o: 'h0000000080003cd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cd0, write: False, capStore: False, potentialCapLoad: False } + 35360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080003d00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 35360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080003d00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 35360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 35360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35360 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 35370 : [doFinishMem] DTlbResp { resp: <'h0000000080003cd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cd0 o: 'h0000000080003cd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cd0, check_high: 'h00000000080003cd4, check_inclusive: True } }, specBits: 'h000 } + 35370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080003cd0, shiftedBE: tagged DataMemAccess , pcHash: 'h8344 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } + 35370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 35370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 35370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 35370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080003cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } +instret:919 PC:0x1ffff0000000000000000000080000332 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3537 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8332 } + 35380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 35380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080003cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + 35380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080003cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + 35380 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 35380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 35380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 64 <= 00000000200003e4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080003cc8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 35390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8354 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 35390 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6e <= 0000000000000064000000001fffff44000000 + 35390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 35390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } + 35390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 35390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:920 PC:0x1ffff0000000000000000000080000336 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3539 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h03, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 35400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 35400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8358 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35400 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 + 35400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 35400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffbc, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f4c +After delta: vaddr = 0x80000f4c + 35400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } +instret:921 PC:0x1ffff000000000000000000008000033a instr:0x00006508 iType:Ld [doCommitNormalInst [0]] 3540 +instret:922 PC:0x1ffff000000000000000000008000033c instr:0xfca43023 iType:St [doCommitNormalInst [1]] 3540 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h6b5, localHist: 'h3ea, globalTaken: True, localTaken: False, pcIndex: 'h169 }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h833c } + 35410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h84ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffbc, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000190 o: 'h0000000000000190 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } + 35410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } + 35410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } + 35410 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 35410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 35410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ba } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080003cd0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 35420 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000000000000001fffff44000000 + 35420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + 35420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ba } + 35420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ba } + 35420 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } + 35420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +instret:923 PC:0x1ffff0000000000000000000080000340 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3542 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000038 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h002 } + 35430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h84bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35430 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 00000000200000be800000001fffff44000000 + 35430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 35430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84bc } +instret:924 PC:0x1ffff0000000000000000000080000344 instr:0x00004908 iType:Ld [doCommitNormalInst [0]] 3543 +instret:925 PC:0x1ffff0000000000000000000080000346 instr:0xfaa42e23 iType:St [doCommitNormalInst [1]] 3543 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0d <= 0000000000000000c00000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8346 } + 35440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84bc } + 35440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84bc } + 35440 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } + 35440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } +instret:926 PC:0x1ffff000000000000000000008000034a instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 3544 +instret:927 PC:0x1ffff000000000000000000008000034c instr:0xfaa42c23 iType:St [doCommitNormalInst [1]] 3544 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35450 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 79 <= 00000000200003f4000000001fffff44000000 + 35450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 35450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:928 PC:0x1ffff0000000000000000000080000350 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3545 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h834c } + 35460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 35460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } +instret:929 PC:0x1ffff0000000000000000000080000354 instr:0xfb842503 iType:Ld [doCommitNormalInst [0]] 3546 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h019, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 63 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 35470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } + 35470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 35470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:930 PC:0x1ffff0000000000000000000080000358 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 3547 +instret:931 PC:0x1ffff000000000000000000008000035c instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 3547 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 35480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82fe } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 35480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 35480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } +instret:932 PC:0x1ffff0000000000000000000080000360 instr:0x15a0006f iType:J [doCommitNormalInst [0]] 3548 +instret:933 PC:0x1ffff00000000000000000000800004ba instr:0x000060e6 iType:Ld [doCommitNormalInst [1]] 3548 +calling cycle +[RFile] wr_ 0: r 68 <= 00000000200003f4000000001fffff44000000 + 35490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 35490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: False, potentialCapLoad: True } + 35490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 35490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 35490 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 35490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc8 +After delta: vaddr = 0x80000fc8 + 35490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } +instret:934 PC:0x1ffff00000000000000000000800004bc instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 3549 +instret:935 PC:0x1ffff00000000000000000000800004be instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 3549 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h012, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 35500 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h010 } + 35500 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000000000000800000001fffff44000000 + 35500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc8, write: False, capStore: False, potentialCapLoad: False } + 35500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 35500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 35500 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 35500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc0 +After delta: vaddr = 0x80000fc0 +instret:936 PC:0x1ffff00000000000000000000800004c0 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 3550 +instret:937 PC:0x1ffff00000000000000000000800002fa instr:0x0040006f iType:J [doCommitNormalInst [1]] 3550 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35510 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc8, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h010 } + 35510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000fc8, shiftedBE: tagged DataMemAccess , pcHash: 'h8314 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35510 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000000800000001fffff44000000 + 35510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc0, write: False, capStore: False, potentialCapLoad: False } + 35510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8314 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h03, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h013, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 35520 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc0, check_high: 'h00000000080000fc8, check_inclusive: True } }, specBits: 'h010 } + 35520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000fc0, shiftedBE: tagged DataMemAccess , pcHash: 'h8316 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8314 } + 35520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8314 } + 35520 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } + 35520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 35520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8316 } +instret:938 PC:0x1ffff00000000000000000000800002fe instr:0xfc442503 iType:Ld [doCommitNormalInst [0]] 3552 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h35a, localHist: 'h3ea, globalTaken: True, localTaken: False, pcIndex: 'h169 }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 05 <= 0000000000000000c00000001fffff44000000 + 35530 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 02 <= 000000002000013a000000001fffff44000000 + 35530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: True, capStore: False, potentialCapLoad: False } + 35530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8316 } + 35530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8316 } + 35530 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } + 35530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000038 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ALU redirect - 1] 'h1ffff00000000000000000000800002d8; 'h4; InstTag { way: 'h1, ptr: 'h16, t: 'h2d } + 35540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 35540 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6a <= 0000000020000400000000001fffff44000000 + 35540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:939 PC:0x1ffff0000000000000000000080000302 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 3554 +calling cycle +[ROB incorrectSpec] 'h4 ; InstTag { way: 'h1, ptr: 'h16, t: 'h2d } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:940 PC:0x1ffff0000000000000000000080000304 instr:0xfca42223 iType:St [doCommitNormalInst [0]] 3556 +instret:941 PC:0x1ffff0000000000000000000080000308 instr:0xfc3ff06f iType:J [doCommitNormalInst [1]] 3556 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8304 } + 35570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } +calling cycle + 35580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } + 35580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hb5a, localHist: 'h3d5, globalTaken: True, localTaken: True, pcIndex: 'h168 }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 35670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 35680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0d <= 0000000000000000c00000001fffff44000000 + 35690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 35690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 35690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff99c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 35700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 35700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 35700 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 35700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } + 35710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35710 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000000c00000001fffff44000000 + 35710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 02 <= 00000000200010b9000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 35720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 35720 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } + 35720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6a <= 0000000020000f20000000001fffff44000000 + 35730 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000000000000c00000001fffff44000000 + 35730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } +instret:942 PC:0x1ffff00000000000000000000800002ca instr:0xfc442583 iType:Ld [doCommitNormalInst [0]] 3573 +instret:943 PC:0x1ffff00000000000000000000800002ce instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 3573 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 67 <= 00000000200000bc800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35740 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h001 } + 35740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h82ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7e <= 00000000200000be800000001fffff44000000 + 35750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 35750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 35750 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 35750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 35750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:944 PC:0x1ffff00000000000000000000800002d0 instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 3575 +instret:945 PC:0x1ffff00000000000000000000800002d8 instr:0x0040006f iType:J [doCommitNormalInst [1]] 3575 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 01 <= 0000000000000018000000001fffff44000000 +[RFile] wr_ 1: r 0b <= 00000000200003cc000000001fffff44000000 + 35760 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000000000000000000001fffff44000000 + 35760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800002fa o: 'h00000000800002fa b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 35760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 35760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:946 PC:0x1ffff00000000000000000000800002dc instr:0xfc442503 iType:Ld [doCommitNormalInst [0]] 3576 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 68 <= 0000000020000f38000000001fffff44000000 +[RFile] wr_ 1: r 6b <= 00000000200003e4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 35770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 35770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 35770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 35770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:947 PC:0x1ffff00000000000000000000800002e0 instr:0x00551593 iType:Alu [doCommitNormalInst [0]] 3577 +instret:948 PC:0x1ffff00000000000000000000800002e4 instr:0x00004517 iType:Auipc [doCommitNormalInst [1]] 3577 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 35780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 35780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 35780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 35780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:949 PC:0x1ffff00000000000000000000800002e8 instr:0x99c50513 iType:Alu [doCommitNormalInst [0]] 3578 +instret:950 PC:0x1ffff00000000000000000000800002ec instr:0x0000952e iType:Alu [doCommitNormalInst [1]] 3578 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 35790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 35790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 35790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +instret:951 PC:0x1ffff00000000000000000000800002ee instr:0xfd04258f iType:Ld [doCommitNormalInst [0]] 3579 +instret:952 PC:0x1ffff00000000000000000000800002f2 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 3579 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 35800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 35800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:953 PC:0x1ffff00000000000000000000800002f6 instr:0x02a080e7 iType:Jr [doCommitNormalInst [0]] 3580 +instret:954 PC:0x1ffff000000000000000000008000031c instr:0x0000711d iType:Alu [doCommitNormalInst [1]] 3580 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 35810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 35810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h832c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 35810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +instret:955 PC:0x1ffff000000000000000000008000031e instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 3581 +instret:956 PC:0x1ffff0000000000000000000080000320 instr:0x0000e8a2 iType:St [doCommitNormalInst [1]] 3581 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h831e } + 35820 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 0000000020000f38000000001fffff44000000 + 35820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 35820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } +instret:957 PC:0x1ffff0000000000000000000080000322 instr:0x00001080 iType:Alu [doCommitNormalInst [0]] 3582 +instret:958 PC:0x1ffff0000000000000000000080000324 instr:0xfea43423 iType:St [doCommitNormalInst [1]] 3582 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 35830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8336 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 35830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } + 35830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831e } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ce0 +After delta: vaddr = 0x80003ce0 + 35830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:959 PC:0x1ffff0000000000000000000080000328 instr:0xfcb44823 iType:St [doCommitNormalInst [0]] 3583 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8320 } + 35840 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 0000000020000f38000000001fffff44000000 + 35840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ce0, write: False, capStore: False, potentialCapLoad: False } + 35840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 35840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } +instret:960 PC:0x1ffff000000000000000000008000032c instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3584 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 35850 : [doFinishMem] DTlbResp { resp: <'h0000000080003ce0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ce0, check_high: 'h00000000080003ce8, check_inclusive: True } }, specBits: 'h000 } + 35850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080003ce0, shiftedBE: tagged DataMemAccess , pcHash: 'h8330 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 35850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } + 35850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ce8 +After delta: vaddr = 0x80003ce8 + 35850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003ce0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8324 } + 35860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8340 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 35860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ce8 o: 'h0000000080003ce8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ce8, write: False, capStore: False, potentialCapLoad: False } + 35860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003ce0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 35860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003ce0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 35860 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } + 35860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35870 : [doFinishMem] DTlbResp { resp: <'h0000000080003ce8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ce8 o: 'h0000000080003ce8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ce8, check_high: 'h00000000080003cf0, check_inclusive: True } }, specBits: 'h000 } + 35870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080003ce8, shiftedBE: tagged DataMemAccess , pcHash: 'h833a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35870 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 55 <= 0000000000000000000000001fffff44000000 + 35870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } + 35870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8324 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 35870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080003ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdad, localHist: 'h001, globalTaken: True, localTaken: False, pcIndex: 'h1ae }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7b <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080003ce0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8328 } + 35880 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4b <= 0000000020000f38000000001fffff44000000 + 35880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } + 35880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080003ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + 35880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080003ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833a } + 35880 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } + 35880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 35880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000015a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 35890 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 41 <= 0000000000000006000000001fffff44000000 + 35890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 35890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } + 35890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cf0 +After delta: vaddr = 0x80003cf0 + 35890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:961 PC:0x1ffff0000000000000000000080000330 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 3589 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 35900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cf0 o: 'h0000000080003cf0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cf0, write: False, capStore: False, potentialCapLoad: False } + 35900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 35900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35900 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080003d28, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 35910 : [doFinishMem] DTlbResp { resp: <'h0000000080003cf0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cf0 o: 'h0000000080003cf0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cf0, check_high: 'h00000000080003cf4, check_inclusive: True } }, specBits: 'h000 } + 35910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080003cf0, shiftedBE: tagged DataMemAccess , pcHash: 'h8344 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } + 35910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080003d28, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 35910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080003d28, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 35910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 35910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080003cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } +instret:962 PC:0x1ffff0000000000000000000080000332 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3591 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8332 } + 35920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 35920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080003cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + 35920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080003cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + 35920 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } + 35920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 35920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 08 <= 00000000200003e4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080003ce8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 35930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8354 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 35930 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 0000000000000190000000001fffff44000000 + 35930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 35930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } + 35930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8332 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 35930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35930 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080003d68, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:963 PC:0x1ffff0000000000000000000080000336 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3593 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h03, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 35940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 35940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8358 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35940 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000000000000001fffff44000000 + 35940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 35940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080003d68, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 35940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080003d68, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 35940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffbc, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f4c +After delta: vaddr = 0x80000f4c + 35940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } +instret:964 PC:0x1ffff000000000000000000008000033a instr:0x00006508 iType:Ld [doCommitNormalInst [0]] 3594 +instret:965 PC:0x1ffff000000000000000000008000033c instr:0xfca43023 iType:St [doCommitNormalInst [1]] 3594 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h6d6, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h169 }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h833c } + 35950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h84ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffbc, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000640 o: 'h0000000000000640 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } + 35950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } + 35950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } + 35950 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 35950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 35950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ba } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080003cf0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 35960 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 0000000000000000000000001fffff44000000 + 35960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + 35960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ba } + 35960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ba } + 35960 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } + 35960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +instret:966 PC:0x1ffff0000000000000000000080000340 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3596 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000038 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h002 } + 35970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h84bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35970 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5d <= 00000000200000be800000001fffff44000000 + 35970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 35970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84bc } +instret:967 PC:0x1ffff0000000000000000000080000344 instr:0x00004908 iType:Ld [doCommitNormalInst [0]] 3597 +instret:968 PC:0x1ffff0000000000000000000080000346 instr:0xfaa42e23 iType:St [doCommitNormalInst [1]] 3597 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7c <= 0000000000000000c00000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8346 } + 35980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84bc } + 35980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84bc } + 35980 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } + 35980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } +instret:969 PC:0x1ffff000000000000000000008000034a instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 3598 +instret:970 PC:0x1ffff000000000000000000008000034c instr:0xfaa42c23 iType:St [doCommitNormalInst [1]] 3598 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35990 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 00000000200003f4000000001fffff44000000 + 35990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 35990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35990 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003d30, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:971 PC:0x1ffff0000000000000000000080000350 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3599 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h834c } + 36000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003d30, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 36000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003d30, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 36000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 36000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 36000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } +instret:972 PC:0x1ffff0000000000000000000080000354 instr:0xfb842503 iType:Ld [doCommitNormalInst [0]] 3600 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h019, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5a <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 36010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 36010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } + 36010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 36010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 36010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 36010 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080003d70, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:973 PC:0x1ffff0000000000000000000080000358 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 3601 +instret:974 PC:0x1ffff000000000000000000008000035c instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 3601 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h012, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 36020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 36020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82fe } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 36020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080003d70, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 36020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080003d70, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 36020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 36020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 36020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } +instret:975 PC:0x1ffff0000000000000000000080000360 instr:0x15a0006f iType:J [doCommitNormalInst [0]] 3602 +instret:976 PC:0x1ffff00000000000000000000800004ba instr:0x000060e6 iType:Ld [doCommitNormalInst [1]] 3602 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 59 <= 00000000200003f4000000001fffff44000000 + 36030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 36030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: False, potentialCapLoad: True } + 36030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 36030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 36030 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } + 36030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc8 +After delta: vaddr = 0x80000fc8 + 36030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 36030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } +instret:977 PC:0x1ffff00000000000000000000800004bc instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 3603 +instret:978 PC:0x1ffff00000000000000000000800004be instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 3603 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h03, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h013, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 36040 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h010 } + 36040 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 57 <= 0000000000000000c00000001fffff44000000 + 36040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc8, write: False, capStore: False, potentialCapLoad: False } + 36040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 36040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 36040 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } + 36040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc0 +After delta: vaddr = 0x80000fc0 +instret:979 PC:0x1ffff00000000000000000000800004c0 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 3604 +instret:980 PC:0x1ffff00000000000000000000800002fa instr:0x0040006f iType:J [doCommitNormalInst [1]] 3604 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h36b, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h169 }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 36050 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc8, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h010 } + 36050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000fc8, shiftedBE: tagged DataMemAccess , pcHash: 'h8314 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36050 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000000000000c00000001fffff44000000 + 36050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc0, write: False, capStore: False, potentialCapLoad: False } + 36050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 36050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8314 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000038 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 36060 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc0, check_high: 'h00000000080000fc8, check_inclusive: True } }, specBits: 'h010 } + 36060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000fc0, shiftedBE: tagged DataMemAccess , pcHash: 'h8316 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8314 } + 36060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8314 } + 36060 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } + 36060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 36060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8316 } +instret:981 PC:0x1ffff00000000000000000000800002fe instr:0xfc442503 iType:Ld [doCommitNormalInst [0]] 3606 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 71 <= 0000000000000001000000001fffff44000000 + 36070 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6f <= 000000002000013a000000001fffff44000000 + 36070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: True, capStore: False, potentialCapLoad: False } + 36070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8316 } + 36070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8316 } + 36070 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 36070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ALU redirect - 1] 'h1ffff00000000000000000000800002d8; 'h4; InstTag { way: 'h1, ptr: 'h16, t: 'h2d } + 36080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 36080 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000020000400000000001fffff44000000 + 36080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:982 PC:0x1ffff0000000000000000000080000302 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 3608 +calling cycle +[ROB incorrectSpec] 'h4 ; InstTag { way: 'h1, ptr: 'h16, t: 'h2d } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:983 PC:0x1ffff0000000000000000000080000304 instr:0xfca42223 iType:St [doCommitNormalInst [0]] 3610 +instret:984 PC:0x1ffff0000000000000000000080000308 instr:0xfc3ff06f iType:J [doCommitNormalInst [1]] 3610 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8304 } + 36110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } +calling cycle + 36120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } + 36120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 36120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 36200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hb6b, localHist: 'h3ea, globalTaken: True, localTaken: False, pcIndex: 'h168 }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 36210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 +calling cycle + 36220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[RFile] wr_ 1: r 7c <= 0000000000000000c00000001fffff44000000 + 36230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 36230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000038 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 36240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 36240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 36240 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } + 36240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 36250 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000000000001000000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 36260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 36270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 36270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:985 PC:0x1ffff00000000000000000000800002ca instr:0xfc442583 iType:Ld [doCommitNormalInst [0]] 3627 +instret:986 PC:0x1ffff00000000000000000000800002ce instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 3627 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5a <= 0000000000000000000000001fffff44000000 + 36280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: False, potentialCapLoad: True } + 36280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc8 +After delta: vaddr = 0x80000fc8 + 36280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 36290 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 36290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc8, write: False, capStore: False, potentialCapLoad: False } + 36290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc0 +After delta: vaddr = 0x80000fc0 +instret:987 PC:0x1ffff00000000000000000000800002d0 instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 3629 +instret:988 PC:0x1ffff00000000000000000000800002d4 instr:0x0380006f iType:J [doCommitNormalInst [1]] 3629 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 59 <= 00000000200003f4000000001fffff44000000 + 36300 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc8, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h000 } + 36300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000fc8, shiftedBE: tagged DataMemAccess , pcHash: 'h8314 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc0, write: False, capStore: False, potentialCapLoad: False } + 36300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8314 } +instret:989 PC:0x1ffff000000000000000000008000030c instr:0xfea0055b iType:Cap [doCommitNormalInst [0]] 3630 +instret:990 PC:0x1ffff0000000000000000000080000310 instr:0xfca44823 iType:St [doCommitNormalInst [1]] 3630 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h03, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 36310 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc0, check_high: 'h00000000080000fc8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8310 } + 36310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000fc0, shiftedBE: tagged DataMemAccess , pcHash: 'h8316 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8314 } + 36310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8314 } + 36310 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } + 36310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8316 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h5b5, localHist: 'h3fa, globalTaken: True, localTaken: False, pcIndex: 'h169 }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 36320 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6f <= 000000002000013a000000001fffff44000000 + 36320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8316 } + 36320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8316 } + 36320 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 36320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8310 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000038 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000fc8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 36330 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000020000400000000001fffff44000000 + 36330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8310 } + 36330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8310 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 36330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000fc0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 36340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc4 +After delta: vaddr = 0x80000fc4 + 36340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:991 PC:0x1ffff0000000000000000000080000314 instr:0x000070e2 iType:Ld [doCommitNormalInst [0]] 3634 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ALU redirect - 1] 'h1ffff00000000000000000000800004e8; 'h2; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } + 36350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc4 o: 'h0000000080000fc4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc4, write: False, capStore: False, potentialCapLoad: False } + 36350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc4 +After delta: vaddr = 0x80000fc4 + 36350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:992 PC:0x1ffff0000000000000000000080000316 instr:0x00007442 iType:Ld [doCommitNormalInst [0]] 3635 +instret:993 PC:0x1ffff0000000000000000000080000318 instr:0x00006121 iType:Alu [doCommitNormalInst [1]] 3635 +calling cycle +[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:994 PC:0x1ffff000000000000000000008000031a instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 3637 +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 36420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 36430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd8 +After delta: vaddr = 0x80000fd8 + 36430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 36440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd8, write: False, capStore: False, potentialCapLoad: False } + 36440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff8 +After delta: vaddr = 0x80000ff8 + 36440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 36450 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd8, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 36450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000fd8, shiftedBE: tagged DataMemAccess , pcHash: 'h84e8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } + 36450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff0 +After delta: vaddr = 0x80000ff0 + 36450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000fd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84e8 } +calling cycle + 36460 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } + 36460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h84ec } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } + 36460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000fd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84e8 } + 36460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000fd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84e8 } + 36460 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } + 36460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ec } +calling cycle +[RFile] wr_ 1: r 6d <= 0000000020000400000000001fffff44000000 + 36470 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } + 36470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h84ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36470 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 43 <= 0000000000000000000000001fffff44000000 + 36470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ec } + 36470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ec } + 36470 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } + 36470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ee } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000fd8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 36480 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4c <= 0000000020000006000000001fffff44000000 + 36480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ee } + 36480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ee } + 36480 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } + 36480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000ff8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 36490 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 65 <= 0000000000000000000000001fffff44000000 + 36490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:995 PC:0x1ffff00000000000000000000800004e8 instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 3649 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000ff0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 36500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 33554431 +Before delta: vaddr = 0xffffffffffffffc4 +After delta: vaddr = 0xffffffffffffffc4 +instret:996 PC:0x1ffff00000000000000000000800004ec instr:0x000070a2 iType:Ld [doCommitNormalInst [0]] 3650 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h03, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000018; 'h0; InstTag { way: 'h0, ptr: 'h07, t: 'h0e } + 36510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'hffffffffffffffc4 o: 'hffffffffffffffc4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'hffffffffffffffc4, write: False, capStore: False, potentialCapLoad: False } + 36510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:997 PC:0x1ffff00000000000000000000800004ee instr:0x00007402 iType:Ld [doCommitNormalInst [0]] 3651 +instret:998 PC:0x1ffff00000000000000000000800004f0 instr:0x00006145 iType:Alu [doCommitNormalInst [1]] 3651 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h07, t: 'h0e } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:999 PC:0x1ffff00000000000000000000800004f2 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 3653 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 36590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7d <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 46 <= 0000000000000000000000001fffff44000000 + 36600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x00000000 +After delta: vaddr = 0x00000000 + 36600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 75 <= 0000000000000000400000001fffff44000000 + 36610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000000000, write: True, capStore: False, potentialCapLoad: False } + 36610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff8 +After delta: vaddr = 0x80000ff8 + 36610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:1000 PC:0x1ffff0000000000000000000080000018 instr:0x0000832a iType:Alu [doCommitNormalInst [0]] 3661 +instret:1001 PC:0x1ffff000000000000000000008000001a instr:0x00004281 iType:Alu [doCommitNormalInst [1]] 3661 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0e <= 00000000200003e4000000001fffff44000000 + 36620 : [doFinishMem] DTlbResp { resp: <'h0000000000000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000000000, check_high: 'h00000000000000008, check_inclusive: True } }, specBits: 'h000 } + 36620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000068, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000018 o: 'h0000000080000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: True, capStore: False, potentialCapLoad: False } + 36620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff0 +After delta: vaddr = 0x80000ff0 + 36620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:1002 PC:0x1ffff000000000000000000008000001c instr:0x00004305 iType:Alu [doCommitNormalInst [0]] 3662 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 05 <= 0000000020000400000000001fffff44000000 + 36630 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } + 36630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000060, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: True, capStore: False, potentialCapLoad: False } + 36630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd8 +After delta: vaddr = 0x80000fd8 + 36630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000004ce }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 36640 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_MMIO_issue] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000000000000, isMMIO: True, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h801e }; MMIOCRq { addr: 'h0000000000000000, func: tagged St , byteEn: , data: TaggedData { tag: False, data: }, loadTags: False } + 36640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd8, write: True, capStore: False, potentialCapLoad: False } + 36640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd8 +After delta: vaddr = 0x80000fd8 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 36650 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd8, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 36650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd8, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 36660 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd8, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 36660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000fd8, shiftedBE: tagged DataMemAccess , pcHash: 'h802e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 36660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00002000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000771 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 02 <= 000000002000040e800000001fffff44000000 + 36670 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000000000000000000001fffff44000000 + 36670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001508 +After delta: vaddr = 0x80001508 + 36670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h16d, localHist: 'h355, globalTaken: True, localTaken: True, pcIndex: 'h028 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +3668: mmioPlatform.rl_tohost: 0x1 (= 1) +PASS diff --git a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test-error-2.txt b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test-error-2.txt new file mode 100644 index 0000000..8597f50 --- /dev/null +++ b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test-error-2.txt @@ -0,0 +1,19308 @@ +make -C ../../Tests/elf_to_hex +make[1]: Entering directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/TooobaTest/Toooba/Tests/elf_to_hex' +make[1]: 'elf_to_hex' is up to date. +make[1]: Leaving directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/TooobaTest/Toooba/Tests/elf_to_hex' +../../Tests/elf_to_hex/elf_to_hex ../../Tests/isa/testC Mem.hex +c_mem_load_elf: ../../Tests/isa/testC is a 64-bit ELF file +Section .text : addr 80000000 to addr 80000532; size 0x 532 (= 1330) bytes +Section .data : addr 80001534 to addr 80001544; size 0x 10 (= 16) bytes +Section .sbss : addr 80001548 to addr 80001550; size 0x 8 (= 8) bytes +Section .bss : addr 80001550 to addr 80003e40; size 0x 28f0 (= 10480) bytes +Section .riscv.attributes: Ignored +Section .comment : Ignored +Section .symtab : Searching for addresses of '_start', 'exit' and 'tohost' symbols +Writing symbols to: symbol_table.txt + No 'exit' label found + No 'tohost' symbol found +Section .shstrtab : Ignored +Section .strtab : Ignored +Min addr: 80000000 (hex) +Max addr: 80003e3f (hex) +Writing mem hex to file 'Mem.hex' +Subtracting 0x80000000 base from addresses +./exe_HW_sim +v1 +tohost +Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 498 to 33554430. +1: top.soc_top.rl_reset_start_initial ... +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +11: Mem_Controller.set_addr_map: addr_base 0x80000000 addr_lim 0xc0000000 + SoC address map: + Boot ROM: 0x1000 .. 0x2000 + Mem0 Controller: 0x80000000 .. 0xc0000000 + UART0: 0xc0000000 .. 0xc0000080 +11: top.soc_top.rl_reset_complete_initial +calling cycle +================================================================ +Bluespec RISC-V standalone system simulation v1.2 +Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved. +================================================================ +INFO: watch_tohost 1, tohost_addr = 0x0, fromhost_addr = 0x0 +12: top.soc_top.method start (tohost 0, fromhost 0) +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +100: top.soc_top.rl_step_0, n = 0, do_release +100: top.soc_top do_release(restartRunning: True, to_host_addr: 0) +100: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0 +calling cycle +101: top.soc_top.rl_ctrl_req +101: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0 +101: top.soc_top do_release(restartRunning: True, to_host_addr: 0) +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000020 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle +[RFile] wr_ 1: r 40 <= 0000000000000400000000001fffff44000000 +calling cycle +[RFile] wr_ 0: r 41 <= 0000000000000408000000001fffff44000000 +instret:0 PC:0x1ffff0000000000000000000000001000 instr:0x00000297 iType:Auipc [doCommitNormalInst [0]] 167 +calling cycle +instret:1 PC:0x1ffff0000000000000000000000001004 instr:0x02028593 iType:Alu [doCommitNormalInst [0]] 168 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Csr, execFunc: tagged Alu Csrs, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Valid csrAddrMHARTID, scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle +[RFile] wr_ 0: r 42 <= 0000000000000000000000001fffff44000000 +calling cycle +instret:2 PC:0x1ffff0000000000000000000000001008 instr:0xf1402573 iType:Csr [doCommitSystemInst] 224 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling 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+calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 3340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 3350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000018, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x00001018 +After delta: vaddr = 0x00001018 +calling cycle + 3360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000018, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000000001000 o: 'h0000000000001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000001018, write: False, capStore: False, potentialCapLoad: False } +calling cycle + 3370 : [doFinishMem] DTlbResp { resp: <'h0000000000001018,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000001018, check_high: 'h00000000000001020, check_inclusive: True } }, specBits: 'h000 } +calling cycle +calling cycle +[doDeqLdQ_MMIO_issue] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid }; MMIOCRq { addr: 'h0000000000001018, func: tagged Ld , byteEn: , data: TaggedData { tag: , data: }, loadTags: False } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +[RFile] wr_ 3: r 43 <= 0000000020000000000000001fffff44000000 +[doDeqLdQ_MMIO_deq] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid }; TaggedData { tag: False, data: }; TaggedData { tag: False, data: } +calling cycle +instret:3 PC:0x1ffff000000000000000000000000100c instr:0x0182b283 iType:Ld [doCommitNormalInst [0]] 403 +calling cycle +calling cycle +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000000; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:4 PC:0x1ffff0000000000000000000000001010 instr:0x00028067 iType:Jr [doCommitNormalInst [0]] 408 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling 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+calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00080000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipcc, execFunc: tagged Alu Add, capFunc: tagged CapModify tagged SpecialRW tagged TCC , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrPCC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h48, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h48, src2: tagged Valid 'h48, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000004f2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 46 <= 0000000000020000000000001fffff44000000 +[RFile] wr_ 1: r 45 <= 40000000200000000000ffff1fffff44000000 +calling cycle +[RFile] wr_ 1: r 47 <= 0000000000020000400000001fffff44000000 +instret:5 PC:0x1ffff0000000000000000000080000000 instr:0x020000db iType:Auipcc [doCommitNormalInst [0]] 1155 +instret:6 PC:0x1ffff0000000000000000000080000004 instr:0x000802b7 iType:Alu [doCommitNormalInst [1]] 1155 +calling cycle +[RFile] wr_ 0: r 48 <= 0000000020000400000000001fffff44000000 +instret:7 PC:0x1ffff0000000000000000000080000008 instr:0x00002285 iType:Alu [doCommitNormalInst [0]] 1156 +calling cycle +[RFile] wr_ 0: r 4a <= 0000000020000004000000001fffff44000000 +[RFile] wr_ 1: r 49 <= 0000000020000400000000001fffff44000000 +instret:8 PC:0x1ffff000000000000000000008000000a instr:0x000002b2 iType:Alu [doCommitNormalInst [0]] 1157 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4b <= 0000000020000006000000001fffff44000000 +[ALU redirect - 1] 'h1ffff0000000000000000000080000502; 'h0; InstTag { way: 'h1, ptr: 'h05, t: 'h0b } + 11580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:9 PC:0x1ffff000000000000000000008000000c instr:0x2052815b iType:Cap [doCommitNormalInst [0]] 1158 +instret:10 PC:0x1ffff0000000000000000000080000010 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1158 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h05, t: 'h0b } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:11 PC:0x1ffff0000000000000000000080000014 instr:0x4f2080e7 iType:Jr [doCommitNormalInst [0]] 1160 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 13430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 13440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff8 +After delta: vaddr = 0x80000ff8 + 13440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4c <= 00000000200003f4000000001fffff44000000 + 13450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000018 o: 'h0000000080000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: True, capStore: False, potentialCapLoad: False } + 13450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff0 +After delta: vaddr = 0x80000ff0 + 13450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4f <= 0000000020000400000000001fffff44000000 + 13460 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } + 13460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: True, capStore: False, potentialCapLoad: False } + 13460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd8 +After delta: vaddr = 0x80000fd8 + 13460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:12 PC:0x1ffff0000000000000000000080000502 instr:0x00007179 iType:Alu [doCommitNormalInst [0]] 1346 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 50 <= 0000000000000000000000001fffff44000000 + 13470 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } + 13470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd8, write: True, capStore: False, potentialCapLoad: False } + 13470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffec, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fec +After delta: vaddr = 0x80000fec + 13470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:13 PC:0x1ffff0000000000000000000080000504 instr:0x0000f406 iType:St [doCommitNormalInst [0]] 1347 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 53 <= 0000000000000000c00000001fffff44000000 + 13480 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd8, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8504 } + 13480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffec, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fec, write: True, capStore: False, potentialCapLoad: False } + 13480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fe0 +After delta: vaddr = 0x80000fe0 + 13480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 13480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8504 } +instret:14 PC:0x1ffff0000000000000000000080000506 instr:0x0000f022 iType:St [doCommitNormalInst [0]] 1348 +instret:15 PC:0x1ffff0000000000000000000080000508 instr:0x00001800 iType:Alu [doCommitNormalInst [1]] 1348 +calling cycle + 13490 : [doFinishMem] DTlbResp { resp: <'h0000000080000fec,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fec, check_high: 'h00000000080000ff0, check_inclusive: True } }, specBits: 'h000 } + 13490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe0 o: 'h0000000080000fe0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe0, write: True, capStore: False, potentialCapLoad: False } + 13490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 13490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8504 } + 13490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 13490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fe0 +After delta: vaddr = 0x80000fe0 +instret:16 PC:0x1ffff000000000000000000008000050a instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 1349 +instret:17 PC:0x1ffff000000000000000000008000050c instr:0xfca43c23 iType:St [doCommitNormalInst [1]] 1349 +calling cycle +[RFile] wr_ 1: r 56 <= 0000000020000147800000001fffff44000000 + 13500 : [doFinishMem] DTlbResp { resp: <'h0000000080000fe0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fe0 o: 'h0000000080000fe0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fe0, check_high: 'h00000000080000fe8, check_inclusive: True } }, specBits: 'h000 } + 13500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe0 o: 'h0000000080000fe0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe0, write: False, capStore: False, potentialCapLoad: False } +instret:18 PC:0x1ffff0000000000000000000080000510 instr:0xfea42623 iType:St [doCommitNormalInst [0]] 1350 +instret:19 PC:0x1ffff0000000000000000000080000514 instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 1350 +calling cycle + 13510 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8504 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000ff8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[RFile] wr_ 1: r 57 <= 0000000020000149800000001fffff44000000 +[ALU redirect - 1] 'h1ffff00000000000000000000800001ae; 'h0; InstTag { way: 'h1, ptr: 'h0b, t: 'h17 } + 13510 : [doFinishMem] DTlbResp { resp: <'h0000000080000fe0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fe0 o: 'h0000000080000fe0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fe0, check_high: 'h00000000080000fe8, check_inclusive: True } }, specBits: 'h000 } + 13510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000fe0, shiftedBE: tagged DataMemAccess , pcHash: 'h851a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, data: TaggedData { tag: False, data: } } +instret:20 PC:0x1ffff0000000000000000000080000516 instr:0xfea43023 iType:St [doCommitNormalInst [0]] 1351 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h0b, t: 'h17 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 13530 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 55 <= 0000000000000000c00000001fffff44000000 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000fe0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +calling cycle +instret:21 PC:0x1ffff000000000000000000008000051a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 1355 +instret:22 PC:0x1ffff000000000000000000008000051e instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1355 +calling cycle +instret:23 PC:0x1ffff0000000000000000000080000522 instr:0xc90080e7 iType:Jr [doCommitNormalInst [0]] 1356 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 14290 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000ff8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8504 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8506 } + 14310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8506 } +calling cycle + 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8506 } + 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8506 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fd8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h850c } + 14330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fd8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h850c } +calling cycle + 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fd8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h850c } + 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fd8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h850c } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fec, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8510 } + 14350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8510 } +calling cycle + 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8510 } + 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8510 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fe0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8516 } + 14370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fe0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8516 } +calling cycle + 14380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fe0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8516 } + 14380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fe0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8516 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 14650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 14660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc8 +After delta: vaddr = 0x80000fc8 + 14660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 58 <= 00000000200003e4000000001fffff44000000 + 14670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000526 o: 'h0000000080000526 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc8, write: True, capStore: False, potentialCapLoad: False } + 14670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc0 +After delta: vaddr = 0x80000fc0 + 14670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5b <= 00000000200003f4000000001fffff44000000 + 14680 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc8, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h000 } + 14680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc0, write: True, capStore: False, potentialCapLoad: False } + 14680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 14680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:24 PC:0x1ffff00000000000000000000800001ae instr:0x00007139 iType:Alu [doCommitNormalInst [0]] 1468 +calling cycle +[RFile] wr_ 0: r 5d <= 0000000000000005000000001fffff44000000 + 14690 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc0, check_high: 'h00000000080000fc8, check_inclusive: True } }, specBits: 'h000 } + 14690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: True, capStore: False, potentialCapLoad: False } + 14690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 +instret:25 PC:0x1ffff00000000000000000000800001b0 instr:0x0000fc06 iType:St [doCommitNormalInst [0]] 1469 +calling cycle + 14700 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fc8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81b0 } + 14700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000014 o: 'h0000000000000014 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: True, capStore: False, potentialCapLoad: False } + 14700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b0 } +instret:26 PC:0x1ffff00000000000000000000800001b2 instr:0x0000f822 iType:St [doCommitNormalInst [0]] 1470 +instret:27 PC:0x1ffff00000000000000000000800001b4 instr:0x00000080 iType:Alu [doCommitNormalInst [1]] 1470 +calling cycle + 14710 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 14710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b0 } + 14710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b0 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:28 PC:0x1ffff00000000000000000000800001b6 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 1471 +instret:29 PC:0x1ffff00000000000000000000800001ba instr:0x00004551 iType:Alu [doCommitNormalInst [1]] 1471 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fc0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81b2 } + 14720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b2 } +instret:30 PC:0x1ffff00000000000000000000800001bc instr:0xfea43023 iType:St [doCommitNormalInst [0]] 1472 +calling cycle + 14730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b2 } + 14730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b2 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81b6 } + 14740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b6 } +calling cycle + 14750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b6 } + 14750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +calling cycle +calling cycle + 14770 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b6 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000fb8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000019 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffe5e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +[RFile] wr_ 1: r 5f <= 0000000000000006400000001fffff44000000 +calling cycle +[RFile] wr_ 0: r 60 <= 0000000000001900000000001fffff44000000 +[RFile] wr_ 1: r 61 <= 0000000020000071000000001fffff44000000 +instret:31 PC:0x1ffff00000000000000000000800001c0 instr:0x00004565 iType:Alu [doCommitNormalInst [0]] 1522 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h155 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 62 <= 0000000020000073000000001fffff44000000 +[ALU redirect - 0] 'h1ffff0000000000000000000080000022; 'h0; InstTag { way: 'h0, ptr: 'h11, t: 'h22 } +instret:32 PC:0x1ffff00000000000000000000800001c2 instr:0x0000052a iType:Alu [doCommitNormalInst [0]] 1523 +instret:33 PC:0x1ffff00000000000000000000800001c4 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1523 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h11, t: 'h22 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:34 PC:0x1ffff00000000000000000000800001c8 instr:0xe5e080e7 iType:Jr [doCommitNormalInst [0]] 1525 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 15450 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000fb8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81bc } + 15470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81bc } +calling cycle + 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81bc } + 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81bc } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 15840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 63 <= 00000000200003c8000000001fffff44000000 + 15850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000068, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800001cc o: 'h00000000800001cc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 15850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 15850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 66 <= 00000000200003e4000000001fffff44000000 + 15860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 15860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000060, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 15860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 + 15860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:35 PC:0x1ffff0000000000000000000080000022 instr:0x00007159 iType:Alu [doCommitNormalInst [0]] 1586 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000050e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 15870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000006400 o: 'h0000000000006400 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: True, capStore: False, potentialCapLoad: False } + 15870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 +instret:36 PC:0x1ffff0000000000000000000080000024 instr:0x0000f486 iType:St [doCommitNormalInst [0]] 1587 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 15880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8024 } + 15880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } + 15880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } +instret:37 PC:0x1ffff0000000000000000000080000026 instr:0x0000f0a2 iType:St [doCommitNormalInst [0]] 1588 +instret:38 PC:0x1ffff0000000000000000000080000028 instr:0x00001880 iType:Alu [doCommitNormalInst [1]] 1588 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 15890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h802e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } + 15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 15890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:39 PC:0x1ffff000000000000000000008000002a instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1589 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000771 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00002000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6c <= 000000002000040e800000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8026 } + 15900 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 68 <= 0000000000001900000000001fffff44000000 + 15900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001548 +After delta: vaddr = 0x80001548 + 15900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 15900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h028 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6d <= 0000000020000552000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 15910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080001548 o: 'h0000000080001548 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001548 o: 'h0000000080001548 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001548, write: False, capStore: False, potentialCapLoad: False } + 15910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } + 15910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 15910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 15910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15920 : [doFinishMem] DTlbResp { resp: <'h0000000080001548,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001548 o: 'h0000000080001548 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001548, check_high: 'h00000000080001550, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h802a } + 15920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080001548, shiftedBE: tagged DataMemAccess , pcHash: 'h8042 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 15920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } + 15920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 15920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080001548, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } +instret:40 PC:0x1ffff000000000000000000008000002e instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 1592 +calling cycle +[RFile] wr_ 0: r 69 <= 0000000000001901c00000001fffff44000000 +[RFile] wr_ 1: r 71 <= 0000000000000800000000001fffff44000000 + 15930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 15930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 15930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080001548, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } + 15930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 15930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 + 15930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 72 <= 00000000000009dc400000001fffff44000000 +[RFile] wr_ 1: r 6a <= 0000000000001900000000001fffff44000000 + 15940 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6f <= 0000000000001900000000001fffff44000000 + 15940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000006400 o: 'h0000000000006400 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: True, capStore: False, potentialCapLoad: False } + 15940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } + 15940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:41 PC:0x1ffff0000000000000000000080000032 instr:0x0000051d iType:Alu [doCommitNormalInst [0]] 1594 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000004d8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15950 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080001548, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001548, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 15950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 15950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:42 PC:0x1ffff0000000000000000000080000034 instr:0x00009961 iType:Alu [doCommitNormalInst [0]] 1595 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 15960 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f68, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 15960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 +instret:43 PC:0x1ffff0000000000000000000080000036 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1596 +instret:44 PC:0x1ffff000000000000000000008000003a instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1596 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 75 <= 40000000000000000000ffff1fffff44000000 + 15970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: True, potentialCapLoad: True } + 15970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:45 PC:0x1ffff000000000000000000008000003e instr:0x50e50513 iType:Alu [doCommitNormalInst [0]] 1597 +calling cycle +[RFile] wr_ 1: r 77 <= 000000002000041c000000001fffff44000000 + 15980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } + 15980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 15980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 78 <= 0000000020000552000000001fffff44000000 + 15990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001548 o: 'h0000000080001548 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } + 15990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001548 +After delta: vaddr = 0x80001548 +calling cycle + 16000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h001 } + 16000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080001548 o: 'h0000000080001548 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001548 o: 'h0000000080001548 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001548, write: False, capStore: False, potentialCapLoad: False } +calling cycle + 16010 : [doFinishMem] DTlbResp { resp: <'h0000000080001548,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001548 o: 'h0000000080001548 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001548, check_high: 'h00000000080001550, check_inclusive: True } }, specBits: 'h001 } + 16010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080001548, shiftedBE: tagged DataMemAccess , pcHash: 'h807c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080001548, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807c } +calling cycle + 16020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080001548, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807c } + 16020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000004d2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7b <= 000000002000041f800000001fffff44000000 + 16500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 16500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7c <= 0000000020000554000000001fffff44000000 + 16510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } + 16510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } + 16520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h808c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 16520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 16520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h001 } + 16530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8090 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16530 : [doRespLdForward] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 7f <= 40000000000000000000ffff1fffff44000000 + 16530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 16530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8090 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: True } + 16540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8090 } + 16540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 16540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } + 16550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h809c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } + 16550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 16560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h001 } + 16560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 16560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809c } + 16560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 16560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 +calling cycle + 16570 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000000001900000000001fffff44000000 + 16570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: True } +calling cycle + 16580 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809c } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f30, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[RFile] wr_ 0: r 47 <= 0000000000000001000000001fffff44000000 + 16580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } + 16580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } +calling cycle +[RFile] wr_ 0: r 02 <= 000000002000002c800000001fffff44000000 + 16590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } + 16590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +calling cycle +[RFile] wr_ 1: r 45 <= 000000002000002e800000001fffff44000000 +[ALU redirect - 1] 'h1ffff00000000000000000000800000e4; 'h1; InstTag { way: 'h0, ptr: 'h05, t: 'h0a } +calling cycle +[ROB incorrectSpec] 'h1 ; InstTag { way: 'h0, ptr: 'h05, t: 'h0a } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 16740 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001548, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080001548, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } + 16750 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 +calling cycle + 16760 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6e <= 0000000000000000000000001fffff44000000 + 16760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080001548, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807c } + 16760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 16760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080001548, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807c } + 16760 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 16760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080001548, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 16770 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 0000000000000000000000001fffff44000000 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 16780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:46 PC:0x1ffff0000000000000000000080000042 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 1678 +calling cycle +[RFile] wr_ 1: r 70 <= 0000000000001900000000001fffff44000000 + 16790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 17050 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f68, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 17060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17060 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 17060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8036 } + 17070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8090 } + 17070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 17070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8090 } + 17070 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } + 17070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } +calling cycle + 17080 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 17080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } + 17080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000771 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00002000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h028 }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 17440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 17450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 71 <= 0000000000000800000000001fffff44000000 + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } + 17460 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000004d8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 72 <= 00000000000009dc400000001fffff44000000 + 17470 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6f <= 0000000000001900000000001fffff44000000 + 17470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 75 <= 40000000000000000000ffff1fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: True, potentialCapLoad: True } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000004d2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 77 <= 000000002000041c000000001fffff44000000 + 17490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } + 17490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:47 PC:0x1ffff0000000000000000000080000044 instr:0xfd843583 iType:Ld [doCommitNormalInst [0]] 1749 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 70 <= 0000000000001900000000001fffff44000000 + 17500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 17500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 78 <= 0000000020000552000000001fffff44000000 +[ALU redirect - 0] 'h1ffff0000000000000000000080000058; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } + 17510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001548 o: 'h0000000080001548 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } + 17510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001548 +After delta: vaddr = 0x80001548 + 17510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:48 PC:0x1ffff0000000000000000000080000048 instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 1751 +instret:49 PC:0x1ffff000000000000000000008000004a instr:0x00006589 iType:Alu [doCommitNormalInst [1]] 1751 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:50 PC:0x1ffff000000000000000000008000004c instr:0x7715859b iType:Alu [doCommitNormalInst [0]] 1753 +instret:51 PC:0x1ffff0000000000000000000080000050 instr:0x00b57463 iType:Br [doCommitNormalInst [1]] 1753 +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000074 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 +calling cycle +[RFile] wr_ 0: r 75 <= 0000000000000000000000001fffff44000000 + 17610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: True, capStore: False, potentialCapLoad: True } +calling cycle + 17620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } +instret:52 PC:0x1ffff0000000000000000000080000058 instr:0x0040006f iType:J [doCommitNormalInst [0]] 1762 +instret:53 PC:0x1ffff000000000000000000008000005c instr:0xfea0055b iType:Cap [doCommitNormalInst [1]] 1762 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:54 PC:0x1ffff0000000000000000000080000060 instr:0xfea44023 iType:St [doCommitNormalInst [0]] 1763 +instret:55 PC:0x1ffff0000000000000000000080000064 instr:0x0740006f iType:J [doCommitNormalInst [1]] 1763 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8060 } + 17640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 + 17640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8060 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: False, capStore: False, potentialCapLoad: True } + 17650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8060 } + 17650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8060 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 17650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 17660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f70, shiftedBE: tagged DataMemAccess , pcHash: 'h80d8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 17660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 17660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d8 } +calling cycle + 17670 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f30, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 17670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 17670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h80dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + 17670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d8 } + 17670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d8 } + 17670 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 17670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[RFile] wr_ 1: r 7b <= 00000000200003e4000000001fffff44000000 + 17680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 17680 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000000000000000000001fffff44000000 + 17680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17680 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 17680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809c } + 17680 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 17680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 17680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 17690 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 17690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } + 17690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 17690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } + 17690 : [Ld resp] 'h0a; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 17690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17700 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h80de } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17700 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: } } + 17700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 17700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 17700 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } + 17700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80de } +instret:56 PC:0x1ffff00000000000000000000800000d8 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1770 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17710 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 79 <= 0000000020000073000000001fffff44000000 + 17710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80de } + 17710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80de } + 17710 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 17710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17720 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 00000000200003f4000000001fffff44000000 + 17720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 + 17730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:57 PC:0x1ffff00000000000000000000800000dc instr:0x000070a6 iType:Ld [doCommitNormalInst [0]] 1773 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[ALU redirect - 1] 'h1ffff00000000000000000000800001cc; 'h0; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } + 17740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } + 17740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 + 17740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:58 PC:0x1ffff00000000000000000000800000de instr:0x00007406 iType:Ld [doCommitNormalInst [0]] 1774 +instret:59 PC:0x1ffff00000000000000000000800000e0 instr:0x00006165 iType:Alu [doCommitNormalInst [1]] 1774 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:60 PC:0x1ffff00000000000000000000800000e2 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 1776 +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 17820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: False, potentialCapLoad: True } + 17830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 17830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h800, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7e <= 0000000000000000000000001fffff44000000 + 17840 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 17840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: True, capStore: False, potentialCapLoad: False } + 17840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 17850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +instret:61 PC:0x1ffff00000000000000000000800001cc instr:0xfca44823 iType:St [doCommitNormalInst [0]] 1785 +instret:62 PC:0x1ffff00000000000000000000800001d0 instr:0x00004501 iType:Alu [doCommitNormalInst [1]] 1785 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0a <= 0000000000000000800000001fffff44000000 + 17860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h81cc } + 17860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 17860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81cc } +instret:63 PC:0x1ffff00000000000000000000800001d2 instr:0xfca42623 iType:St [doCommitNormalInst [0]] 1786 +instret:64 PC:0x1ffff00000000000000000000800001d6 instr:0x0040006f iType:J [doCommitNormalInst [1]] 1786 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17870 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0b <= 0000000000000000000000001fffff44000000 + 17870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81cc } + 17870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81cc } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 17870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h400, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h169 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 01 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81d2 } + 17880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: True, capStore: False, potentialCapLoad: False } + 17880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 17880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000038 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h002 } + 17890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d2 } + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d2 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:65 PC:0x1ffff00000000000000000000800001da instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 1789 +instret:66 PC:0x1ffff00000000000000000000800001de instr:0x00004509 iType:Alu [doCommitNormalInst [1]] 1789 +calling cycle +[RFile] wr_ 1: r 02 <= 0000000000000000c00000001fffff44000000 +[ALU redirect - 0] 'h1ffff00000000000000000000800001e8; 'h1; InstTag { way: 'h0, ptr: 'h0a, t: 'h14 } + 17900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h002 } + 17900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } +calling cycle +[ROB incorrectSpec] 'h1 ; InstTag { way: 'h0, ptr: 'h0a, t: 'h14 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 17920 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +instret:67 PC:0x1ffff00000000000000000000800001e0 instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 1792 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 18460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hc00, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 01 <= 0000000000000000000000001fffff44000000 + 18470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 18470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +calling cycle + 18480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 18480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +instret:68 PC:0x1ffff00000000000000000000800001e8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 1848 +instret:69 PC:0x1ffff00000000000000000000800001ec instr:0x00004501 iType:Alu [doCommitNormalInst [1]] 1848 +calling cycle +[RFile] wr_ 1: r 02 <= 0000000000000000c00000001fffff44000000 + 18490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 18490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } +instret:70 PC:0x1ffff00000000000000000000800001ee instr:0xfca42423 iType:St [doCommitNormalInst [0]] 1849 +instret:71 PC:0x1ffff00000000000000000000800001f2 instr:0x0040006f iType:J [doCommitNormalInst [1]] 1849 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81ee } + 18500 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 0000000000000000000000001fffff44000000 + 18500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ee } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 18510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ee } + 18510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ee } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 18510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +instret:72 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 1852 +instret:73 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 1852 +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h2; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } +calling cycle +[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:74 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 1855 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 19010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 19020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 19030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 19030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4e <= 0000000020000484000000001fffff44000000 + 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 19040 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } + 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:75 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 1904 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 08 <= 000000002000054d000000001fffff44000000 + 19050 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 0000000000000000000000001fffff44000000 + 19050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 19060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 19070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 19070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:76 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 1907 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 54 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 4d <= 0000000000000000000000001fffff44000000 + 19080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 19080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 19080 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } + 19080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001534 +After delta: vaddr = 0x80001534 + 19080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 42 <= 000000002000054d000000001fffff44000000 + 19090 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 0000000000000000000000001fffff44000000 + 19090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080001534 o: 'h0000000080001534 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001534 o: 'h0000000080001534 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001534, write: False, capStore: False, potentialCapLoad: False } + 19090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 19090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:77 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 1909 +instret:78 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 1909 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 53 <= 0000000020000f30000000001fffff44000000 + 19100 : [doFinishMem] DTlbResp { resp: <'h0000000080001534,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001534 o: 'h0000000080001534 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001534, check_high: 'h00000000080001538, check_inclusive: True } }, specBits: 'h000 } + 19100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080001534, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 19100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 19100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080001534, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:79 PC:0x1ffff0000000000000000000080000214 instr:0x32458693 iType:Alu [doCommitNormalInst [0]] 1910 +instret:80 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 1910 +calling cycle +[RFile] wr_ 1: r 56 <= 0000000000000000000000001fffff44000000 + 19110 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 19110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 19110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080001534, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 19110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 19110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } +calling cycle +[RFile] wr_ 0: r 50 <= 0000000000000000000000001fffff44000000 + 19120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 19120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 19120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 19120 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } + 19120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } +calling cycle + 19130 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080001534, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001534, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[RFile] wr_ 0: r 4b <= 0000000020000f30000000001fffff44000000 + 19130 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5a <= 0000000000000000c00000001fffff44000000 + 19130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 19130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 19130 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 19130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[RFile] wr_ 0: r 4c <= 0000000020000f30000000001fffff44000000 + 19140 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000000000000001fffff44000000 +calling cycle +calling cycle +calling cycle +[RFile] wr_ 1: r 5c <= 0000000000000000000000001fffff44000000 +calling cycle +[RFile] wr_ 1: r 55 <= 0000000020000f30000000001fffff44000000 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 19600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 19610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 19620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 19620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 19630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 19630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 19630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 19630 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } + 19630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19640 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 19640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19640 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5e <= 0000000000000000000000001fffff44000000 + 19640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 19640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 19650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 19650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 19650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 19650 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } + 19650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 19650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 19660 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 61 <= 0000000000000005000000001fffff44000000 + 19660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 19660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 19660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 19660 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } + 19660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5d <= 0000000000000000000000001fffff44000000 + 19670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 19670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19670 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 0000000000000000000000001fffff44000000 + 19670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cc8 +After delta: vaddr = 0x80003cc8 + 19670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'he00, localHist: 'h2aa, globalTaken: True, localTaken: True, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5f <= 0000000020000f30000000001fffff44000000 + 19680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cc8 o: 'h0000000080003cc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cc8, write: True, capStore: False, potentialCapLoad: False } + 19680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 19680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 19680 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } + 19680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19690 : [doFinishMem] DTlbResp { resp: <'h0000000080003cc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cc8 o: 'h0000000080003cc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cc8, check_high: 'h00000000080003cd0, check_inclusive: True } }, specBits: 'h000 } + 19690 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 60 <= 0000000000000000000000001fffff44000000 + 19690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 19690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 64 <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 6b <= 0000000000000000000000001fffff44000000 + 19700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 19700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001534 +After delta: vaddr = 0x80001534 +calling cycle +[RFile] wr_ 0: r 65 <= 000000002000054d000000001fffff44000000 + 19710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 19710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080001534 o: 'h0000000080001534 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001534 o: 'h0000000080001534 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001534, write: False, capStore: False, potentialCapLoad: False } + 19710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } +calling cycle +[RFile] wr_ 1: r 68 <= 0000000000000000000000001fffff44000000 + 19720 : [doFinishMem] DTlbResp { resp: <'h0000000080001534,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001534 o: 'h0000000080001534 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001534, check_high: 'h00000000080001538, check_inclusive: True } }, specBits: 'h000 } + 19720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080001534, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 19720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 19720 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 19720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080001534, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +calling cycle +[RFile] wr_ 0: r 69 <= 0000000020000f30000000001fffff44000000 + 19730 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000000000000001fffff44000000 + 19730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080001534, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 19730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +calling cycle +[RFile] wr_ 0: r 6a <= 0000000020000f30000000001fffff44000000 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 19860 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001534, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 19870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19870 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 19870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080001534, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 19870 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 19870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 +calling cycle + 19880 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 0000000000000006400000001fffff44000000 + 19880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080001534, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 19880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 19880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080001534, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 19880 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 19880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080001534, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 19890 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000000000006400000001fffff44000000 + 19890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cd0 +After delta: vaddr = 0x80003cd0 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 19900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000019 o: 'h0000000000000019 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cd0 o: 'h0000000080003cd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cd0, write: True, capStore: False, potentialCapLoad: False } +instret:81 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 1990 +calling cycle + 19910 : [doFinishMem] DTlbResp { resp: <'h0000000080003cd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cd0 o: 'h0000000080003cd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cd0, check_high: 'h00000000080003cd4, check_inclusive: True } }, specBits: 'h000 } +instret:82 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 1991 +instret:83 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 1991 +calling cycle +instret:84 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 1992 +instret:85 PC:0x1ffff0000000000000000000080000228 instr:0xa9c58593 iType:Alu [doCommitNormalInst [1]] 1992 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:86 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 1993 +instret:87 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 1993 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:88 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 1994 +instret:89 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 1994 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003cd0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 19950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003cd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:90 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 1995 +instret:91 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 1995 +calling cycle + 19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003cd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:92 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 1996 +instret:93 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 1996 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:94 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 1997 +instret:95 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 1997 +calling cycle + 19980 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003cd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080003cd0, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:96 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 1998 +instret:97 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 1998 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080001534, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:98 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 1999 +instret:99 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [1]] 1999 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:100 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [0]] 2000 +instret:101 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [1]] 2000 +calling cycle +instret:102 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 2001 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +[RFile] wr_ 2: r 67 <= 0000000000000000000000001fffff44000000 +calling cycle + 20120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:103 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 2012 +instret:104 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 2012 +calling cycle + 20130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cc0 +After delta: vaddr = 0x80003cc0 +instret:105 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 2013 +instret:106 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 2013 +calling cycle + 20140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cc0, write: True, capStore: False, potentialCapLoad: False } +instret:107 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 2014 +instret:108 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 2014 +calling cycle + 20150 : [doFinishMem] DTlbResp { resp: <'h0000000080003cc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cc0, check_high: 'h00000000080003cc8, check_inclusive: True } }, specBits: 'h000 } +calling cycle +instret:109 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2016 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +calling cycle +instret:110 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 2018 +instret:111 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 2018 +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa3e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 20260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h827a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + 20270 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } + 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:112 PC:0x1ffff0000000000000000000080000276 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2027 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000098 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 73 <= 00000000200010a0800000001fffff44000000 + 20280 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6f <= 0000000000000000000000001fffff44000000 + 20280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 +calling cycle +[RFile] wr_ 1: r 74 <= 0000000020000f30000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } +calling cycle +[RFile] wr_ 1: r 77 <= 00000000200000a4000000001fffff44000000 + 20300 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 20300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h828c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } +instret:113 PC:0x1ffff000000000000000000008000027a instr:0xfc842503 iType:Ld [doCommitNormalInst [0]] 2030 +calling cycle +[RFile] wr_ 0: r 71 <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 75 <= 00000000200000a6000000001fffff44000000 +[ALU redirect - 1] 'h1ffff0000000000000000000080000328; 'h0; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } + 20310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + 20310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + 20310 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 20310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +[RFile] wr_ 0: r 70 <= 0000000020000f30000000001fffff44000000 + 20330 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000000000000001fffff44000000 +instret:114 PC:0x1ffff000000000000000000008000027e instr:0x00551593 iType:Alu [doCommitNormalInst [0]] 2033 +instret:115 PC:0x1ffff0000000000000000000080000282 instr:0x00004517 iType:Auipc [doCommitNormalInst [1]] 2033 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } +instret:116 PC:0x1ffff0000000000000000000080000286 instr:0xa3e50513 iType:Alu [doCommitNormalInst [0]] 2034 +instret:117 PC:0x1ffff000000000000000000008000028a instr:0x0000952e iType:Alu [doCommitNormalInst [1]] 2034 +calling cycle +instret:118 PC:0x1ffff000000000000000000008000028c instr:0xfd04258f iType:Ld [doCommitNormalInst [0]] 2035 +instret:119 PC:0x1ffff0000000000000000000080000290 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2035 +calling cycle +instret:120 PC:0x1ffff0000000000000000000080000294 instr:0x098080e7 iType:Jr [doCommitNormalInst [0]] 2036 +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 20400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 62 <= 00000000200003cc000000001fffff44000000 + 20410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000298 o: 'h0000000080000298 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 20410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 20410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7c <= 00000000200003e4000000001fffff44000000 + 20420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 20420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 20420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 20420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:121 PC:0x1ffff0000000000000000000080000328 instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 2042 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 20430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 20430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 20430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 20430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:122 PC:0x1ffff000000000000000000008000032a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2043 +calling cycle + 20440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 20440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 20440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +instret:123 PC:0x1ffff000000000000000000008000032c instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 2044 +instret:124 PC:0x1ffff000000000000000000008000032e instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 2044 +calling cycle + 20450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 20450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +instret:125 PC:0x1ffff0000000000000000000080000330 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 2045 +calling cycle + 20460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 20460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8338 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } +instret:126 PC:0x1ffff0000000000000000000080000334 instr:0xfcb44823 iType:St [doCommitNormalInst [0]] 2046 +calling cycle + 20470 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000020000f30000000001fffff44000000 + 20470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20480 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080003cd0, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cc0 +After delta: vaddr = 0x80003cc0 +calling cycle + 20490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cc0, write: False, capStore: False, potentialCapLoad: False } + 20490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20490 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 20490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003cd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:127 PC:0x1ffff0000000000000000000080000338 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2049 +calling cycle + 20500 : [doFinishMem] DTlbResp { resp: <'h0000000080003cc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cc0, check_high: 'h00000000080003cc8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003cc8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 20500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080003cc0, shiftedBE: tagged DataMemAccess , pcHash: 'h833c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 20500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003cc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +calling cycle + 20510 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 05 <= 0000000000000000000000001fffff44000000 + 20510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003cc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 20510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003cc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080003cc0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003cc0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 20520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003cc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +calling cycle + 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003cc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003cc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:128 PC:0x1ffff000000000000000000008000033c instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2053 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h832a } + 20540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +calling cycle + 20550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } + 20550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h832c } + 20560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } +calling cycle + 20570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } + 20570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8330 } + 20580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } +calling cycle + 20590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 20590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8334 } + 20600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } +calling cycle + 20610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } + 20610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 20920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 20930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 20930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 20940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 20940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 20950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8342 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 20950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8342 } +instret:129 PC:0x1ffff000000000000000000008000033e instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2095 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h833e } + 20960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8342 } + 20960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8342 } + 20960 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } + 20960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 20960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 20970 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7e <= 0000000020000f30000000001fffff44000000 + 20970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 20970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } + 20970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 20980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h834c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cc8 +After delta: vaddr = 0x80003cc8 + 20980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 20980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cc8 o: 'h0000000080003cc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cc8, write: False, capStore: False, potentialCapLoad: False } + 20990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } + 20990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } + 20990 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 20990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 20990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:130 PC:0x1ffff0000000000000000000080000342 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2099 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf00, localHist: 'h2aa, globalTaken: True, localTaken: True, pcIndex: 'h1b4 }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0b <= 0000000000000000000000001fffff44000000 + 21000 : [doFinishMem] DTlbResp { resp: <'h0000000080003cc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cc8 o: 'h0000000080003cc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cc8, check_high: 'h00000000080003cd0, check_inclusive: True } }, specBits: 'h000 } + 21000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080003cc8, shiftedBE: tagged DataMemAccess , pcHash: 'h8346 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21000 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 0000000020000f30000000001fffff44000000 + 21000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } + 21000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 21000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080003cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } +calling cycle + 21010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 21010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 21010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080003cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 21010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080003cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 21010 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } + 21010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cd0 +After delta: vaddr = 0x80003cd0 + 21010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 21020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8360 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 21020 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000000c00000001fffff44000000 + 21020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cd0 o: 'h0000000080003cd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cd0, write: False, capStore: False, potentialCapLoad: False } + 21020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 21020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080003cc8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21030 : [doFinishMem] DTlbResp { resp: <'h0000000080003cd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cd0 o: 'h0000000080003cd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cd0, check_high: 'h00000000080003cd4, check_inclusive: True } }, specBits: 'h000 } + 21030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080003cd0, shiftedBE: tagged DataMemAccess , pcHash: 'h8350 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21030 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 0000000000000000000000001fffff44000000 + 21030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 21030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 21030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080003cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } +calling cycle + 21040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 21040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8364 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } + 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080003cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } + 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080003cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } + 21040 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } + 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8364 } +instret:131 PC:0x1ffff0000000000000000000080000346 instr:0x00006508 iType:Ld [doCommitNormalInst [0]] 2104 +calling cycle + 21050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } + 21050 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 43 <= 0000000000000006400000001fffff44000000 + 21050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8364 } + 21050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8364 } + 21050 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } } + 21050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21060 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0e <= 0000000000000000000000001fffff44000000 + 21060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffbc, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f4c +After delta: vaddr = 0x80000f4c +instret:132 PC:0x1ffff0000000000000000000080000348 instr:0xfca43023 iType:St [doCommitNormalInst [0]] 2106 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8348 } + 21070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffbc, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000019 o: 'h0000000000000019 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } + 21070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080003cd0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 21080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } + 21080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:133 PC:0x1ffff000000000000000000008000034c instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2108 +calling cycle +[ALU redirect - 0] 'h1ffff000000000000000000008000036c; 'h1; InstTag { way: 'h0, ptr: 'h0f, t: 'h1e } +instret:134 PC:0x1ffff0000000000000000000080000350 instr:0x00004908 iType:Ld [doCommitNormalInst [0]] 2109 +instret:135 PC:0x1ffff0000000000000000000080000352 instr:0xfaa42e23 iType:St [doCommitNormalInst [1]] 2109 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8352 } + 21100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } +[ROB incorrectSpec] 'h1 ; InstTag { way: 'h0, ptr: 'h0f, t: 'h1e } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 21110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } + 21110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:136 PC:0x1ffff0000000000000000000080000356 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 2111 +instret:137 PC:0x1ffff0000000000000000000080000358 instr:0xfaa42c23 iType:St [doCommitNormalInst [1]] 2111 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8358 } + 21120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } +instret:138 PC:0x1ffff000000000000000000008000035c instr:0x0040006f iType:J [doCommitNormalInst [0]] 2112 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } + 21130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:139 PC:0x1ffff0000000000000000000080000360 instr:0xfb842503 iType:Ld [doCommitNormalInst [0]] 2113 +calling cycle +instret:140 PC:0x1ffff0000000000000000000080000364 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2114 +instret:141 PC:0x1ffff0000000000000000000080000368 instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2114 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0e, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000018e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:142 PC:0x1ffff000000000000000000008000036c instr:0x18e0006f iType:J [doCommitNormalInst [0]] 2157 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 22080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 22090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 22090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 +calling cycle + 22100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 22100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h84fa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + 22100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fa } +calling cycle +[RFile] wr_ 1: r 42 <= 00000000200003e4000000001fffff44000000 + 22110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 22110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h84fc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fa } + 22110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fa } + 22110 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } } + 22110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fc } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22120 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0d <= 00000000200000a6000000001fffff44000000 + 22120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fc } + 22120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fc } + 22120 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 22120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22130 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 00000000200003f4000000001fffff44000000 + 22130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:143 PC:0x1ffff00000000000000000000800004fa instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2214 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +instret:144 PC:0x1ffff00000000000000000000800004fc instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2215 +instret:145 PC:0x1ffff00000000000000000000800004fe instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2215 +calling cycle + 22160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h004 } + 22160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:146 PC:0x1ffff0000000000000000000080000500 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2216 +instret:147 PC:0x1ffff0000000000000000000080000298 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2216 +calling cycle + 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 22170 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } + 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:148 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [0]] 2217 +calling cycle + 22180 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 54 <= 0000000000000000000000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h780, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 22200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:149 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [0]] 2220 +calling cycle +[RFile] wr_ 1: r 50 <= 0000000000000000400000001fffff44000000 + 22210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 22210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +calling cycle +[RFile] wr_ 0: r 51 <= 0000000000000000c00000001fffff44000000 + 22220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 22220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +instret:150 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 2222 +calling cycle + 22230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 22230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } +instret:151 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [0]] 2223 +instret:152 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [1]] 2223 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 22240 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000000400000001fffff44000000 + 22240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 22250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +instret:153 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 2226 +instret:154 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 2226 +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h0; InstTag { way: 'h0, ptr: 'h16, t: 'h2c } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h16, t: 'h2c } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:155 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2229 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 22340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 22350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 22360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 22360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5e <= 0000000020000484000000001fffff44000000 + 22370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 22370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 22370 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } + 22370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:156 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2237 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 55 <= 000000002000054d000000001fffff44000000 + 22380 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5c <= 0000000000000000400000001fffff44000000 + 22380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 22400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 22400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:157 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2240 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 08 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 56 <= 0000000000000001000000001fffff44000000 + 22410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 22410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 22410 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } + 22410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001538 +After delta: vaddr = 0x80001538 + 22410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 57 <= 000000002000054e000000001fffff44000000 + 22420 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5f <= 0000000000000000000000001fffff44000000 + 22420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001538, write: False, capStore: False, potentialCapLoad: False } + 22420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 22420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:158 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 2242 +instret:159 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2242 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 65 <= 0000000020000f30000000001fffff44000000 + 22430 : [doFinishMem] DTlbResp { resp: <'h0000000080001538,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001538, check_high: 'h0000000008000153c, check_inclusive: True } }, specBits: 'h000 } + 22430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080001538, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 22430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 22430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:160 PC:0x1ffff0000000000000000000080000214 instr:0x32458693 iType:Alu [doCommitNormalInst [0]] 2243 +instret:161 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 2243 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5b <= 0000000000000008000000001fffff44000000 + 22440 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 22440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 22440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 22440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 22440 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } + 22440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 22440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5d <= 0000000000000000000000001fffff44000000 + 22450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 22450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22450 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5a <= 0000000000000019000000001fffff44000000 + 22450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 22450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 22450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 22450 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } + 22450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 61 <= 0000000020000f30000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080001538, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 22460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22460 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 0000000000000000c00000001fffff44000000 + 22460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 22460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 22460 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } + 22460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cf0 +After delta: vaddr = 0x80003cf0 + 22460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 60 <= 0000000020000f38000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22470 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 69 <= 0000000000000000000000001fffff44000000 + 22470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000064 o: 'h0000000000000064 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cf0 o: 'h0000000080003cf0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cf0, write: True, capStore: False, potentialCapLoad: False } + 22470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 22470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 22470 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } + 22470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 22470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:162 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2247 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 22480 : [doFinishMem] DTlbResp { resp: <'h0000000080003cf0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cf0 o: 'h0000000080003cf0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cf0, check_high: 'h00000000080003cf4, check_inclusive: True } }, specBits: 'h000 } + 22480 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 41 <= 0000000000000000400000001fffff44000000 + 22480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 22480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:163 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 2248 +instret:164 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 2248 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22490 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 22490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 22490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:165 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 2249 +instret:166 PC:0x1ffff0000000000000000000080000228 instr:0xa9c58593 iType:Alu [doCommitNormalInst [1]] 2249 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6c <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 22500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 22500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 22500 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } + 22500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 22500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:167 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 2250 +instret:168 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2250 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 67 <= 0000000020000f30000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22510 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6f <= 0000000000000005000000001fffff44000000 + 22510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 22510 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:169 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2251 +instret:170 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 2251 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6e <= 0000000000000008000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003cf0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 22520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22520 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000000000000000400000001fffff44000000 + 22520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ce8 +After delta: vaddr = 0x80003ce8 + 22520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:171 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2252 +instret:172 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 2252 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbc0, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6d <= 0000000020000f38000000001fffff44000000 + 22530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ce8 o: 'h0000000080003ce8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ce8, write: True, capStore: False, potentialCapLoad: False } + 22530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 22530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 22530 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } + 22530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003cf0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:173 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 2253 +instret:174 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 2253 +calling cycle + 22540 : [doFinishMem] DTlbResp { resp: <'h0000000080003ce8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ce8 o: 'h0000000080003ce8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ce8, check_high: 'h00000000080003cf0, check_inclusive: True } }, specBits: 'h000 } + 22540 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7b <= 0000000000000000000000001fffff44000000 + 22540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003cf0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 22540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003cf0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 22540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:175 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2254 +instret:176 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2254 +calling cycle +[RFile] wr_ 0: r 74 <= 0000000000000001000000001fffff44000000 +[RFile] wr_ 1: r 7a <= 0000000000000008000000001fffff44000000 + 22550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 22550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001538 +After delta: vaddr = 0x80001538 +instret:177 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2255 +instret:178 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 2255 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 71 <= 000000002000054e000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003ce8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 22560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001538, write: False, capStore: False, potentialCapLoad: False } + 22560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } +calling cycle +[RFile] wr_ 1: r 66 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22570 : [doFinishMem] DTlbResp { resp: <'h0000000080001538,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001538, check_high: 'h0000000008000153c, check_inclusive: True } }, specBits: 'h000 } + 22570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080001538, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 22570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 22570 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } + 22570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:179 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2257 +calling cycle +[RFile] wr_ 0: r 63 <= 0000000020000f30000000001fffff44000000 + 22580 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000000000000000000001fffff44000000 + 22580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 22580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 22580 : [Ld resp] 'h14; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } + 22580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003ce8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +instret:180 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 2258 +instret:181 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 2258 +calling cycle +[RFile] wr_ 0: r 7d <= 0000000020000f38000000001fffff44000000 + 22590 : [doRespLdMem] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 79 <= 0000000000000019000000001fffff44000000 + 22590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003ce8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 22590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003ce8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:182 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 2259 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080001538, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[ALU redirect - 1] 'h1ffff0000000000000000000080000276; 'h0; InstTag { way: 'h1, ptr: 'h08, t: 'h11 } + 22610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:183 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 2261 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h08, t: 'h11 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa3e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 22700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h827a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + 22710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + 22710 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } + 22710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000098 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 44 <= 00000000200010a0800000001fffff44000000 + 22720 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 05 <= 0000000000000000400000001fffff44000000 + 22720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 40 <= 0000000020000f30000000001fffff44000000 + 22730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 43 <= 00000000200000a4000000001fffff44000000 + 22740 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 22740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h828c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7e <= 0000000000000008000000001fffff44000000 +[RFile] wr_ 1: r 01 <= 00000000200000a6000000001fffff44000000 + 22750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + 22750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + 22750 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 22750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0a <= 0000000020000f38000000001fffff44000000 + 22760 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 0000000000000000000000001fffff44000000 + 22760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 22760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 45 <= 00000000200003cc000000001fffff44000000 + 22770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000298 o: 'h0000000080000298 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 22770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 22770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 02 <= 00000000200003e4000000001fffff44000000 + 22780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 22780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 22780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 22780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 22790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 22790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 22790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 22800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 22800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 22800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 2: r 77 <= 0000000000000000000000001fffff44000000 + 22810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 22810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 22810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 22820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8338 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 22820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:184 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 2282 +instret:185 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 2282 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 22830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8342 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22830 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7c <= 0000000020000f38000000001fffff44000000 + 22830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ce0 +After delta: vaddr = 0x80003ce0 + 22830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:186 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 2283 +instret:187 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 2283 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 22840 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000020000f38000000001fffff44000000 + 22840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ce0, write: True, capStore: False, potentialCapLoad: False } + 22840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ce0 +After delta: vaddr = 0x80003ce0 + 22840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:188 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 2284 +instret:189 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 2284 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22850 : [doFinishMem] DTlbResp { resp: <'h0000000080003ce0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ce0, check_high: 'h00000000080003ce8, check_inclusive: True } }, specBits: 'h000 } + 22850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ce0, write: False, capStore: False, potentialCapLoad: False } + 22850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ce8 +After delta: vaddr = 0x80003ce8 + 22850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22860 : [doFinishMem] DTlbResp { resp: <'h0000000080003ce0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ce0, check_high: 'h00000000080003ce8, check_inclusive: True } }, specBits: 'h000 } + 22860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080003ce0, shiftedBE: tagged DataMemAccess , pcHash: 'h833c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ce8 o: 'h0000000080003ce8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ce8, write: False, capStore: False, potentialCapLoad: False } + 22860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 22860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:190 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2286 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22870 : [doFinishMem] DTlbResp { resp: <'h0000000080003ce8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ce8 o: 'h0000000080003ce8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ce8, check_high: 'h00000000080003cf0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003ce0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 22870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080003ce8, shiftedBE: tagged DataMemAccess , pcHash: 'h8346 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22870 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000000000000001fffff44000000 + 22870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 22870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 22870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080003ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hde0, localHist: 'h155, globalTaken: True, localTaken: False, pcIndex: 'h1b4 }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0e <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 22880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h834c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } + 22880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080003ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 22880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080003ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 22880 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } + 22880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 22880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003ce0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +instret:191 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 2288 +instret:192 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 2288 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0e, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000018e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 22890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 22890 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 0000000000000000c00000001fffff44000000 + 22890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 22890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003ce0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 22890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003ce0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 22890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:193 PC:0x1ffff0000000000000000000080000276 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2289 +instret:194 PC:0x1ffff000000000000000000008000027a instr:0xfc842503 iType:Ld [doCommitNormalInst [1]] 2289 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 22900 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 54 <= 0000000020000f38000000001fffff44000000 + 22900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 22900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 22900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:195 PC:0x1ffff000000000000000000008000027e instr:0x00551593 iType:Alu [doCommitNormalInst [0]] 2290 +instret:196 PC:0x1ffff0000000000000000000080000282 instr:0x00004517 iType:Auipc [doCommitNormalInst [1]] 2290 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 22910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 22910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8360 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } + 22910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cf0 +After delta: vaddr = 0x80003cf0 + 22910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:197 PC:0x1ffff0000000000000000000080000286 instr:0xa3e50513 iType:Alu [doCommitNormalInst [0]] 2291 +instret:198 PC:0x1ffff000000000000000000008000028a instr:0x0000952e iType:Alu [doCommitNormalInst [1]] 2291 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } + 22920 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000000000000001fffff44000000 + 22920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cf0 o: 'h0000000080003cf0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cf0, write: False, capStore: False, potentialCapLoad: False } + 22920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 22920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:199 PC:0x1ffff000000000000000000008000028c instr:0xfd04258f iType:Ld [doCommitNormalInst [0]] 2292 +instret:200 PC:0x1ffff0000000000000000000080000290 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2292 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 57 <= 00000000200003e4000000001fffff44000000 + 22930 : [doFinishMem] DTlbResp { resp: <'h0000000080003cf0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cf0 o: 'h0000000080003cf0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cf0, check_high: 'h00000000080003cf4, check_inclusive: True } }, specBits: 'h000 } + 22930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080003cf0, shiftedBE: tagged DataMemAccess , pcHash: 'h8350 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 22930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 22930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080003cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } +instret:201 PC:0x1ffff0000000000000000000080000294 instr:0x098080e7 iType:Jr [doCommitNormalInst [0]] 2293 +instret:202 PC:0x1ffff0000000000000000000080000328 instr:0x0000711d iType:Alu [doCommitNormalInst [1]] 2293 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 22940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8364 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 22940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080003cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } + 22940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080003cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } + 22940 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } + 22940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 +instret:203 PC:0x1ffff000000000000000000008000032a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2294 +instret:204 PC:0x1ffff000000000000000000008000032c instr:0x0000e8a2 iType:St [doCommitNormalInst [1]] 2294 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080003ce0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h832a } + 22950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h84fa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22950 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 0000000000000019000000001fffff44000000 + 22950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + 22950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +instret:205 PC:0x1ffff000000000000000000008000032e instr:0x00001080 iType:Alu [doCommitNormalInst [0]] 2295 +instret:206 PC:0x1ffff0000000000000000000080000330 instr:0xfea43423 iType:St [doCommitNormalInst [1]] 2295 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h6f0, localHist: 'h2aa, globalTaken: True, localTaken: True, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h002 } + 22960 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 0000000000000000000000001fffff44000000 + 22960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } + 22960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffbc, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f4c +After delta: vaddr = 0x80000f4c +instret:207 PC:0x1ffff0000000000000000000080000334 instr:0xfcb44823 iType:St [doCommitNormalInst [0]] 2296 +instret:208 PC:0x1ffff0000000000000000000080000338 instr:0xfe843503 iType:Ld [doCommitNormalInst [1]] 2296 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h832c } + 22970 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h84fc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22970 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 68 <= 00000000200000a6000000001fffff44000000 + 22970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffbc, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000064 o: 'h0000000000000064 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } + 22970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } +instret:209 PC:0x1ffff000000000000000000008000033c instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2297 +instret:210 PC:0x1ffff000000000000000000008000033e instr:0xfca43423 iType:St [doCommitNormalInst [1]] 2297 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080003ce8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 22980 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 56 <= 00000000200003f4000000001fffff44000000 + 22980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } + 22980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:211 PC:0x1ffff0000000000000000000080000342 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2298 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8330 } + 22990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 22990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } +instret:212 PC:0x1ffff0000000000000000000080000346 instr:0x00006508 iType:Ld [doCommitNormalInst [0]] 2299 +instret:213 PC:0x1ffff0000000000000000000080000348 instr:0xfca43023 iType:St [doCommitNormalInst [1]] 2299 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 23000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 23000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 23000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 23000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 41 <= 0000000020000484000000001fffff44000000 +[RFile] wr_ 1: r 5a <= 0000000000000000c00000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080003cf0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8334 } + 23010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 23010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h028 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 23010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h028, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:214 PC:0x1ffff000000000000000000008000034c instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2301 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h028, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h028, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 23020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h028 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 23020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 23020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 23020 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } + 23020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h028 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 23020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } +instret:215 PC:0x1ffff0000000000000000000080000350 instr:0x00004908 iType:Ld [doCommitNormalInst [0]] 2302 +instret:216 PC:0x1ffff0000000000000000000080000352 instr:0xfaa42e23 iType:St [doCommitNormalInst [1]] 2302 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h028, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h028, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 67 <= 000000002000054d000000001fffff44000000 + 23030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h020 } + 23030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23030 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 0000000000000000400000001fffff44000000 + 23030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h020 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 23030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 23030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 23030 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 23030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } +instret:217 PC:0x1ffff0000000000000000000080000356 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 2303 +instret:218 PC:0x1ffff0000000000000000000080000358 instr:0xfaa42c23 iType:St [doCommitNormalInst [1]] 2303 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h020 } + 23040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23040 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000000400000001fffff44000000 + 23040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 23040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 23040 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } + 23040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:219 PC:0x1ffff000000000000000000008000035c instr:0x0040006f iType:J [doCommitNormalInst [0]] 2304 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 55 <= 0000000020001089000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23050 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6c <= 0000000000000000400000001fffff44000000 + 23050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 23050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 23050 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 23050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 23050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } +instret:220 PC:0x1ffff0000000000000000000080000360 instr:0xfb842503 iType:Ld [doCommitNormalInst [0]] 2305 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5d <= 0000000000000000800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23060 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000000000000001fffff44000000 + 23060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 23060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } + 23060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 23060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h020 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 23060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:221 PC:0x1ffff0000000000000000000080000364 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2306 +instret:222 PC:0x1ffff0000000000000000000080000368 instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2306 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h833e } + 23070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h020 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 23070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h020 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 23070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } +instret:223 PC:0x1ffff000000000000000000008000036c instr:0x18e0006f iType:J [doCommitNormalInst [0]] 2307 +instret:224 PC:0x1ffff00000000000000000000800004fa instr:0x000060e6 iType:Ld [doCommitNormalInst [1]] 2307 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 71 <= 0000000020000f30000000001fffff44000000 +[RFile] wr_ 1: r 5b <= 0000000000000001000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23080 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 23080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 23080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } + 23080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 23080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001538 +After delta: vaddr = 0x80001538 + 23080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } +instret:225 PC:0x1ffff00000000000000000000800004fc instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2308 +instret:226 PC:0x1ffff00000000000000000000800004fe instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2308 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6a <= 000000002000054e000000001fffff44000000 +[RFile] wr_ 1: r 6e <= 0000000000000000000000001fffff44000000 + 23090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8348 } + 23090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001538, write: False, capStore: False, potentialCapLoad: False } + 23090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 23090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 23090 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } + 23090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 23090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } +instret:227 PC:0x1ffff0000000000000000000080000500 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2309 +instret:228 PC:0x1ffff0000000000000000000080000298 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2309 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 79 <= 0000000000000008000000001fffff44000000 +[RFile] wr_ 1: r 6f <= 0000000020000f30000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 23100 : [doFinishMem] DTlbResp { resp: <'h0000000080001538,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001538, check_high: 'h0000000008000153c, check_inclusive: True } }, specBits: 'h000 } + 23100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080001538, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23100 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000000000000000c00000001fffff44000000 + 23100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 23100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 23100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 23100 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } + 23100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:229 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [0]] 2310 +instret:230 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [1]] 2310 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7b <= 0000000020000f38000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 23110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23110 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000000000000000000001fffff44000000 + 23110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 23110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 23110 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } + 23110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 23110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } +instret:231 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 2311 +instret:232 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [1]] 2311 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23120 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 0000000000000019000000001fffff44000000 + 23120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 23120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } + 23120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 23120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 23120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:233 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [0]] 2312 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080001538, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23130 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8352 } + 23130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23130 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000000000000800000001fffff44000000 + 23130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 23130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cf0 +After delta: vaddr = 0x80003cf0 + 23130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 78 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 23140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000064 o: 'h0000000000000064 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cf0 o: 'h0000000080003cf0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cf0, write: True, capStore: False, potentialCapLoad: False } + 23140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 23140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 23140 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } + 23140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 23140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 77 <= 0000000020000f30000000001fffff44000000 + 23150 : [doFinishMem] DTlbResp { resp: <'h0000000080003cf0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cf0 o: 'h0000000080003cf0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cf0, check_high: 'h00000000080003cf4, check_inclusive: True } }, specBits: 'h000 } + 23150 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 05 <= 0000000000000005000000001fffff44000000 + 23150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 23150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } + 23150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 23150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 72 <= 0000000000000010000000001fffff44000000 + 23160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8358 } + 23160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23160 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000000000000800000001fffff44000000 + 23160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d08 +After delta: vaddr = 0x80003d08 + 23160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hb78, localHist: 'h3aa, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 70 <= 0000000020000f40000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d08 o: 'h0000000080003d08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d08, write: True, capStore: False, potentialCapLoad: False } + 23170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 23170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 23170 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } + 23170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } +calling cycle +calling cycle + 23190 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 23190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } + 23190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 23190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 23200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +calling cycle + 23210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 23210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 23210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h5bc, localHist: 'h3aa, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 23260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +calling cycle + 23270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[RFile] wr_ 1: r 5a <= 0000000000000000c00000001fffff44000000 + 23280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 23280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 23290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 23290 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 23290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23300 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000000800000001fffff44000000 + 23300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +instret:234 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 2332 +instret:235 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 2332 +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000204; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } + 23330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 23330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 23350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 23350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 23350 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 23350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:236 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2335 +calling cycle + 23360 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 23410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 23420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 41 <= 0000000020000484000000001fffff44000000 + 23430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 23430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 23430 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } + 23430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:237 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2343 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 67 <= 000000002000054d000000001fffff44000000 + 23440 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6c <= 0000000000000000800000001fffff44000000 + 23440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 23460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 23460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:238 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2346 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 55 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 5b <= 0000000000000002000000001fffff44000000 + 23470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 23470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 23470 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 23470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x8000153c +After delta: vaddr = 0x8000153c + 23470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6a <= 000000002000054f000000001fffff44000000 + 23480 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000000000000001fffff44000000 + 23480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h000000008000153c, write: False, capStore: False, potentialCapLoad: False } + 23480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 23480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:239 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 2348 +instret:240 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2348 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 71 <= 0000000020000f30000000001fffff44000000 + 23490 : [doFinishMem] DTlbResp { resp: <'h000000008000153c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h000000008000153c, check_high: 'h00000000080001540, check_inclusive: True } }, specBits: 'h000 } + 23490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h000000008000153c, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 23490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 23490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:241 PC:0x1ffff0000000000000000000080000214 instr:0x32458693 iType:Alu [doCommitNormalInst [0]] 2349 +instret:242 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 2349 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 0000000000000010000000001fffff44000000 + 23500 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 23500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 23500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 23500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 23500 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } + 23500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 23500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6e <= 0000000000000000000000001fffff44000000 + 23510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 23510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23510 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 0000000000000064000000001fffff44000000 + 23510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 23510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 23510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 23510 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } + 23510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6f <= 0000000020000f30000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h000000008000153c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 23520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23520 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000000000000000c00000001fffff44000000 + 23520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 23520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 23520 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } + 23520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d10 +After delta: vaddr = 0x80003d10 + 23520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7b <= 0000000020000f40000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23530 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000000000000000000001fffff44000000 + 23530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000190 o: 'h0000000000000190 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d10 o: 'h0000000080003d10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d10, write: True, capStore: False, potentialCapLoad: False } + 23530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 23530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 23530 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } + 23530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 23530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23530 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h000000008000157c, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:243 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2353 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23540 : [doFinishMem] DTlbResp { resp: <'h0000000080003d10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d10 o: 'h0000000080003d10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d10, check_high: 'h00000000080003d14, check_inclusive: True } }, specBits: 'h000 } + 23540 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000000000000800000001fffff44000000 + 23540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 23540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h000000008000157c, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h000000008000157c, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 23540 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800015bc, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:244 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 2354 +instret:245 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 2354 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23550 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 23550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 23550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800015bc, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 23550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:246 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 2355 +instret:247 PC:0x1ffff0000000000000000000080000228 instr:0xa9c58593 iType:Alu [doCommitNormalInst [1]] 2355 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 78 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 23560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 23560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 23560 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } + 23560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 23560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:248 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 2356 +instret:249 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2356 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23570 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800015bc, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800015bc, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[RFile] wr_ 1: r 77 <= 0000000020000f30000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23570 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 05 <= 0000000000000005000000001fffff44000000 + 23570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 23570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 23570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 23570 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 23570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:250 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2357 +instret:251 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 2357 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 72 <= 0000000000000010000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d10, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 23580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23580 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000000000000800000001fffff44000000 + 23580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d08 +After delta: vaddr = 0x80003d08 + 23580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:252 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2358 +instret:253 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 2358 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hade, localHist: 'h3aa, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 70 <= 0000000020000f40000000001fffff44000000 + 23590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d08 o: 'h0000000080003d08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d08, write: True, capStore: False, potentialCapLoad: False } + 23590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 23590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 23590 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } + 23590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003d10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:254 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 2359 +instret:255 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 2359 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23600 : [doFinishMem] DTlbResp { resp: <'h0000000080003d08,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d08 o: 'h0000000080003d08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d08, check_high: 'h00000000080003d10, check_inclusive: True } }, specBits: 'h000 } + 23600 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 42 <= 0000000000000000000000001fffff44000000 + 23600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003d10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 23600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 23600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 23600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:256 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2360 +instret:257 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2360 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 40 <= 0000000000000002000000001fffff44000000 +[RFile] wr_ 1: r 4d <= 0000000000000010000000001fffff44000000 + 23610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 23610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x8000153c +After delta: vaddr = 0x8000153c + 23610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:258 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2361 +instret:259 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 2361 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 23620 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003d10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080003d10, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[RFile] wr_ 0: r 7e <= 000000002000054f000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 23620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h000000008000153c, write: False, capStore: False, potentialCapLoad: False } + 23620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 23620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0b <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23630 : [doFinishMem] DTlbResp { resp: <'h000000008000153c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h000000008000153c, check_high: 'h00000000080001540, check_inclusive: True } }, specBits: 'h000 } + 23630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h000000008000153c, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 23630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 23630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 23630 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 23630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:260 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2363 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h56f, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 76 <= 0000000020000f30000000001fffff44000000 + 23640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 23640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23640 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 0000000000000000000000001fffff44000000 + 23640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 23640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 23640 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } } + 23640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 23640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:261 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 2364 +instret:262 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 2364 +calling cycle +[RFile] wr_ 0: r 47 <= 0000000020000f40000000001fffff44000000 + 23650 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0d <= 0000000000000064000000001fffff44000000 + 23650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 23650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 23650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 23650 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 23650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23650 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080003d50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:263 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 2365 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, paddr: 'h000000008000153c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 23660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23660 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000000800000001fffff44000000 + 23660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080003d50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 23660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[ALU redirect - 1] 'h1ffff0000000000000000000080000276; 'h0; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } + 23670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 23670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 23670 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } + 23670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23670 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080003d90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:264 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 2367 +calling cycle + 23680 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080003d50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080003d50, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 23680 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h000000008000157c, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 23690 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 23690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080003d90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +calling cycle + 23700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h000000008000157c, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h000000008000157c, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23700 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800015bc, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +calling cycle + 23710 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080003d90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080003d90, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 23710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800015bc, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa3e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 23760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h827a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + 23770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + 23770 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 23770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000098 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4a <= 00000000200010a0800000001fffff44000000 + 23780 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000000800000001fffff44000000 + 23780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 52 <= 0000000020000f30000000001fffff44000000 + 23790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 49 <= 00000000200000a4000000001fffff44000000 + 23800 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 23800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h828c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0c <= 0000000000000010000000001fffff44000000 +[RFile] wr_ 1: r 50 <= 00000000200000a6000000001fffff44000000 + 23810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + 23810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + 23810 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } + 23810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 54 <= 0000000020000f40000000001fffff44000000 + 23820 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4b <= 0000000000000000000000001fffff44000000 + 23820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 23820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4c <= 00000000200003cc000000001fffff44000000 + 23830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000298 o: 'h0000000080000298 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 23830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 23830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 51 <= 00000000200003e4000000001fffff44000000 + 23840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 23840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 23840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 23840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 23850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 23850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 23850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 23850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 23860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 23860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 23860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 2: r 43 <= 0000000000000000000000001fffff44000000 + 23870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 23870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 23870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 23880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 23880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8338 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 23880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:265 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 2388 +instret:266 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 2388 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 23890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8342 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23890 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 02 <= 0000000020000f40000000001fffff44000000 + 23890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d00 +After delta: vaddr = 0x80003d00 + 23890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:267 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 2389 +instret:268 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 2389 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23900 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6b <= 0000000020000f40000000001fffff44000000 + 23900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d00, write: True, capStore: False, potentialCapLoad: False } + 23900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d00 +After delta: vaddr = 0x80003d00 + 23900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:269 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 2390 +instret:270 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 2390 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 23910 : [doFinishMem] DTlbResp { resp: <'h0000000080003d00,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d00, check_high: 'h00000000080003d08, check_inclusive: True } }, specBits: 'h000 } + 23910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d00, write: False, capStore: False, potentialCapLoad: False } + 23910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d08 +After delta: vaddr = 0x80003d08 + 23910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23920 : [doFinishMem] DTlbResp { resp: <'h0000000080003d00,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d00, check_high: 'h00000000080003d08, check_inclusive: True } }, specBits: 'h000 } + 23920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080003d00, shiftedBE: tagged DataMemAccess , pcHash: 'h833c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d08 o: 'h0000000080003d08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d08, write: False, capStore: False, potentialCapLoad: False } + 23920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 23920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:271 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2392 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23930 : [doFinishMem] DTlbResp { resp: <'h0000000080003d08,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d08 o: 'h0000000080003d08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d08, check_high: 'h00000000080003d10, check_inclusive: True } }, specBits: 'h000 } + 23930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080003d08, shiftedBE: tagged DataMemAccess , pcHash: 'h8346 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23930 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 45 <= 0000000000000000000000001fffff44000000 + 23930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 23930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 23930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hd6f, localHist: 'h0aa, globalTaken: True, localTaken: False, pcIndex: 'h1b4 }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 64 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 23940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h834c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23940 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5f <= 0000000000000000c00000001fffff44000000 + 23940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } + 23940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 23940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:272 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 2394 +instret:273 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 2394 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0e, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000018e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 23950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 23950 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 0000000020000f40000000001fffff44000000 + 23950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 23950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 23950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:274 PC:0x1ffff0000000000000000000080000276 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2395 +instret:275 PC:0x1ffff000000000000000000008000027a instr:0xfc842503 iType:Ld [doCommitNormalInst [1]] 2395 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 23960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } + 23960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d10 +After delta: vaddr = 0x80003d10 + 23960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:276 PC:0x1ffff000000000000000000008000027e instr:0x00551593 iType:Alu [doCommitNormalInst [0]] 2396 +instret:277 PC:0x1ffff0000000000000000000080000282 instr:0x00004517 iType:Auipc [doCommitNormalInst [1]] 2396 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } + 23970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d10 o: 'h0000000080003d10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d10, write: False, capStore: False, potentialCapLoad: False } + 23970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 23970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:278 PC:0x1ffff0000000000000000000080000286 instr:0xa3e50513 iType:Alu [doCommitNormalInst [0]] 2397 +instret:279 PC:0x1ffff000000000000000000008000028a instr:0x0000952e iType:Alu [doCommitNormalInst [1]] 2397 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23980 : [doFinishMem] DTlbResp { resp: <'h0000000080003d10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d10 o: 'h0000000080003d10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d10, check_high: 'h00000000080003d14, check_inclusive: True } }, specBits: 'h000 } + 23980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080003d10, shiftedBE: tagged DataMemAccess , pcHash: 'h8350 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 23980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 23980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:280 PC:0x1ffff000000000000000000008000028c instr:0xfd04258f iType:Ld [doCommitNormalInst [0]] 2398 +instret:281 PC:0x1ffff0000000000000000000080000290 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2398 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6a <= 00000000200003e4000000001fffff44000000 + 23990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 23990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8360 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23990 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5c <= 0000000000000064000000001fffff44000000 + 23990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 23990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 23990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:282 PC:0x1ffff0000000000000000000080000294 instr:0x098080e7 iType:Jr [doCommitNormalInst [0]] 2399 +instret:283 PC:0x1ffff0000000000000000000080000328 instr:0x0000711d iType:Alu [doCommitNormalInst [1]] 2399 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 24000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8364 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24000 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 69 <= 0000000000000000000000001fffff44000000 + 24000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 24000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffbc, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f4c +After delta: vaddr = 0x80000f4c + 24000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:284 PC:0x1ffff000000000000000000008000032a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2400 +instret:285 PC:0x1ffff000000000000000000008000032c instr:0x0000e8a2 iType:St [doCommitNormalInst [1]] 2400 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080003d00, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } + 24010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h84fa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24010 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000000000000000000001fffff44000000 + 24010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffbc, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000190 o: 'h0000000000000190 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } + 24010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 +instret:286 PC:0x1ffff000000000000000000008000032e instr:0x00001080 iType:Alu [doCommitNormalInst [0]] 2401 +instret:287 PC:0x1ffff0000000000000000000080000330 instr:0xfea43423 iType:St [doCommitNormalInst [1]] 2401 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h6b7, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 24020 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 66 <= 00000000200000a6000000001fffff44000000 + 24020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +instret:288 PC:0x1ffff0000000000000000000080000334 instr:0xfcb44823 iType:St [doCommitNormalInst [0]] 2402 +instret:289 PC:0x1ffff0000000000000000000080000338 instr:0xfe843503 iType:Ld [doCommitNormalInst [1]] 2402 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h002 } + 24030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h84fc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } +instret:290 PC:0x1ffff000000000000000000008000033c instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2403 +instret:291 PC:0x1ffff000000000000000000008000033e instr:0xfca43423 iType:St [doCommitNormalInst [1]] 2403 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080003d08, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24040 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 00000000200003f4000000001fffff44000000 + 24040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:292 PC:0x1ffff0000000000000000000080000342 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2404 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 24050 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800015bc, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 24050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:293 PC:0x1ffff0000000000000000000080000346 instr:0x00006508 iType:Ld [doCommitNormalInst [0]] 2405 +instret:294 PC:0x1ffff0000000000000000000080000348 instr:0xfca43023 iType:St [doCommitNormalInst [1]] 2405 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h03d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 58 <= 0000000000000000c00000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 24060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24060 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 24060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800015bc, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h35b, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03a, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080003d10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 24070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 24070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 24070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:295 PC:0x1ffff000000000000000000008000034c instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2407 +calling cycle + 24080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 24080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 24080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 24080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 24080 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } + 24080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h032 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 24080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } +instret:296 PC:0x1ffff0000000000000000000080000350 instr:0x00004908 iType:Ld [doCommitNormalInst [0]] 2408 +instret:297 PC:0x1ffff0000000000000000000080000352 instr:0xfaa42e23 iType:St [doCommitNormalInst [1]] 2408 +calling cycle + 24090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h020 } + 24090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24090 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 55 <= 0000000000000000800000001fffff44000000 + 24090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h022 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 24090 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } + 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +instret:298 PC:0x1ffff0000000000000000000080000356 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 2409 +instret:299 PC:0x1ffff0000000000000000000080000358 instr:0xfaa42c23 iType:St [doCommitNormalInst [1]] 2409 +calling cycle +[RFile] wr_ 1: r 70 <= 0000000000000000800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h020 } + 24100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24100 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 65 <= 0000000000000000800000001fffff44000000 + 24100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 24100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 24100 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } + 24100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } +instret:300 PC:0x1ffff000000000000000000008000035c instr:0x0040006f iType:J [doCommitNormalInst [0]] 2410 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h023, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h021, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24110 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 79 <= 0000000000000000000000001fffff44000000 + 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 24110 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } + 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:301 PC:0x1ffff0000000000000000000080000360 instr:0xfb842503 iType:Ld [doCommitNormalInst [0]] 2411 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h023, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h023, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6e <= 0000000000000000c00000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24120 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000000000000000000000001fffff44000000 + 24120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 24120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:302 PC:0x1ffff0000000000000000000080000364 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2412 +instret:303 PC:0x1ffff0000000000000000000080000368 instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2412 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h027, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h027, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h5; InstTag { way: 'h1, ptr: 'h09, t: 'h13 } + 24130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 24130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h020 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 24130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h023, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:304 PC:0x1ffff000000000000000000008000036c instr:0x18e0006f iType:J [doCommitNormalInst [0]] 2413 +instret:305 PC:0x1ffff00000000000000000000800004fa instr:0x000060e6 iType:Ld [doCommitNormalInst [1]] 2413 +calling cycle +[ROB incorrectSpec] 'h5 ; InstTag { way: 'h1, ptr: 'h09, t: 'h13 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h0 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:306 PC:0x1ffff00000000000000000000800004fc instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2415 +instret:307 PC:0x1ffff00000000000000000000800004fe instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2415 +calling cycle +instret:308 PC:0x1ffff0000000000000000000080000500 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2416 +instret:309 PC:0x1ffff0000000000000000000080000298 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2416 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } +instret:310 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [0]] 2417 +instret:311 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [1]] 2417 +calling cycle +instret:312 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 2418 +instret:313 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [1]] 2418 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:314 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [0]] 2419 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 24210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 24220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: False, data: } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7f <= 0000000020000484000000001fffff44000000 + 24230 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000000000000c00000001fffff44000000 + 24230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 77 <= 000000002000054d000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 24250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 0000000000000003000000001fffff44000000 + 24260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 24260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001540 +After delta: vaddr = 0x80001540 + 24260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 67 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 7d <= 0000000020000550000000001fffff44000000 + 24270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001540, write: False, capStore: False, potentialCapLoad: False } + 24270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 24270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 24270 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } + 24270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7e <= 0000000020000f30000000001fffff44000000 + 24280 : [doFinishMem] DTlbResp { resp: <'h0000000080001540,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001540, check_high: 'h00000000080001544, check_inclusive: True } }, specBits: 'h000 } + 24280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080001540, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24280 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000000000000000000001fffff44000000 + 24280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 24280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0d <= 0000000000000018000000001fffff44000000 + 24290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 24290 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } + 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 24290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24300 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 24300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24300 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000000000000190000000001fffff44000000 + 24300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 24300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 72 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080001540, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 24310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 24310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 24310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 24310 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 24310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 05 <= 0000000020000f30000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 24320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24320 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000000000000c00000001fffff44000000 + 24320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 24320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 24320 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 24320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d30 +After delta: vaddr = 0x80003d30 + 24320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24320 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 42 <= 0000000020000f48000000001fffff44000000 + 24330 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000000000000001fffff44000000 + 24330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000640 o: 'h0000000000000640 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d30 o: 'h0000000080003d30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d30, write: True, capStore: False, potentialCapLoad: False } + 24330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 24330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 24330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24340 : [doFinishMem] DTlbResp { resp: <'h0000000080003d30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d30 o: 'h0000000080003d30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d30, check_high: 'h00000000080003d34, check_inclusive: True } }, specBits: 'h000 } + 24340 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7c <= 0000000000000000c00000001fffff44000000 + 24340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 24340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24350 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800015c0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 24350 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 24350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 24350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24360 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080003d10, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +[RFile] wr_ 1: r 75 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 24360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 24360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 24360 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 24360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 43 <= 0000000020000f30000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24370 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000005000000001fffff44000000 + 24370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003d10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d08, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 24380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003d08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +calling cycle + 24390 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 24390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003d08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 24390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003d08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d00, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 24400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080003d00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +calling cycle + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080003d00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080003d00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24410 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080003d48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h832a } + 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080003d48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 24420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +calling cycle + 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } + 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24430 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080003d88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h832c } + 24440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080003d88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 24440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } + 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24450 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080003d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h5ad, localHist: 'h3d5, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8330 } + 24460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080003d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 24460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } +calling cycle + 24470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24470 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003d80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +calling cycle +[RFile] wr_ 1: r 58 <= 0000000000000000c00000001fffff44000000 + 24480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8334 } + 24480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003d80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 24480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24490 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 65 <= 0000000000000000c00000001fffff44000000 + 24490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } + 24490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h833e } + 24500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +instret:315 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 2451 +instret:316 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 2451 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000204; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8348 } + 24520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 24520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 24540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } + 24540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:317 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2454 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8352 } + 24550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } +calling cycle + 24560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } + 24560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8358 } + 24570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } + 24580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 24590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 24600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 24600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 24600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 24610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7f <= 0000000020000484000000001fffff44000000 + 24620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 24620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 24620 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 24620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:318 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2462 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 77 <= 000000002000054d000000001fffff44000000 + 24630 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000000000000c00000001fffff44000000 + 24630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 24650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 24650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:319 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2465 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 67 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 79 <= 0000000000000003000000001fffff44000000 + 24660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 24660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 24660 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } + 24660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001540 +After delta: vaddr = 0x80001540 + 24660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24670 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080003d50, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +[RFile] wr_ 1: r 7d <= 0000000020000550000000001fffff44000000 + 24670 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000000000000000000001fffff44000000 + 24670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001540, write: False, capStore: False, potentialCapLoad: False } + 24670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 24670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:320 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 2467 +instret:321 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2467 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7e <= 0000000020000f30000000001fffff44000000 + 24680 : [doFinishMem] DTlbResp { resp: <'h0000000080001540,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001540, check_high: 'h00000000080001544, check_inclusive: True } }, specBits: 'h000 } + 24680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080001540, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 24680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24680 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 24680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080003d50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 24680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:322 PC:0x1ffff0000000000000000000080000214 instr:0x32458693 iType:Alu [doCommitNormalInst [0]] 2468 +instret:323 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 2468 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0d <= 0000000000000018000000001fffff44000000 + 24690 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 24690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 24690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 24690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 24690 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } + 24690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 72 <= 0000000000000000000000001fffff44000000 + 24700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 24700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24700 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000000000000190000000001fffff44000000 + 24700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 24700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 24700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 24700 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 24700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 05 <= 0000000020000f30000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080001540, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 24710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24710 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000000000000c00000001fffff44000000 + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 24710 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d30 +After delta: vaddr = 0x80003d30 + 24710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 42 <= 0000000020000f48000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24720 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000000000000001fffff44000000 + 24720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000640 o: 'h0000000000000640 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d30 o: 'h0000000080003d30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d30, write: True, capStore: False, potentialCapLoad: False } + 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 24720 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } + 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 24720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:324 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2472 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24730 : [doFinishMem] DTlbResp { resp: <'h0000000080003d30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d30 o: 'h0000000080003d30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d30, check_high: 'h00000000080003d34, check_inclusive: True } }, specBits: 'h000 } + 24730 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7c <= 0000000000000000c00000001fffff44000000 + 24730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 24730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:325 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 2473 +instret:326 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 2473 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24740 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 24740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 24740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:327 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 2474 +instret:328 PC:0x1ffff0000000000000000000080000228 instr:0xa9c58593 iType:Alu [doCommitNormalInst [1]] 2474 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 75 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 24750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 24750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 24750 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 24750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 24750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:329 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 2475 +instret:330 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2475 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 43 <= 0000000020000f30000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24760 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000005000000001fffff44000000 + 24760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 24760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 24760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 24760 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 24760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:331 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2476 +instret:332 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 2476 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4e <= 0000000000000018000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d30, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 24770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24770 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 0000000000000000c00000001fffff44000000 + 24770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d28 +After delta: vaddr = 0x80003d28 + 24770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:333 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2477 +instret:334 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 2477 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'had6, localHist: 'h3d5, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0a <= 0000000020000f48000000001fffff44000000 + 24780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d28 o: 'h0000000080003d28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d28, write: True, capStore: False, potentialCapLoad: False } + 24780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 24780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 24780 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } + 24780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003d30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:335 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 2478 +instret:336 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 2478 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24790 : [doFinishMem] DTlbResp { resp: <'h0000000080003d28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d28 o: 'h0000000080003d28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d28, check_high: 'h00000000080003d30, check_inclusive: True } }, specBits: 'h000 } + 24790 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 57 <= 0000000000000000000000001fffff44000000 + 24790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003d30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 24790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003d30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 24790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:337 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2479 +instret:338 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2479 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 52 <= 0000000000000003000000001fffff44000000 +[RFile] wr_ 1: r 56 <= 0000000000000018000000001fffff44000000 + 24800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 24800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001540 +After delta: vaddr = 0x80001540 + 24800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:339 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2480 +instret:340 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 2480 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0c <= 0000000020000550000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d28, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 24810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001540, write: False, capStore: False, potentialCapLoad: False } + 24810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0e <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24820 : [doFinishMem] DTlbResp { resp: <'h0000000080001540,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001540, check_high: 'h00000000080001544, check_inclusive: True } }, specBits: 'h000 } + 24820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080001540, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 24820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 24820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 24820 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } + 24820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:341 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2482 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h56b, localHist: 'h3aa, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 46 <= 0000000020000f30000000001fffff44000000 + 24830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 24830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24830 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 54 <= 0000000000000000000000001fffff44000000 + 24830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 24830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 24830 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } + 24830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:342 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 2483 +instret:343 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 2483 +calling cycle +[RFile] wr_ 0: r 59 <= 0000000020000f48000000001fffff44000000 + 24840 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 68 <= 0000000000000190000000001fffff44000000 + 24840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 24840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 24840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 24840 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } + 24840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003d28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +instret:344 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 2484 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080001540, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 24850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24850 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6b <= 0000000000000000c00000001fffff44000000 + 24850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003d28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 24850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003d28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[ALU redirect - 1] 'h1ffff0000000000000000000080000276; 'h0; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } + 24860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 24860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 24860 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } + 24860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24860 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:345 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 2486 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 24880 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 24880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa3e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 24950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h827a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + 24960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827a } + 24960 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } } + 24960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000098 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4f <= 00000000200010a0800000001fffff44000000 + 24970 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 45 <= 0000000000000000c00000001fffff44000000 + 24970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24980 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080003d90, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +[RFile] wr_ 1: r 5f <= 0000000020000f30000000001fffff44000000 + 24980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5c <= 00000000200000a4000000001fffff44000000 + 24990 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 24990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h828c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24990 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 24990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080003d90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6b <= 0000000000000018000000001fffff44000000 +[RFile] wr_ 1: r 5d <= 00000000200000a6000000001fffff44000000 + 25000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + 25000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h828c } + 25000 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } + 25000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 08 <= 0000000020000f48000000001fffff44000000 + 25010 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 61 <= 0000000000000000000000001fffff44000000 + 25010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 25010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 60 <= 00000000200003cc000000001fffff44000000 + 25020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000298 o: 'h0000000080000298 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 25020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 25020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5a <= 00000000200003e4000000001fffff44000000 + 25030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 25030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 25030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 25030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 25040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 25040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 25040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 25050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 25050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 25050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 2: r 49 <= 0000000000000000000000001fffff44000000 + 25060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 25060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 25060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 25070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8338 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 25070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:346 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 2507 +instret:347 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 2507 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 25080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8342 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25080 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 0000000020000f48000000001fffff44000000 + 25080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d20 +After delta: vaddr = 0x80003d20 + 25080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:348 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 2508 +instret:349 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 2508 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25090 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 0000000020000f48000000001fffff44000000 + 25090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d20, write: True, capStore: False, potentialCapLoad: False } + 25090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d20 +After delta: vaddr = 0x80003d20 + 25090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:350 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 2509 +instret:351 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 2509 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25100 : [doFinishMem] DTlbResp { resp: <'h0000000080003d20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d20, check_high: 'h00000000080003d28, check_inclusive: True } }, specBits: 'h000 } + 25100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d20, write: False, capStore: False, potentialCapLoad: False } + 25100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d28 +After delta: vaddr = 0x80003d28 + 25100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25110 : [doFinishMem] DTlbResp { resp: <'h0000000080003d20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d20, check_high: 'h00000000080003d28, check_inclusive: True } }, specBits: 'h000 } + 25110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080003d20, shiftedBE: tagged DataMemAccess , pcHash: 'h833c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d28 o: 'h0000000080003d28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d28, write: False, capStore: False, potentialCapLoad: False } + 25110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 25110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:352 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2511 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25120 : [doFinishMem] DTlbResp { resp: <'h0000000080003d28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d28 o: 'h0000000080003d28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d28, check_high: 'h00000000080003d30, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d20, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 25120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080003d28, shiftedBE: tagged DataMemAccess , pcHash: 'h8346 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25120 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4c <= 0000000000000000000000001fffff44000000 + 25120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 25120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 25120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080003d28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hd6b, localHist: 'h055, globalTaken: True, localTaken: False, pcIndex: 'h1b4 }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 74 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 25130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h834c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } + 25130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080003d28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 25130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080003d28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 25130 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 25130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 25130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003d20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +instret:353 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 2513 +instret:354 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 2513 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0e, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000018e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 25140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 25140 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000000c00000001fffff44000000 + 25140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 25140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003d20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 25140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003d20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 25140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:355 PC:0x1ffff0000000000000000000080000276 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2514 +instret:356 PC:0x1ffff000000000000000000008000027a instr:0xfc842503 iType:Ld [doCommitNormalInst [1]] 2514 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 25150 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 55 <= 0000000020000f48000000001fffff44000000 + 25150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 25150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 25150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:357 PC:0x1ffff000000000000000000008000027e instr:0x00551593 iType:Alu [doCommitNormalInst [0]] 2515 +instret:358 PC:0x1ffff0000000000000000000080000282 instr:0x00004517 iType:Auipc [doCommitNormalInst [1]] 2515 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 25160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8360 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } + 25160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d30 +After delta: vaddr = 0x80003d30 + 25160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:359 PC:0x1ffff0000000000000000000080000286 instr:0xa3e50513 iType:Alu [doCommitNormalInst [0]] 2516 +instret:360 PC:0x1ffff000000000000000000008000028a instr:0x0000952e iType:Alu [doCommitNormalInst [1]] 2516 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } + 25170 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000000000000000000001fffff44000000 + 25170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d30 o: 'h0000000080003d30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d30, write: False, capStore: False, potentialCapLoad: False } + 25170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 25170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:361 PC:0x1ffff000000000000000000008000028c instr:0xfd04258f iType:Ld [doCommitNormalInst [0]] 2517 +instret:362 PC:0x1ffff0000000000000000000080000290 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2517 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7d <= 00000000200003e4000000001fffff44000000 + 25180 : [doFinishMem] DTlbResp { resp: <'h0000000080003d30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d30 o: 'h0000000080003d30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d30, check_high: 'h00000000080003d34, check_inclusive: True } }, specBits: 'h000 } + 25180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080003d30, shiftedBE: tagged DataMemAccess , pcHash: 'h8350 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 25180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 25180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080003d30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } +instret:363 PC:0x1ffff0000000000000000000080000294 instr:0x098080e7 iType:Jr [doCommitNormalInst [0]] 2518 +instret:364 PC:0x1ffff0000000000000000000080000328 instr:0x0000711d iType:Alu [doCommitNormalInst [1]] 2518 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 25190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8364 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 25190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080003d30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } + 25190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080003d30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } + 25190 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } + 25190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 +instret:365 PC:0x1ffff000000000000000000008000032a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2519 +instret:366 PC:0x1ffff000000000000000000008000032c instr:0x0000e8a2 iType:St [doCommitNormalInst [1]] 2519 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080003d20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h832a } + 25200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h84fa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25200 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6c <= 0000000000000190000000001fffff44000000 + 25200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + 25200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +instret:367 PC:0x1ffff000000000000000000008000032e instr:0x00001080 iType:Alu [doCommitNormalInst [0]] 2520 +instret:368 PC:0x1ffff0000000000000000000080000330 instr:0xfea43423 iType:St [doCommitNormalInst [1]] 2520 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h6b5, localHist: 'h3aa, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h002 } + 25210 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000000000000001fffff44000000 + 25210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } + 25210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffbc, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f4c +After delta: vaddr = 0x80000f4c +instret:369 PC:0x1ffff0000000000000000000080000334 instr:0xfcb44823 iType:St [doCommitNormalInst [0]] 2521 +instret:370 PC:0x1ffff0000000000000000000080000338 instr:0xfe843503 iType:Ld [doCommitNormalInst [1]] 2521 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h832c } + 25220 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h84fc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25220 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0b <= 00000000200000a6000000001fffff44000000 + 25220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffbc, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000640 o: 'h0000000000000640 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } + 25220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } +instret:371 PC:0x1ffff000000000000000000008000033c instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2522 +instret:372 PC:0x1ffff000000000000000000008000033e instr:0xfca43423 iType:St [doCommitNormalInst [1]] 2522 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080003d28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 25230 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 79 <= 00000000200003f4000000001fffff44000000 + 25230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } + 25230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:373 PC:0x1ffff0000000000000000000080000342 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2523 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8330 } + 25240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 25240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } +instret:374 PC:0x1ffff0000000000000000000080000346 instr:0x00006508 iType:Ld [doCommitNormalInst [0]] 2524 +instret:375 PC:0x1ffff0000000000000000000080000348 instr:0xfca43023 iType:St [doCommitNormalInst [1]] 2524 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 25250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 25250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 25250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h35a, localHist: 'h355, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h07d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 73 <= 0000000000000000c00000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080003d30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8334 } + 25260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 25260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 25260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:376 PC:0x1ffff000000000000000000008000034c instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2526 +calling cycle + 25270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 25270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 25270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 25270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 25270 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } + 25270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h078 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 25270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } +instret:377 PC:0x1ffff0000000000000000000080000350 instr:0x00004908 iType:Ld [doCommitNormalInst [0]] 2527 +instret:378 PC:0x1ffff0000000000000000000080000352 instr:0xfaa42e23 iType:St [doCommitNormalInst [1]] 2527 +calling cycle + 25280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h030 } + 25280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25280 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 67 <= 0000000000000000c00000001fffff44000000 + 25280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h070 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 25280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 25280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 25280 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } + 25280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +instret:379 PC:0x1ffff0000000000000000000080000356 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 2528 +instret:380 PC:0x1ffff0000000000000000000080000358 instr:0xfaa42c23 iType:St [doCommitNormalInst [1]] 2528 +calling cycle + 25290 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800015c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +[RFile] wr_ 0: r 0a <= 0000000000000000800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h020 } + 25290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25290 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000000000000c00000001fffff44000000 + 25290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 25290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 25290 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } } + 25290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:381 PC:0x1ffff000000000000000000008000035c instr:0x0040006f iType:J [doCommitNormalInst [0]] 2529 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h023, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h022, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25300 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0d <= 0000000000000000000000001fffff44000000 + 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 25300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } +instret:382 PC:0x1ffff0000000000000000000080000360 instr:0xfb842503 iType:Ld [doCommitNormalInst [0]] 2530 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h023, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h023, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 72 <= 0000000000000001000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 25310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 25310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 25310 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 25310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h020, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } +instret:383 PC:0x1ffff0000000000000000000080000364 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2531 +instret:384 PC:0x1ffff0000000000000000000080000368 instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2531 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h027, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h027, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h5; InstTag { way: 'h1, ptr: 'h09, t: 'h13 } + 25320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 25320 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000000000000000000001fffff44000000 + 25320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } + 25320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h020 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 25320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h023, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:385 PC:0x1ffff000000000000000000008000036c instr:0x18e0006f iType:J [doCommitNormalInst [0]] 2532 +instret:386 PC:0x1ffff00000000000000000000800004fa instr:0x000060e6 iType:Ld [doCommitNormalInst [1]] 2532 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h833e } + 25330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } +[ROB incorrectSpec] 'h5 ; InstTag { way: 'h1, ptr: 'h09, t: 'h13 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h0 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } + 25340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:387 PC:0x1ffff00000000000000000000800004fc instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2534 +instret:388 PC:0x1ffff00000000000000000000800004fe instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2534 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8348 } + 25350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } +instret:389 PC:0x1ffff0000000000000000000080000500 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2535 +instret:390 PC:0x1ffff0000000000000000000080000298 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2535 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:391 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [0]] 2536 +instret:392 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [1]] 2536 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8352 } + 25370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } +instret:393 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 2537 +instret:394 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [1]] 2537 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } + 25380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:395 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [0]] 2538 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8358 } + 25390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 25390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 25400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 25400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } + 25400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 25410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7c <= 0000000020000484000000001fffff44000000 + 25420 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000001000000001fffff44000000 + 25420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 25420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 43 <= 000000002000054d000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 25440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0d <= 0000000000000004000000001fffff44000000 + 25450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 25450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001544 +After delta: vaddr = 0x80001544 + 25450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 77 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 47 <= 0000000020000551000000001fffff44000000 + 25460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080001544 o: 'h0000000080001544 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001544 o: 'h0000000080001544 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001544, write: False, capStore: False, potentialCapLoad: False } + 25460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 25460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 25460 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 25460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0c <= 0000000020000f30000000001fffff44000000 + 25470 : [doFinishMem] DTlbResp { resp: <'h0000000080001544,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001544 o: 'h0000000080001544 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001544, check_high: 'h00000000080001548, check_inclusive: True } }, specBits: 'h000 } + 25470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080001544, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25470 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 0000000000000000000000001fffff44000000 + 25470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 25470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080001544, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 68 <= 0000000000000020000000001fffff44000000 + 25480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 25480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080001544, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 25480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080001544, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 25480 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 25480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 25480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25490 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 25490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25490 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000000000000000000001fffff44000000 + 25490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 25490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 25490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4e <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080001544, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 25500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 25500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 25500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 25500 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 25500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 62 <= 0000000020000f30000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 25510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25510 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 0000000000000000c00000001fffff44000000 + 25510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 25510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 25510 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 25510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d50 +After delta: vaddr = 0x80003d50 + 25510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 57 <= 0000000020000f50000000001fffff44000000 + 25520 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 0000000000000000000000001fffff44000000 + 25520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080003d40 o: 'h0000000080003d40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d50 o: 'h0000000080003d50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d50, write: True, capStore: False, potentialCapLoad: False } + 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 25520 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } + 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 25520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25530 : [doFinishMem] DTlbResp { resp: <'h0000000080003d50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d50 o: 'h0000000080003d50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d50, check_high: 'h00000000080003d54, check_inclusive: True } }, specBits: 'h000 } + 25530 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 02 <= 0000000000000001000000001fffff44000000 + 25530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 25530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25540 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 25540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 25540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 01 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 25550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 25550 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } } + 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 25550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 49 <= 0000000020000f30000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25560 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 45 <= 0000000000000005000000001fffff44000000 + 25560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 25560 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5e <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 25570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25570 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000001000000001fffff44000000 + 25570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d48 +After delta: vaddr = 0x80003d48 + 25570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hb5a, localHist: 'h3ea, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 54 <= 0000000020000f50000000001fffff44000000 + 25580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080003d40 o: 'h0000000080003d40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d48 o: 'h0000000080003d48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d48, write: True, capStore: False, potentialCapLoad: False } + 25580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 25580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 25580 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } + 25580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle + 25600 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h5ad, localHist: 'h3ea, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +calling cycle + 25680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[RFile] wr_ 1: r 73 <= 0000000000000000c00000001fffff44000000 + 25690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 25690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 25700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 25700 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } + 25700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25710 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000000000001000000001fffff44000000 + 25710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +instret:396 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 2573 +instret:397 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 2573 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 25740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h2d6, localHist: 'h355, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 25750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 25750 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } } + 25750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +instret:398 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2575 +instret:399 PC:0x1ffff0000000000000000000080000200 instr:0x0ae0006f iType:J [doCommitNormalInst [1]] 2575 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00a, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25760 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0d <= 0000000000000000000000001fffff44000000 + 25760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +instret:400 PC:0x1ffff00000000000000000000800002ae instr:0x0040006f iType:J [doCommitNormalInst [0]] 2576 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0a <= 0000000000000000800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 25770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 25780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 25780 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 25780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 25780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:401 PC:0x1ffff00000000000000000000800002b2 instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 2578 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h96b, localHist: 'h1f5, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0c <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 7c <= 0000000000000000400000001fffff44000000 + 25790 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000000000000000000001fffff44000000 + 25790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: True, capStore: False, potentialCapLoad: False } + 25790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 25790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 25800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 25800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:402 PC:0x1ffff00000000000000000000800002b6 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 2580 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h002 } + 25810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 25810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:403 PC:0x1ffff00000000000000000000800002b8 instr:0xfca42623 iType:St [doCommitNormalInst [0]] 2581 +instret:404 PC:0x1ffff00000000000000000000800002bc instr:0xf1fff06f iType:J [doCommitNormalInst [1]] 2581 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7e <= 0000000000000000c00000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 25820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82b8 } + 25820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 25820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h03a, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25830 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 57 <= 0000000000000000000000001fffff44000000 + 25830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } + 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h4b5, localHist: 'h355, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h028 } + 25840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h029 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 25840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h02b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 25850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 25850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 25850 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } + 25850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h3; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } + 25860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h009 } + 25860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25860 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 0000000000000000400000001fffff44000000 + 25860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } +calling cycle +[ROB incorrectSpec] 'h3 ; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 25880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 25880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 25880 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 25880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle + 25900 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hcb5, localHist: 'h3aa, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0a <= 0000000000000000800000001fffff44000000 + 25990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 25990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 26000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 26000 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 26000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 26000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'he5a, localHist: 'h2fa, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0c <= 0000000000000000000000001fffff44000000 + 26010 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000000000000400000001fffff44000000 + 26010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 26010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 26020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[RFile] wr_ 0: r 7e <= 0000000000000000c00000001fffff44000000 + 26030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 26030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, data: TaggedData { tag: False, data: } } +instret:405 PC:0x1ffff00000000000000000000800001da instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 2603 +instret:406 PC:0x1ffff00000000000000000000800001de instr:0x00004509 iType:Alu [doCommitNormalInst [1]] 2603 +calling cycle + 26040 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 57 <= 0000000000000000000000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h009, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:407 PC:0x1ffff00000000000000000000800001e0 instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2605 +instret:408 PC:0x1ffff00000000000000000000800001e8 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2605 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00a, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:409 PC:0x1ffff00000000000000000000800001ec instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 2606 +instret:410 PC:0x1ffff00000000000000000000800001ee instr:0xfca42423 iType:St [doCommitNormalInst [1]] 2606 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000204; 'h3; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81ee } + 26070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00b } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 26070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ee } +instret:411 PC:0x1ffff00000000000000000000800001f2 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2607 +instret:412 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [1]] 2607 +calling cycle +[ROB incorrectSpec] 'h3 ; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 26090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ee } + 26090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ee } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 26090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:413 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [0]] 2609 +instret:414 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [1]] 2609 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 26140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 26150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 26160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 26160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 02 <= 0000000020000484000000001fffff44000000 + 26170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 26170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 26170 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 26170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:415 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2617 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5e <= 000000002000054d000000001fffff44000000 + 26180 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000000000000000000001fffff44000000 + 26180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 26200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 26200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:416 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2620 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5f <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 49 <= 0000000000000000000000001fffff44000000 + 26210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 26210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 26210 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } } + 26210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001534 +After delta: vaddr = 0x80001534 + 26210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 54 <= 000000002000054d000000001fffff44000000 + 26220 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 45 <= 0000000000000000400000001fffff44000000 + 26220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080001534 o: 'h0000000080001534 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001534 o: 'h0000000080001534 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001534, write: False, capStore: False, potentialCapLoad: False } + 26220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 26220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:417 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 2622 +instret:418 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2622 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6b <= 0000000020000f30000000001fffff44000000 + 26230 : [doFinishMem] DTlbResp { resp: <'h0000000080001534,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001534 o: 'h0000000080001534 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001534, check_high: 'h00000000080001538, check_inclusive: True } }, specBits: 'h000 } + 26230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080001534, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 26230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 26230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080001534, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:419 PC:0x1ffff0000000000000000000080000214 instr:0x32458693 iType:Alu [doCommitNormalInst [0]] 2623 +instret:420 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 2623 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5c <= 0000000000000000000000001fffff44000000 + 26240 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 26240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 26240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080001534, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 26240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080001534, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 26240 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 26240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 26240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4f <= 0000000000000020000000001fffff44000000 + 26250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 26250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26250 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000006400000001fffff44000000 + 26250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 26250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 26250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 26250 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } + 26250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 66 <= 0000000020000f50000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080001534, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 26260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26260 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4b <= 0000000000000000c00000001fffff44000000 + 26260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 26260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 26260 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 26260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d50 +After delta: vaddr = 0x80003d50 + 26260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6a <= 0000000020000f50000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26270 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000000000000400000001fffff44000000 + 26270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080003d40 o: 'h0000000080003d40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000019 o: 'h0000000000000019 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d50 o: 'h0000000080003d50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d50, write: True, capStore: False, potentialCapLoad: False } + 26270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 26270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 26270 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } + 26270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 26270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:421 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2627 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 26280 : [doFinishMem] DTlbResp { resp: <'h0000000080003d50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d50 o: 'h0000000080003d50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d50, check_high: 'h00000000080003d54, check_inclusive: True } }, specBits: 'h000 } + 26280 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 0000000000000000000000001fffff44000000 + 26280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 26280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:422 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 2628 +instret:423 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 2628 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26290 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 26290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 26290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:424 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 2629 +instret:425 PC:0x1ffff0000000000000000000080000228 instr:0xa9c58593 iType:Alu [doCommitNormalInst [1]] 2629 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 53 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 26300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 26300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 26300 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 26300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 26300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:426 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 2630 +instret:427 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2630 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 50 <= 0000000020000f50000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26310 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 0000000000000005000000001fffff44000000 + 26310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 26310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 26310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 26310 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } + 26310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:428 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2631 +instret:429 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 2631 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 51 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 26320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26320 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 69 <= 0000000000000000000000001fffff44000000 + 26320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d48 +After delta: vaddr = 0x80003d48 + 26320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:430 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2632 +instret:431 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 2632 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf2d, localHist: 'h3ea, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 41 <= 0000000020000f50000000001fffff44000000 + 26330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080003d40 o: 'h0000000080003d40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d48 o: 'h0000000080003d48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d48, write: True, capStore: False, potentialCapLoad: False } + 26330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 26330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 26330 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 26330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003d50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:432 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 2633 +instret:433 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 2633 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26340 : [doFinishMem] DTlbResp { resp: <'h0000000080003d48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d48 o: 'h0000000080003d48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d48, check_high: 'h00000000080003d50, check_inclusive: True } }, specBits: 'h000 } + 26340 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6e <= 0000000000000000400000001fffff44000000 + 26340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003d50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 26340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003d50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 26340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 26340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:434 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2634 +instret:435 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2634 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6d <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 61 <= 0000000000000000000000001fffff44000000 + 26350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 26350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001534 +After delta: vaddr = 0x80001534 + 26350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:436 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2635 +instret:437 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 2635 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 55 <= 000000002000054d000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 26360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080001534 o: 'h0000000080001534 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001534 o: 'h0000000080001534 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001534, write: False, capStore: False, potentialCapLoad: False } + 26360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 26360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7b <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26370 : [doFinishMem] DTlbResp { resp: <'h0000000080001534,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001534 o: 'h0000000080001534 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001534, check_high: 'h00000000080001538, check_inclusive: True } }, specBits: 'h000 } + 26370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080001534, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 26370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 26370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 26370 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } + 26370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080001534, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:438 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2637 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h796, localHist: 'h3d5, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 74 <= 0000000020000f50000000001fffff44000000 + 26380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 26380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26380 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5d <= 0000000000000000400000001fffff44000000 + 26380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080001534, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 26380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080001534, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 26380 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } + 26380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 26380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:439 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 2638 +instret:440 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 2638 +calling cycle +[RFile] wr_ 0: r 58 <= 0000000020000f50000000001fffff44000000 + 26390 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6f <= 0000000000000006400000001fffff44000000 + 26390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 26390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 26390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 26390 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 26390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003d48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +instret:441 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 2639 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080001534, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 26400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26400 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 0000000000000000000000001fffff44000000 + 26400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003d48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 26400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003d48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 26400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 26410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 26410 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 26410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26410 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080003dd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:442 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 2641 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 05 <= 0000000000000000c00000001fffff44000000 + 26420 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000000000000000000001fffff44000000 + 26420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080003dd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 26420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 26420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26420 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080003dc8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 70 <= 0000000000000000400000001fffff44000000 + 26430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 26430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080003dc8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 26430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26440 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080003dd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080003dd0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 26440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 26440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 26440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h3cb, localHist: 'h3d5, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h4; InstTag { way: 'h1, ptr: 'h1b, t: 'h37 } + 26450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h010 } + 26450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h011 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 26450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +calling cycle +[ROB incorrectSpec] 'h4 ; InstTag { way: 'h1, ptr: 'h1b, t: 'h37 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 26470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 26470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 26470 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 26470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 26480 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 26520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 26530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 26540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 26540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 75 <= 0000000020000484000000001fffff44000000 + 26550 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 42 <= 0000000000000000400000001fffff44000000 + 26550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 73 <= 000000002000054d000000001fffff44000000 + 26560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 26570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 76 <= 0000000000000001000000001fffff44000000 + 26580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 26580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001538 +After delta: vaddr = 0x80001538 + 26580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7c <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 0d <= 000000002000054e000000001fffff44000000 + 26590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001538, write: False, capStore: False, potentialCapLoad: False } + 26590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 26590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 26590 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 26590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4e <= 0000000020000f30000000001fffff44000000 + 26600 : [doFinishMem] DTlbResp { resp: <'h0000000080001538,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001538, check_high: 'h0000000008000153c, check_inclusive: True } }, specBits: 'h000 } + 26600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080001538, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26600 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 0000000000000000400000001fffff44000000 + 26600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 26600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0a <= 0000000000000008000000001fffff44000000 +[RFile] wr_ 2: r 6c <= 0000000000000000000000001fffff44000000 + 26610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 26610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 26610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 26610 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } + 26610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 26610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 26620 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 26620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26620 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 43 <= 0000000000000019000000001fffff44000000 + 26620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 26620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 26620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } +instret:443 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 2662 +instret:444 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 2662 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 71 <= 0000000000000020000000001fffff44000000 + 26630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 26630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 26630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 26630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 26630 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 26630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d40 +After delta: vaddr = 0x80003d40 + 26630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } +instret:445 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 2663 +instret:446 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 2663 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 77 <= 0000000020000f50000000001fffff44000000 + 26640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 26640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 26640 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000000000000c00000001fffff44000000 + 26640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080003d40 o: 'h0000000080003d40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d40 o: 'h0000000080003d40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d40, write: True, capStore: False, potentialCapLoad: False } + 26640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 26640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 26640 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 26640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d70 +After delta: vaddr = 0x80003d70 + 26640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26640 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:447 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 2664 +instret:448 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 2664 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 62 <= 0000000020000f58000000001fffff44000000 + 26650 : [doFinishMem] DTlbResp { resp: <'h0000000080003d40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d40 o: 'h0000000080003d40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d40, check_high: 'h00000000080003d48, check_inclusive: True } }, specBits: 'h000 } + 26650 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000000400000001fffff44000000 + 26650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080003d60 o: 'h0000000080003d60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000064 o: 'h0000000000000064 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d70 o: 'h0000000080003d70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d70, write: True, capStore: False, potentialCapLoad: False } + 26650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 26650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26650 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800015b8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 26660 : [doFinishMem] DTlbResp { resp: <'h0000000080003d70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d70 o: 'h0000000080003d70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d70, check_high: 'h00000000080003d74, check_inclusive: True } }, specBits: 'h000 } + 26660 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 0000000000000000400000001fffff44000000 + 26660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 26660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800015b8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800015b8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:449 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2666 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26670 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 26670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 26670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4a <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 26680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 26680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 26680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 26680 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } + 26680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 26680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003d40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +instret:450 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 2668 +instret:451 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 2668 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 46 <= 0000000020000f50000000001fffff44000000 + 26690 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 0000000000000005000000001fffff44000000 + 26690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003d40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080003d40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:452 PC:0x1ffff0000000000000000000080000272 instr:0x02a0006f iType:J [doCommitNormalInst [0]] 2669 +instret:453 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [1]] 2669 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7e <= 0000000000000008000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 26700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 26700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26700 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 54 <= 0000000000000000400000001fffff44000000 + 26700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d68 +After delta: vaddr = 0x80003d68 + 26700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:454 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [0]] 2670 +instret:455 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [1]] 2670 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbcb, localHist: 'h1f5, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 57 <= 0000000020000f58000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080003d60 o: 'h0000000080003d60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d68 o: 'h0000000080003d68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d68, write: True, capStore: False, potentialCapLoad: False } + 26710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 26710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 26710 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 26710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26710 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080003dc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:456 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [0]] 2671 +instret:457 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [1]] 2671 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080001538, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26720 : [doFinishMem] DTlbResp { resp: <'h0000000080003d68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d68 o: 'h0000000080003d68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d68, check_high: 'h00000000080003d70, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 26720 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000000400000001fffff44000000 + 26720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080003dc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 26720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 26720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 02 <= 0000000000000001000000001fffff44000000 +[RFile] wr_ 1: r 64 <= 0000000000000008000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001538 +After delta: vaddr = 0x80001538 + 26730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 56 <= 000000002000054e000000001fffff44000000 + 26740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 26740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001538, write: False, capStore: False, potentialCapLoad: False } + 26740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 26740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 01 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26750 : [doFinishMem] DTlbResp { resp: <'h0000000080001538,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001538, check_high: 'h0000000008000153c, check_inclusive: True } }, specBits: 'h000 } + 26750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080001538, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 26750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 26750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 26750 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 26750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h5e5, localHist: 'h3ea, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 66 <= 0000000020000f50000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 26760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26760 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000000000000400000001fffff44000000 + 26760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 26760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 26760 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } } + 26760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 26760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +calling cycle +calling cycle + 26780 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 26780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 26780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 26780 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } + 26780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26780 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +calling cycle + 26790 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 26790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26790 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800015b8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +calling cycle + 26800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800015b8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800015b8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h2f2, localHist: 'h37d, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 26850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 05 <= 0000000000000000c00000001fffff44000000 + 26870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 26870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 26880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 26880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 26880 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 26880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26890 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000000000000400000001fffff44000000 + 26890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 26900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h179, localHist: 'h3d5, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 26910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 26910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 26910 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 26910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +instret:458 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 2691 +instret:459 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 2691 +calling cycle + 26920 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080003dd0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +[ALU redirect - 1] 'h1ffff0000000000000000000080000204; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } + 26920 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000000400000001fffff44000000 + 26920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 26940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26940 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 26940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080003dd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:460 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2694 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 26990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 27000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 27010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 75 <= 0000000020000484000000001fffff44000000 + 27020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 27020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 27020 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } + 27020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:461 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2702 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 73 <= 000000002000054d000000001fffff44000000 + 27030 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 42 <= 0000000000000000400000001fffff44000000 + 27030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 27050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 27050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:462 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2705 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7c <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 76 <= 0000000000000001000000001fffff44000000 + 27060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 27060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 27060 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 27060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001538 +After delta: vaddr = 0x80001538 + 27060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0d <= 000000002000054e000000001fffff44000000 + 27070 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 0000000000000000400000001fffff44000000 + 27070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001538, write: False, capStore: False, potentialCapLoad: False } + 27070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 27070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:463 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 2707 +instret:464 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2707 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4e <= 0000000020000f30000000001fffff44000000 + 27080 : [doFinishMem] DTlbResp { resp: <'h0000000080001538,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001538, check_high: 'h0000000008000153c, check_inclusive: True } }, specBits: 'h000 } + 27080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080001538, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 27080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 27080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:465 PC:0x1ffff0000000000000000000080000214 instr:0x32458693 iType:Alu [doCommitNormalInst [0]] 2708 +instret:466 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 2708 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0a <= 0000000000000008000000001fffff44000000 + 27090 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 27090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 27090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 27090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 27090 : [Ld resp] 'h0a; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } + 27090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 27090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 71 <= 0000000000000020000000001fffff44000000 + 27100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 27100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27100 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 43 <= 0000000000000019000000001fffff44000000 + 27100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 27100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 27100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 27100 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 27100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 77 <= 0000000020000f50000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080001538, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 27110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27110 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000000000000c00000001fffff44000000 + 27110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 27110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 27110 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 27110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d70 +After delta: vaddr = 0x80003d70 + 27110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 62 <= 0000000020000f58000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27120 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000000400000001fffff44000000 + 27120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080003d60 o: 'h0000000080003d60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000064 o: 'h0000000000000064 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d70 o: 'h0000000080003d70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d70, write: True, capStore: False, potentialCapLoad: False } + 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 27120 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } + 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 27120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:467 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2712 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27130 : [doFinishMem] DTlbResp { resp: <'h0000000080003d70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d70 o: 'h0000000080003d70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d70, check_high: 'h00000000080003d74, check_inclusive: True } }, specBits: 'h000 } + 27130 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 0000000000000000400000001fffff44000000 + 27130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 27130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:468 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 2713 +instret:469 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 2713 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27140 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 27140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 27140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:470 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 2714 +instret:471 PC:0x1ffff0000000000000000000080000228 instr:0xa9c58593 iType:Alu [doCommitNormalInst [1]] 2714 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4a <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 27150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 27150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 27150 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } + 27150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 27150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:472 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 2715 +instret:473 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2715 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 46 <= 0000000020000f50000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27160 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 0000000000000005000000001fffff44000000 + 27160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 27160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 27160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 27160 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } + 27160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:474 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2716 +instret:475 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 2716 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7e <= 0000000000000008000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d70, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 27170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27170 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 54 <= 0000000000000000400000001fffff44000000 + 27170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d68 +After delta: vaddr = 0x80003d68 + 27170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:476 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2717 +instret:477 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 2717 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h979, localHist: 'h1f5, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 57 <= 0000000020000f58000000001fffff44000000 + 27180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080003d60 o: 'h0000000080003d60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d68 o: 'h0000000080003d68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d68, write: True, capStore: False, potentialCapLoad: False } + 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 27180 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003d70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:478 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 2718 +instret:479 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 2718 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27190 : [doFinishMem] DTlbResp { resp: <'h0000000080003d68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d68 o: 'h0000000080003d68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d68, check_high: 'h00000000080003d70, check_inclusive: True } }, specBits: 'h000 } + 27190 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000000400000001fffff44000000 + 27190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003d70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 27190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003d70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 27190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:480 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2719 +instret:481 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2719 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 02 <= 0000000000000001000000001fffff44000000 +[RFile] wr_ 1: r 64 <= 0000000000000008000000001fffff44000000 + 27200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 27200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001538 +After delta: vaddr = 0x80001538 + 27200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:482 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2720 +instret:483 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 2720 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 56 <= 000000002000054e000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d68, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 27210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001538, write: False, capStore: False, potentialCapLoad: False } + 27210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 27210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 01 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27220 : [doFinishMem] DTlbResp { resp: <'h0000000080001538,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001538, check_high: 'h0000000008000153c, check_inclusive: True } }, specBits: 'h000 } + 27220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080001538, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 27220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 27220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 27220 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 27220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:484 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2722 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h4bc, localHist: 'h3ea, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 66 <= 0000000020000f50000000001fffff44000000 + 27230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 27230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27230 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000000000000400000001fffff44000000 + 27230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 27230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 27230 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } } + 27230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 27230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:485 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 2723 +instret:486 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 2723 +calling cycle +[RFile] wr_ 0: r 59 <= 0000000020000f58000000001fffff44000000 + 27240 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 45 <= 0000000000000019000000001fffff44000000 + 27240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 27240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 27240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 27240 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } + 27240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003d68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +instret:487 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 2724 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080001538, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 27250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27250 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 0000000000000000400000001fffff44000000 + 27250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003d68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 27250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003d68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 27260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 27260 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 27260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:488 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 2726 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5e <= 0000000000000000c00000001fffff44000000 + 27270 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 0000000000000000400000001fffff44000000 + 27270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 27270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4c <= 0000000000000000800000001fffff44000000 + 27280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 27280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 27290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 27290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h25e, localHist: 'h3d5, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h4; InstTag { way: 'h0, ptr: 'h18, t: 'h30 } + 27300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h010 } + 27300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h011 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 27300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +calling cycle +[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h18, t: 'h30 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 27320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 27320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 27320 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 27320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 27330 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 27380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 27390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6b <= 0000000020000484000000001fffff44000000 + 27400 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6f <= 0000000000000000800000001fffff44000000 + 27400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 69 <= 000000002000054d000000001fffff44000000 + 27410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 27420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6e <= 0000000000000002000000001fffff44000000 + 27430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 27430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x8000153c +After delta: vaddr = 0x8000153c + 27430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 60 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 74 <= 000000002000054f000000001fffff44000000 + 27440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h000000008000153c, write: False, capStore: False, potentialCapLoad: False } + 27440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 27440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 27440 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } + 27440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7f <= 0000000020000f30000000001fffff44000000 + 27450 : [doFinishMem] DTlbResp { resp: <'h000000008000153c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h000000008000153c, check_high: 'h00000000080001540, check_inclusive: True } }, specBits: 'h000 } + 27450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h000000008000153c, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27450 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6c <= 0000000000000000400000001fffff44000000 + 27450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 27450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4d <= 0000000000000010000000001fffff44000000 +[RFile] wr_ 2: r 5f <= 0000000000000000000000001fffff44000000 + 27460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 27460 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } + 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 27460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27470 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 27470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27470 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 65 <= 0000000000000064000000001fffff44000000 + 27470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 27470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 27470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } +instret:489 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 2747 +instret:490 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 2747 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5a <= 0000000000000020000000001fffff44000000 + 27480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 27480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 27480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 27480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 27480 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } + 27480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d60 +After delta: vaddr = 0x80003d60 + 27480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } +instret:491 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 2748 +instret:492 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 2748 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5d <= 0000000020000f50000000001fffff44000000 + 27490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 27490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 27490 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 0000000000000000c00000001fffff44000000 + 27490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080003d60 o: 'h0000000080003d60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d60 o: 'h0000000080003d60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d60, write: True, capStore: False, potentialCapLoad: False } + 27490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 27490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 27490 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } + 27490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d90 +After delta: vaddr = 0x80003d90 + 27490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:493 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 2749 +instret:494 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 2749 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 63 <= 0000000020000f60000000001fffff44000000 + 27500 : [doFinishMem] DTlbResp { resp: <'h0000000080003d60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d60 o: 'h0000000080003d60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d60, check_high: 'h00000000080003d68, check_inclusive: True } }, specBits: 'h000 } + 27500 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000000000000400000001fffff44000000 + 27500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080003d80 o: 'h0000000080003d80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000190 o: 'h0000000000000190 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d90 o: 'h0000000080003d90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d90, write: True, capStore: False, potentialCapLoad: False } + 27500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 27500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27510 : [doFinishMem] DTlbResp { resp: <'h0000000080003d90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d90 o: 'h0000000080003d90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d90, check_high: 'h00000000080003d94, check_inclusive: True } }, specBits: 'h000 } + 27510 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000000800000001fffff44000000 + 27510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 27510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:495 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2751 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27520 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 27520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 27520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 40 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 27530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 27530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 27530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 27530 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 27530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 27530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003d60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +instret:496 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 2753 +instret:497 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 2753 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 72 <= 0000000020000f50000000001fffff44000000 + 27540 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000005000000001fffff44000000 + 27540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 27540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003d60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 27540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003d60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:498 PC:0x1ffff0000000000000000000080000272 instr:0x02a0006f iType:J [doCommitNormalInst [0]] 2754 +instret:499 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [1]] 2754 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 05 <= 0000000000000010000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 27550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 27550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27550 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0d <= 0000000000000000800000001fffff44000000 + 27550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d88 +After delta: vaddr = 0x80003d88 + 27550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:500 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [0]] 2755 +instret:501 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [1]] 2755 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'ha5e, localHist: 'h0fa, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 78 <= 0000000020000f60000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080003d80 o: 'h0000000080003d80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d88 o: 'h0000000080003d88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d88, write: True, capStore: False, potentialCapLoad: False } + 27560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 27560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 27560 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } + 27560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:502 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [0]] 2756 +instret:503 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [1]] 2756 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h000000008000153c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27570 : [doFinishMem] DTlbResp { resp: <'h0000000080003d88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d88 o: 'h0000000080003d88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d88, check_high: 'h00000000080003d90, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 27570 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000000000000400000001fffff44000000 + 27570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 27570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 75 <= 0000000000000002000000001fffff44000000 +[RFile] wr_ 1: r 68 <= 0000000000000010000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 27580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 27580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x8000153c +After delta: vaddr = 0x8000153c + 27580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 61 <= 000000002000054f000000001fffff44000000 + 27590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 27590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h000000008000153c, write: False, capStore: False, potentialCapLoad: False } + 27590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 27590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 42 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27600 : [doFinishMem] DTlbResp { resp: <'h000000008000153c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h000000008000153c, check_high: 'h00000000080001540, check_inclusive: True } }, specBits: 'h000 } + 27600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h000000008000153c, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 27600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 27600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 27600 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 27600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h52f, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 77 <= 0000000020000f50000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 27610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27610 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000000400000001fffff44000000 + 27610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 27610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 27610 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 27610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 27610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +calling cycle +calling cycle + 27630 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 27630 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 27640 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h297, localHist: 'h3be, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 27700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5e <= 0000000000000000c00000001fffff44000000 + 27720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 27720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 27730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 27730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 27730 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 27730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27740 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 0000000000000000800000001fffff44000000 + 27740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 27750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h14b, localHist: 'h3d5, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 27760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 27760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 27760 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 27760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +instret:504 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 2776 +instret:505 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 2776 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000204; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } + 27770 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6e <= 0000000000000000400000001fffff44000000 + 27770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:506 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2779 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 27850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 27860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6b <= 0000000020000484000000001fffff44000000 + 27870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 27870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 27870 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } + 27870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:507 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2787 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 69 <= 000000002000054d000000001fffff44000000 + 27880 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6f <= 0000000000000000800000001fffff44000000 + 27880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 27900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 27900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:508 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2790 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 60 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 6e <= 0000000000000002000000001fffff44000000 + 27910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 27910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 27910 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } + 27910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x8000153c +After delta: vaddr = 0x8000153c + 27910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 74 <= 000000002000054f000000001fffff44000000 + 27920 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6c <= 0000000000000000400000001fffff44000000 + 27920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h000000008000153c, write: False, capStore: False, potentialCapLoad: False } + 27920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 27920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:509 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 2792 +instret:510 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2792 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7f <= 0000000020000f30000000001fffff44000000 + 27930 : [doFinishMem] DTlbResp { resp: <'h000000008000153c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h000000008000153c, check_high: 'h00000000080001540, check_inclusive: True } }, specBits: 'h000 } + 27930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h000000008000153c, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 27930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 27930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:511 PC:0x1ffff0000000000000000000080000214 instr:0x32458693 iType:Alu [doCommitNormalInst [0]] 2793 +instret:512 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 2793 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4d <= 0000000000000010000000001fffff44000000 + 27940 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 27940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 27940 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } + 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 27940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5a <= 0000000000000020000000001fffff44000000 + 27950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 27950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27950 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 65 <= 0000000000000064000000001fffff44000000 + 27950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 27950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 27950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 27950 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } + 27950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5d <= 0000000020000f50000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h000000008000153c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 27960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27960 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 0000000000000000c00000001fffff44000000 + 27960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 27960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 27960 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } + 27960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d90 +After delta: vaddr = 0x80003d90 + 27960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 63 <= 0000000020000f60000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27970 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000000000000400000001fffff44000000 + 27970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080003d80 o: 'h0000000080003d80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000190 o: 'h0000000000000190 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d90 o: 'h0000000080003d90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d90, write: True, capStore: False, potentialCapLoad: False } + 27970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 27970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 27970 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 27970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 27970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:513 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2797 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27980 : [doFinishMem] DTlbResp { resp: <'h0000000080003d90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d90 o: 'h0000000080003d90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d90, check_high: 'h00000000080003d94, check_inclusive: True } }, specBits: 'h000 } + 27980 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000000800000001fffff44000000 + 27980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 27980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:514 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 2798 +instret:515 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 2798 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27990 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 27990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 27990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:516 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 2799 +instret:517 PC:0x1ffff0000000000000000000080000228 instr:0xa9c58593 iType:Alu [doCommitNormalInst [1]] 2799 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 40 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 28000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 28000 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 28000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:518 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 2800 +instret:519 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2800 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 72 <= 0000000020000f50000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28010 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000005000000001fffff44000000 + 28010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 28010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 28010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 28010 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } } + 28010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:520 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2801 +instret:521 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 2801 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 05 <= 0000000000000010000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 28020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28020 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0d <= 0000000000000000800000001fffff44000000 + 28020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d88 +After delta: vaddr = 0x80003d88 + 28020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:522 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2802 +instret:523 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 2802 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h94b, localHist: 'h0fa, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 78 <= 0000000020000f60000000001fffff44000000 + 28030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080003d80 o: 'h0000000080003d80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d88 o: 'h0000000080003d88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d88, write: True, capStore: False, potentialCapLoad: False } + 28030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 28030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 28030 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } + 28030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003d90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:524 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 2803 +instret:525 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 2803 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28040 : [doFinishMem] DTlbResp { resp: <'h0000000080003d88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d88 o: 'h0000000080003d88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d88, check_high: 'h00000000080003d90, check_inclusive: True } }, specBits: 'h000 } + 28040 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000000000000400000001fffff44000000 + 28040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003d90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 28040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003d90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 28040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 28040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:526 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2804 +instret:527 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2804 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 75 <= 0000000000000002000000001fffff44000000 +[RFile] wr_ 1: r 68 <= 0000000000000010000000001fffff44000000 + 28050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 28050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x8000153c +After delta: vaddr = 0x8000153c + 28050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:528 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2805 +instret:529 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 2805 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 61 <= 000000002000054f000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 28060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h000000008000153c, write: False, capStore: False, potentialCapLoad: False } + 28060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 42 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28070 : [doFinishMem] DTlbResp { resp: <'h000000008000153c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h000000008000153c, check_high: 'h00000000080001540, check_inclusive: True } }, specBits: 'h000 } + 28070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h000000008000153c, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 28070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 28070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 28070 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 28070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:530 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2807 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h4a5, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 77 <= 0000000020000f50000000001fffff44000000 + 28080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 28080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28080 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000000400000001fffff44000000 + 28080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 28080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 28080 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 28080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:531 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 2808 +instret:532 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 2808 +calling cycle +[RFile] wr_ 0: r 43 <= 0000000020000f60000000001fffff44000000 + 28090 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 0000000000000064000000001fffff44000000 + 28090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 28090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 28090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 28090 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 28090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003d88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +instret:533 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 2809 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h000000008000153c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 28100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28100 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 0000000000000000800000001fffff44000000 + 28100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003d88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 28100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003d88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 28100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 28110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 28110 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } + 28110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28110 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080003e10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:534 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 2811 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 73 <= 0000000000000000c00000001fffff44000000 + 28120 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7e <= 0000000000000000800000001fffff44000000 + 28120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080003e10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 28120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28120 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080003e08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0e <= 0000000000000000c00000001fffff44000000 + 28130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 28130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080003e08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 28130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28140 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080003e10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080003e10, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 28140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 28140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 28140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h252, localHist: 'h3d5, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h4; InstTag { way: 'h0, ptr: 'h18, t: 'h30 } + 28150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h010 } + 28150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h011 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 28150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +calling cycle +[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h18, t: 'h30 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 28170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 28170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 28170 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 28170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 28180 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 28230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 28240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, data: TaggedData { tag: False, data: } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4e <= 0000000020000484000000001fffff44000000 + 28250 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 45 <= 0000000000000000c00000001fffff44000000 + 28250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 54 <= 000000002000054d000000001fffff44000000 + 28260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 28270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4f <= 0000000000000003000000001fffff44000000 + 28280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 28280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001540 +After delta: vaddr = 0x80001540 + 28280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5c <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 66 <= 0000000020000550000000001fffff44000000 + 28290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001540, write: False, capStore: False, potentialCapLoad: False } + 28290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 28290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 28290 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } + 28290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 08 <= 0000000020000f30000000001fffff44000000 + 28300 : [doFinishMem] DTlbResp { resp: <'h0000000080001540,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001540, check_high: 'h00000000080001544, check_inclusive: True } }, specBits: 'h000 } + 28300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080001540, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28300 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5f <= 0000000000000000400000001fffff44000000 + 28300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 28300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 50 <= 0000000000000018000000001fffff44000000 +[RFile] wr_ 2: r 7c <= 0000000000000000000000001fffff44000000 + 28310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 28310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 28310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 28310 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } + 28310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 28310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28320 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 28320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28320 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6a <= 0000000000000190000000001fffff44000000 + 28320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 28320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } +instret:535 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 2832 +instret:536 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 2832 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 53 <= 0000000000000020000000001fffff44000000 + 28330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 28330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 28330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 28330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 28330 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 28330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d80 +After delta: vaddr = 0x80003d80 + 28330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } +instret:537 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 2833 +instret:538 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 2833 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5b <= 0000000020000f50000000001fffff44000000 + 28340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 28340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 28340 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000000c00000001fffff44000000 + 28340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080003d80 o: 'h0000000080003d80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d80 o: 'h0000000080003d80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d80, write: True, capStore: False, potentialCapLoad: False } + 28340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 28340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 28340 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } + 28340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003db0 +After delta: vaddr = 0x80003db0 + 28340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28340 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:539 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 2834 +instret:540 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 2834 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4b <= 0000000020000f68000000001fffff44000000 + 28350 : [doFinishMem] DTlbResp { resp: <'h0000000080003d80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d80 o: 'h0000000080003d80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d80, check_high: 'h00000000080003d88, check_inclusive: True } }, specBits: 'h000 } + 28350 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4c <= 0000000000000000400000001fffff44000000 + 28350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080003da0 o: 'h0000000080003da0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000640 o: 'h0000000000000640 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003db0 o: 'h0000000080003db0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003db0, write: True, capStore: False, potentialCapLoad: False } + 28350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 28350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28360 : [doFinishMem] DTlbResp { resp: <'h0000000080003db0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003db0 o: 'h0000000080003db0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003db0, check_high: 'h00000000080003db4, check_inclusive: True } }, specBits: 'h000 } + 28360 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 02 <= 0000000000000000c00000001fffff44000000 + 28360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 28360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:541 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2836 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28370 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003d80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 28370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 28370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 55 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 28380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 28380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 28380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 28380 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 28380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 28380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003d80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +instret:542 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 2838 +instret:543 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 2838 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7a <= 0000000020000f50000000001fffff44000000 + 28390 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6e <= 0000000000000005000000001fffff44000000 + 28390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003d80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003d80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:544 PC:0x1ffff0000000000000000000080000272 instr:0x02a0006f iType:J [doCommitNormalInst [0]] 2839 +instret:545 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [1]] 2839 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5e <= 0000000000000018000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 28400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 28400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28400 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000000000000c00000001fffff44000000 + 28400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003da8 +After delta: vaddr = 0x80003da8 + 28400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:546 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [0]] 2840 +instret:547 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [1]] 2840 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'ha52, localHist: 'h07d, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 51 <= 0000000020000f68000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080003da0 o: 'h0000000080003da0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003da8 o: 'h0000000080003da8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003da8, write: True, capStore: False, potentialCapLoad: False } + 28410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 28410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 28410 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } + 28410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28410 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080003e00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:548 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [0]] 2841 +instret:549 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [1]] 2841 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080001540, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28420 : [doFinishMem] DTlbResp { resp: <'h0000000080003da8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003da8 o: 'h0000000080003da8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003da8, check_high: 'h00000000080003db0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 28420 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5a <= 0000000000000000400000001fffff44000000 + 28420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080003e00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 28420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 28420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6b <= 0000000000000003000000001fffff44000000 +[RFile] wr_ 1: r 67 <= 0000000000000018000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 28430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 28430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 28430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001540 +After delta: vaddr = 0x80001540 + 28430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 64 <= 0000000020000550000000001fffff44000000 + 28440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 28440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001540, write: False, capStore: False, potentialCapLoad: False } + 28440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6f <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28450 : [doFinishMem] DTlbResp { resp: <'h0000000080001540,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001540, check_high: 'h00000000080001544, check_inclusive: True } }, specBits: 'h000 } + 28450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080001540, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 28450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 28450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 28450 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } + 28450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h529, localHist: 'h3fa, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5d <= 0000000020000f50000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 28460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28460 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000000000000400000001fffff44000000 + 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 28460 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } + 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +calling cycle +calling cycle + 28480 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 28480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 28480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 28480 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } + 28480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28480 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +calling cycle + 28490 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 28490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h294, localHist: 'h3df, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 28550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 73 <= 0000000000000000c00000001fffff44000000 + 28570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 28570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 28580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 28580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 28580 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } + 28580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28590 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7e <= 0000000000000000c00000001fffff44000000 + 28590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 28600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h14a, localHist: 'h3d5, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 28610 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +instret:550 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 2861 +instret:551 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 2861 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28620 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080003e10, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +[ALU redirect - 1] 'h1ffff0000000000000000000080000204; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } + 28620 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000000400000001fffff44000000 + 28620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 28640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28640 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 28640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080003e10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:552 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2864 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 28700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 28710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4e <= 0000000020000484000000001fffff44000000 + 28720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 28720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 28720 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } } + 28720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:553 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2872 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 54 <= 000000002000054d000000001fffff44000000 + 28730 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 45 <= 0000000000000000c00000001fffff44000000 + 28730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 28750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 28750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:554 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2875 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5c <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 4f <= 0000000000000003000000001fffff44000000 + 28760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 28760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 28760 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } + 28760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001540 +After delta: vaddr = 0x80001540 + 28760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 66 <= 0000000020000550000000001fffff44000000 + 28770 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5f <= 0000000000000000400000001fffff44000000 + 28770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001540, write: False, capStore: False, potentialCapLoad: False } + 28770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 28770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:555 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 2877 +instret:556 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2877 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 08 <= 0000000020000f30000000001fffff44000000 + 28780 : [doFinishMem] DTlbResp { resp: <'h0000000080001540,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001540, check_high: 'h00000000080001544, check_inclusive: True } }, specBits: 'h000 } + 28780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080001540, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 28780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 28780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:557 PC:0x1ffff0000000000000000000080000214 instr:0x32458693 iType:Alu [doCommitNormalInst [0]] 2878 +instret:558 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 2878 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 50 <= 0000000000000018000000001fffff44000000 + 28790 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 28790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 28790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 28790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 28790 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } + 28790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 53 <= 0000000000000020000000001fffff44000000 + 28800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 28800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28800 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6a <= 0000000000000190000000001fffff44000000 + 28800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 28800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 28800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 28800 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 28800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5b <= 0000000020000f50000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080001540, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 28810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28810 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000000c00000001fffff44000000 + 28810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 28810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 28810 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } + 28810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003db0 +After delta: vaddr = 0x80003db0 + 28810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4b <= 0000000020000f68000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28820 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4c <= 0000000000000000400000001fffff44000000 + 28820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080003da0 o: 'h0000000080003da0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000640 o: 'h0000000000000640 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003db0 o: 'h0000000080003db0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003db0, write: True, capStore: False, potentialCapLoad: False } + 28820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 28820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 28820 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } + 28820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 28820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:559 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2882 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28830 : [doFinishMem] DTlbResp { resp: <'h0000000080003db0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003db0 o: 'h0000000080003db0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003db0, check_high: 'h00000000080003db4, check_inclusive: True } }, specBits: 'h000 } + 28830 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 02 <= 0000000000000000c00000001fffff44000000 + 28830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 28830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:560 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 2883 +instret:561 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 2883 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28840 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 28840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 28840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:562 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 2884 +instret:563 PC:0x1ffff0000000000000000000080000228 instr:0xa9c58593 iType:Alu [doCommitNormalInst [1]] 2884 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 55 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 28850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 28850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 28850 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 28850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 28850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:564 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 2885 +instret:565 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2885 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7a <= 0000000020000f50000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28860 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6e <= 0000000000000005000000001fffff44000000 + 28860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 28860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 28860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 28860 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 28860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:566 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2886 +instret:567 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 2886 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5e <= 0000000000000018000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003db0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 28870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28870 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000000000000c00000001fffff44000000 + 28870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003da8 +After delta: vaddr = 0x80003da8 + 28870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:568 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2887 +instret:569 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 2887 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h94a, localHist: 'h07d, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 51 <= 0000000020000f68000000001fffff44000000 + 28880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080003da0 o: 'h0000000080003da0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003da8 o: 'h0000000080003da8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003da8, write: True, capStore: False, potentialCapLoad: False } + 28880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 28880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 28880 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } + 28880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003db0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:570 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 2888 +instret:571 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 2888 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28890 : [doFinishMem] DTlbResp { resp: <'h0000000080003da8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003da8 o: 'h0000000080003da8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003da8, check_high: 'h00000000080003db0, check_inclusive: True } }, specBits: 'h000 } + 28890 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5a <= 0000000000000000400000001fffff44000000 + 28890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003db0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 28890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003db0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 28890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 28890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:572 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2889 +instret:573 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 2889 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6b <= 0000000000000003000000001fffff44000000 +[RFile] wr_ 1: r 67 <= 0000000000000018000000001fffff44000000 + 28900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 28900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001540 +After delta: vaddr = 0x80001540 + 28900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:574 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2890 +instret:575 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 2890 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 64 <= 0000000020000550000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003da8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 28910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001540, write: False, capStore: False, potentialCapLoad: False } + 28910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6f <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28920 : [doFinishMem] DTlbResp { resp: <'h0000000080001540,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001540, check_high: 'h00000000080001544, check_inclusive: True } }, specBits: 'h000 } + 28920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080001540, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 28920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 28920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 28920 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } + 28920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:576 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2892 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h4a5, localHist: 'h3fa, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5d <= 0000000020000f50000000001fffff44000000 + 28930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 28930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28930 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000000000000400000001fffff44000000 + 28930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 28930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 28930 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } + 28930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:577 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 2893 +instret:578 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 2893 +calling cycle +[RFile] wr_ 0: r 65 <= 0000000020000f68000000001fffff44000000 + 28940 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6c <= 0000000000000190000000001fffff44000000 + 28940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 28940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 28940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 28940 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } + 28940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003da8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +instret:579 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 2894 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080001540, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 28950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28950 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 72 <= 0000000000000000c00000001fffff44000000 + 28950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003da8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 28950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003da8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 28950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 28960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 28960 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } + 28960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:580 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 2896 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 69 <= 0000000000000000c00000001fffff44000000 + 28970 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 05 <= 0000000000000000c00000001fffff44000000 + 28970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7b <= 0000000000000001000000001fffff44000000 + 28980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 28980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 28990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 28990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h252, localHist: 'h3d5, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h4; InstTag { way: 'h0, ptr: 'h18, t: 'h30 } + 29000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h010 } + 29000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h011 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 29000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +calling cycle +[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h18, t: 'h30 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 29020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 29020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 29020 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } + 29020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 29030 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 29070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 29080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 29090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 29090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7f <= 0000000020000484000000001fffff44000000 + 29100 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 0000000000000001000000001fffff44000000 + 29100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0d <= 000000002000054d000000001fffff44000000 + 29110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 29120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 71 <= 0000000000000004000000001fffff44000000 + 29130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 29130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001544 +After delta: vaddr = 0x80001544 + 29130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0a <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 77 <= 0000000020000551000000001fffff44000000 + 29140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080001544 o: 'h0000000080001544 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001544 o: 'h0000000080001544 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001544, write: False, capStore: False, potentialCapLoad: False } + 29140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 29140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 29140 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } + 29140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 52 <= 0000000020000f30000000001fffff44000000 + 29150 : [doFinishMem] DTlbResp { resp: <'h0000000080001544,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001544 o: 'h0000000080001544 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001544, check_high: 'h00000000080001548, check_inclusive: True } }, specBits: 'h000 } + 29150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080001544, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29150 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7c <= 0000000000000000400000001fffff44000000 + 29150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 29150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080001544, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 46 <= 0000000000000020000000001fffff44000000 +[RFile] wr_ 2: r 60 <= 0000000000000000000000001fffff44000000 + 29160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 29160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080001544, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 29160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080001544, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 29160 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 29160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 29160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 29170 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 29170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29170 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000000000000001fffff44000000 + 29170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 29170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 29170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } +instret:581 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 2917 +instret:582 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 2917 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4a <= 0000000000000020000000001fffff44000000 + 29180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 29180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 29180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 29180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 29180 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } + 29180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003da0 +After delta: vaddr = 0x80003da0 + 29180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } +instret:583 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 2918 +instret:584 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 2918 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0c <= 0000000020000f50000000001fffff44000000 + 29190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 29190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 29190 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 43 <= 0000000000000000c00000001fffff44000000 + 29190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080003da0 o: 'h0000000080003da0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003da0 o: 'h0000000080003da0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003da0, write: True, capStore: False, potentialCapLoad: False } + 29190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 29190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 29190 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } } + 29190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003dd0 +After delta: vaddr = 0x80003dd0 + 29190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:585 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 2919 +instret:586 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 2919 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 44 <= 0000000020000f70000000001fffff44000000 + 29200 : [doFinishMem] DTlbResp { resp: <'h0000000080003da0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003da0 o: 'h0000000080003da0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003da0, check_high: 'h00000000080003da8, check_inclusive: True } }, specBits: 'h000 } + 29200 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0e <= 0000000000000000400000001fffff44000000 + 29200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080003dc0 o: 'h0000000080003dc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003dd0 o: 'h0000000080003dd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003dd0, write: True, capStore: False, potentialCapLoad: False } + 29200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 29200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 29210 : [doFinishMem] DTlbResp { resp: <'h0000000080003dd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003dd0 o: 'h0000000080003dd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003dd0, check_high: 'h00000000080003dd4, check_inclusive: True } }, specBits: 'h000 } + 29210 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000001000000001fffff44000000 + 29210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 29210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:587 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2921 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29220 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003da0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 29220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 29220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 56 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 29230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 29230 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 29230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003da0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +instret:588 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 2923 +instret:589 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 2923 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 49 <= 0000000020000f50000000001fffff44000000 + 29240 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000005000000001fffff44000000 + 29240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 29240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003da0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 29240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003da0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 29240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:590 PC:0x1ffff0000000000000000000080000272 instr:0x02a0006f iType:J [doCommitNormalInst [0]] 2924 +instret:591 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [1]] 2924 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 73 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 29250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 29250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29250 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 66 <= 0000000000000001000000001fffff44000000 + 29250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003dc8 +After delta: vaddr = 0x80003dc8 + 29250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:592 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [0]] 2925 +instret:593 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [1]] 2925 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'ha52, localHist: 'h03e, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7e <= 0000000020000f70000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080003dc0 o: 'h0000000080003dc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003dc8 o: 'h0000000080003dc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003dc8, write: True, capStore: False, potentialCapLoad: False } + 29260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 29260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 29260 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 29260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:594 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [0]] 2926 +instret:595 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [1]] 2926 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080001544, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29270 : [doFinishMem] DTlbResp { resp: <'h0000000080003dc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003dc8 o: 'h0000000080003dc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003dc8, check_high: 'h00000000080003dd0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 29270 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000000400000001fffff44000000 + 29270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 29270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4e <= 0000000000000004000000001fffff44000000 +[RFile] wr_ 1: r 41 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 29280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 29280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 29280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001544 +After delta: vaddr = 0x80001544 + 29280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 68 <= 0000000020000551000000001fffff44000000 + 29290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 29290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080001544 o: 'h0000000080001544 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001544 o: 'h0000000080001544 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001544, write: False, capStore: False, potentialCapLoad: False } + 29290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 29290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 45 <= 0000000000000020000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29300 : [doFinishMem] DTlbResp { resp: <'h0000000080001544,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001544 o: 'h0000000080001544 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001544, check_high: 'h00000000080001548, check_inclusive: True } }, specBits: 'h000 } + 29300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080001544, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 29300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 29300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 29300 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } + 29300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080001544, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h529, localHist: 'h3fd, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5b <= 0000000020000f50000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 29310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29310 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4c <= 0000000000000000400000001fffff44000000 + 29310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080001544, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 29310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080001544, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 29310 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } + 29310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 29310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +calling cycle +calling cycle + 29330 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 29330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 29330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 29330 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 29330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 29340 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h294, localHist: 'h3ef, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 29400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 69 <= 0000000000000000c00000001fffff44000000 + 29420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 29420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 29430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 29430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 29430 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } + 29430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29440 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 05 <= 0000000000000001000000001fffff44000000 + 29440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 29450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h14a, localHist: 'h3d5, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 29460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 29460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 29460 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } + 29460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +instret:596 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 2946 +instret:597 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 2946 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29470 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000000000000400000001fffff44000000 + 29470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7c <= 0000000000000000800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h008 } + 29480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } +instret:598 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2948 +instret:599 PC:0x1ffff0000000000000000000080000200 instr:0x0ae0006f iType:J [doCommitNormalInst [1]] 2948 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 29490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 29490 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 29490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 29490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:600 PC:0x1ffff00000000000000000000800002ae instr:0x0040006f iType:J [doCommitNormalInst [0]] 2949 +instret:601 PC:0x1ffff00000000000000000000800002b2 instr:0xfcc42503 iType:Ld [doCommitNormalInst [1]] 2949 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h8a5, localHist: 'h3ef, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7f <= 0000000000000000800000001fffff44000000 + 29500 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000000400000001fffff44000000 + 29500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: True, capStore: False, potentialCapLoad: False } + 29500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 29500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 52 <= 0000000000000000000000001fffff44000000 + 29510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 29510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 29510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h012 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:602 PC:0x1ffff00000000000000000000800002b6 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 2951 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h002 } + 29520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 29520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:603 PC:0x1ffff00000000000000000000800002b8 instr:0xfca42623 iType:St [doCommitNormalInst [0]] 2952 +instret:604 PC:0x1ffff00000000000000000000800002bc instr:0xf1fff06f iType:J [doCommitNormalInst [1]] 2952 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 57 <= 0000000000000000c00000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 29530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82b8 } + 29530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 29530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 29530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29540 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000000000000000000001fffff44000000 + 29540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 29540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } + 29540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 29540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h452, localHist: 'h3d5, globalTaken: True, localTaken: True, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 29550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 29550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h011 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 29560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 29560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 29560 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } + 29560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h0; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } + 29570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h011 } + 29570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29570 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 0000000000000000800000001fffff44000000 + 29570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 29590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 29590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 29590 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } + 29590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle + 29610 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hc52, localHist: 'h3ea, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 29680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +calling cycle + 29690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[RFile] wr_ 1: r 7c <= 0000000000000000800000001fffff44000000 + 29700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 29700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 29710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 29710 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 29710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 29720 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000000800000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h629, localHist: 'h2aa, globalTaken: True, localTaken: True, pcIndex: 'h169 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 29740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:605 PC:0x1ffff00000000000000000000800001da instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 2974 +instret:606 PC:0x1ffff00000000000000000000800001de instr:0x00004509 iType:Alu [doCommitNormalInst [1]] 2974 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 52 <= 0000000000000000000000001fffff44000000 +[ALU redirect - 1] 'h1ffff00000000000000000000800001e8; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } + 29750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: True, capStore: False, potentialCapLoad: False } + 29750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 29750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:607 PC:0x1ffff00000000000000000000800001e0 instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2977 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 29830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'he29, localHist: 'h3f7, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 52 <= 0000000000000000000000001fffff44000000 + 29840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 29840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +calling cycle + 29850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 29850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +instret:608 PC:0x1ffff00000000000000000000800001e8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2985 +instret:609 PC:0x1ffff00000000000000000000800001ec instr:0x00004501 iType:Alu [doCommitNormalInst [1]] 2985 +calling cycle +[RFile] wr_ 1: r 57 <= 0000000000000000c00000001fffff44000000 + 29860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 29860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } +instret:610 PC:0x1ffff00000000000000000000800001ee instr:0xfca42423 iType:St [doCommitNormalInst [0]] 2986 +instret:611 PC:0x1ffff00000000000000000000800001f2 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2986 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81ee } + 29870 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000000000000000000001fffff44000000 + 29870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ee } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ee } + 29880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ee } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 29880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:612 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 2989 +instret:613 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 2989 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h2; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } + 29900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +calling cycle +[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:614 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 2992 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 29970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 29980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 29990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 29990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 75 <= 0000000020000484000000001fffff44000000 + 30000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 30000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 30000 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } + 30000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:615 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3000 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 73 <= 000000002000054d000000001fffff44000000 + 30010 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 56 <= 0000000000000000000000001fffff44000000 + 30010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 30030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 30030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:616 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 3003 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4e <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 49 <= 0000000000000000000000001fffff44000000 + 30040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 30040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 30040 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 30040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001534 +After delta: vaddr = 0x80001534 + 30040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7e <= 000000002000054d000000001fffff44000000 + 30050 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000000800000001fffff44000000 + 30050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080001534 o: 'h0000000080001534 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001534 o: 'h0000000080001534 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001534, write: False, capStore: False, potentialCapLoad: False } + 30050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 30050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:617 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 3005 +instret:618 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 3005 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 68 <= 0000000020000f30000000001fffff44000000 + 30060 : [doFinishMem] DTlbResp { resp: <'h0000000080001534,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001534 o: 'h0000000080001534 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001534, check_high: 'h00000000080001538, check_inclusive: True } }, specBits: 'h000 } + 30060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080001534, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 30060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 30060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001534, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:619 PC:0x1ffff0000000000000000000080000214 instr:0x32458693 iType:Alu [doCommitNormalInst [0]] 3006 +instret:620 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 3006 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5c <= 0000000000000000000000001fffff44000000 + 30070 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 30070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 30070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001534, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 30070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001534, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 30070 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } + 30070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 30070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 66 <= 0000000000000040000000001fffff44000000 + 30080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 30080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30080 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 42 <= 0000000000000006400000001fffff44000000 + 30080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 30080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 30080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 30080 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 30080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5f <= 0000000020000f70000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080001534, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 30090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30090 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000000000000c00000001fffff44000000 + 30090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 30090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 30090 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } + 30090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003dd0 +After delta: vaddr = 0x80003dd0 + 30090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 53 <= 0000000020000f70000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30100 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 41 <= 0000000000000000800000001fffff44000000 + 30100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080003dc0 o: 'h0000000080003dc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000019 o: 'h0000000000000019 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003dd0 o: 'h0000000080003dd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003dd0, write: True, capStore: False, potentialCapLoad: False } + 30100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 30100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 30100 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } + 30100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 30100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:621 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 3010 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 30110 : [doFinishMem] DTlbResp { resp: <'h0000000080003dd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003dd0 o: 'h0000000080003dd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003dd0, check_high: 'h00000000080003dd4, check_inclusive: True } }, specBits: 'h000 } + 30110 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4c <= 0000000000000000000000001fffff44000000 + 30110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 30110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:622 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 3011 +instret:623 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 3011 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30120 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 30120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 30120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:624 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 3012 +instret:625 PC:0x1ffff0000000000000000000080000228 instr:0xa9c58593 iType:Alu [doCommitNormalInst [1]] 3012 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6a <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 30130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 30130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 30130 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 30130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 30130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:626 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 3013 +instret:627 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 3013 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4b <= 0000000020000f70000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30140 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 0000000000000005000000001fffff44000000 + 30140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 30140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 30140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 30140 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 30140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:628 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 3014 +instret:629 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 3014 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 55 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003dd0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 30150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30150 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000000000000000000001fffff44000000 + 30150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003dc8 +After delta: vaddr = 0x80003dc8 + 30150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:630 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3015 +instret:631 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 3015 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf14, localHist: 'h03e, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 50 <= 0000000020000f70000000001fffff44000000 + 30160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080003dc0 o: 'h0000000080003dc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003dc8 o: 'h0000000080003dc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003dc8, write: True, capStore: False, potentialCapLoad: False } + 30160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 30160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 30160 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } + 30160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003dd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:632 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 3016 +instret:633 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 3016 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30170 : [doFinishMem] DTlbResp { resp: <'h0000000080003dc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003dc8 o: 'h0000000080003dc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003dc8, check_high: 'h00000000080003dd0, check_inclusive: True } }, specBits: 'h000 } + 30170 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 0000000000000000800000001fffff44000000 + 30170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003dd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 30170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003dd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 30170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 30170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:634 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 3017 +instret:635 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 3017 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 59 <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 5a <= 0000000000000000000000001fffff44000000 + 30180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 30180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001534 +After delta: vaddr = 0x80001534 + 30180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:636 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 3018 +instret:637 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 3018 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 51 <= 000000002000054d000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003dc8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 30190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080001534 o: 'h0000000080001534 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001534 o: 'h0000000080001534 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001534, write: False, capStore: False, potentialCapLoad: False } + 30190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 30190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6e <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30200 : [doFinishMem] DTlbResp { resp: <'h0000000080001534,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001534 o: 'h0000000080001534 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001534, check_high: 'h00000000080001538, check_inclusive: True } }, specBits: 'h000 } + 30200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080001534, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 30200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 30200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 30200 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } + 30200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080001534, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:638 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 3020 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h78a, localHist: 'h3fd, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6c <= 0000000020000f70000000001fffff44000000 + 30210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 30210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30210 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5d <= 0000000000000000800000001fffff44000000 + 30210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080001534, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 30210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080001534, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 30210 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } + 30210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 30210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:639 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 3021 +instret:640 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 3021 +calling cycle +[RFile] wr_ 0: r 08 <= 0000000020000f70000000001fffff44000000 + 30220 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5e <= 0000000000000006400000001fffff44000000 + 30220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 30220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 30220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 30220 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 30220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003dc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +instret:641 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 3022 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080001534, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 30230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30230 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 0000000000000000000000001fffff44000000 + 30230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003dc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 30230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003dc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 30230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 30240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 30240 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } + 30240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30240 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003e50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:642 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 3024 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 78 <= 0000000000000000c00000001fffff44000000 + 30250 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 0000000000000000000000001fffff44000000 + 30250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003e50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 30250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 30250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30250 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080003e48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6d <= 0000000000000000400000001fffff44000000 + 30260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 30260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080003e48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 30260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30270 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003e50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080003e50, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 30270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 30270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 30270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h3c5, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h4; InstTag { way: 'h1, ptr: 'h1b, t: 'h37 } + 30280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h010 } + 30280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h011 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 30280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +calling cycle +[ROB incorrectSpec] 'h4 ; InstTag { way: 'h1, ptr: 'h1b, t: 'h37 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 30300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 30300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 30300 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 30300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 30310 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 30350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 30360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 30370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 30370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, data: TaggedData { tag: False, data: } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 47 <= 0000000020000484000000001fffff44000000 + 30380 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 61 <= 0000000000000000400000001fffff44000000 + 30380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 69 <= 000000002000054d000000001fffff44000000 + 30390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 30400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 76 <= 0000000000000001000000001fffff44000000 + 30410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 30410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001538 +After delta: vaddr = 0x80001538 + 30410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7f <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 71 <= 000000002000054e000000001fffff44000000 + 30420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001538, write: False, capStore: False, potentialCapLoad: False } + 30420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 30420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 30420 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 30420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4a <= 0000000020000f30000000001fffff44000000 + 30430 : [doFinishMem] DTlbResp { resp: <'h0000000080001538,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001538, check_high: 'h0000000008000153c, check_inclusive: True } }, specBits: 'h000 } + 30430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080001538, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30430 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000000000000800000001fffff44000000 + 30430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 30430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7c <= 0000000000000008000000001fffff44000000 +[RFile] wr_ 2: r 54 <= 0000000000000000000000001fffff44000000 + 30440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 30440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 30440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 30440 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } } + 30440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 30440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 30450 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 30450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30450 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0d <= 0000000000000019000000001fffff44000000 + 30450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 30450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 30450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } +instret:643 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 3045 +instret:644 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 3045 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 05 <= 0000000000000040000000001fffff44000000 + 30460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 30460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 30460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 30460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 30460 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 30460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003dc0 +After delta: vaddr = 0x80003dc0 + 30460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } +instret:645 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 3046 +instret:646 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 3046 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0a <= 0000000020000f70000000001fffff44000000 + 30470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 30470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 30470 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000000c00000001fffff44000000 + 30470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080003dc0 o: 'h0000000080003dc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003dc0 o: 'h0000000080003dc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003dc0, write: True, capStore: False, potentialCapLoad: False } + 30470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 30470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 30470 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } + 30470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003df0 +After delta: vaddr = 0x80003df0 + 30470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30470 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:647 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 3047 +instret:648 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 3047 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0c <= 0000000020000f78000000001fffff44000000 + 30480 : [doFinishMem] DTlbResp { resp: <'h0000000080003dc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003dc0 o: 'h0000000080003dc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003dc0, check_high: 'h00000000080003dc8, check_inclusive: True } }, specBits: 'h000 } + 30480 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 0000000000000000800000001fffff44000000 + 30480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080003de0 o: 'h0000000080003de0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000064 o: 'h0000000000000064 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003df0 o: 'h0000000080003df0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003df0, write: True, capStore: False, potentialCapLoad: False } + 30480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 30480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30480 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800015b8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 30490 : [doFinishMem] DTlbResp { resp: <'h0000000080003df0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003df0 o: 'h0000000080003df0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003df0, check_high: 'h00000000080003df4, check_inclusive: True } }, specBits: 'h000 } + 30490 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6b <= 0000000000000000400000001fffff44000000 + 30490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 30490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800015b8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800015b8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:649 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 3049 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30500 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003dc0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 30500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 30500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 43 <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 30510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 30510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 30510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 30510 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } + 30510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 30510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003dc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +instret:650 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 3051 +instret:651 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 3051 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0e <= 0000000020000f70000000001fffff44000000 + 30520 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 0000000000000005000000001fffff44000000 + 30520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 30520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003dc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 30520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003dc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 30520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:652 PC:0x1ffff0000000000000000000080000272 instr:0x02a0006f iType:J [doCommitNormalInst [0]] 3052 +instret:653 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [1]] 3052 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 57 <= 0000000000000008000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 30530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 30530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30530 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7e <= 0000000000000000400000001fffff44000000 + 30530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003de8 +After delta: vaddr = 0x80003de8 + 30530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:654 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [0]] 3053 +instret:655 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [1]] 3053 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbc5, localHist: 'h01f, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 44 <= 0000000020000f78000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080003de0 o: 'h0000000080003de0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003de8 o: 'h0000000080003de8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003de8, write: True, capStore: False, potentialCapLoad: False } + 30540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 30540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 30540 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } + 30540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30540 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080003e40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:656 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [0]] 3054 +instret:657 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [1]] 3054 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, paddr: 'h0000000080001538, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30550 : [doFinishMem] DTlbResp { resp: <'h0000000080003de8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003de8 o: 'h0000000080003de8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003de8, check_high: 'h00000000080003df0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 30550 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 66 <= 0000000000000000800000001fffff44000000 + 30550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080003e40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 30550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 30550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 75 <= 0000000000000001000000001fffff44000000 +[RFile] wr_ 1: r 45 <= 0000000000000008000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 30560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 30560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 30560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001538 +After delta: vaddr = 0x80001538 + 30560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 67 <= 000000002000054e000000001fffff44000000 + 30570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 30570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001538, write: False, capStore: False, potentialCapLoad: False } + 30570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 30570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 56 <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30580 : [doFinishMem] DTlbResp { resp: <'h0000000080001538,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001538, check_high: 'h0000000008000153c, check_inclusive: True } }, specBits: 'h000 } + 30580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080001538, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 30580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 30580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 30580 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } + 30580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h5e2, localHist: 'h3fe, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5f <= 0000000020000f70000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 30590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30590 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 41 <= 0000000000000000800000001fffff44000000 + 30590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 30590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 30590 : [Ld resp] 'h14; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 30590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 30590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +calling cycle +calling cycle + 30610 : [doRespLdMem] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 30610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 30610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 30610 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } + 30610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30610 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +calling cycle + 30620 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 30620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001578, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30620 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800015b8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +calling cycle + 30630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800015b8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800015b8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h2f1, localHist: 'h3fb, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 30680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 78 <= 0000000000000000c00000001fffff44000000 + 30700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 30700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 30710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 30710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 30710 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } + 30710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30720 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 0000000000000000400000001fffff44000000 + 30720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 30730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h178, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 30740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 30740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 30740 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 30740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +instret:658 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 3074 +instret:659 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 3074 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30750 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080003e50, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +[ALU redirect - 1] 'h1ffff0000000000000000000080000204; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } + 30750 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000000800000001fffff44000000 + 30750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 30770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30770 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 30770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003e50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 30770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:660 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 3077 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 30820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 30830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 30840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 30840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 47 <= 0000000020000484000000001fffff44000000 + 30850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 30850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 30850 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } + 30850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:661 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3085 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 69 <= 000000002000054d000000001fffff44000000 + 30860 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 61 <= 0000000000000000400000001fffff44000000 + 30860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 30880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 30880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:662 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 3088 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7f <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 76 <= 0000000000000001000000001fffff44000000 + 30890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 30890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 30890 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 30890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001538 +After delta: vaddr = 0x80001538 + 30890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 71 <= 000000002000054e000000001fffff44000000 + 30900 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000000000000800000001fffff44000000 + 30900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001538, write: False, capStore: False, potentialCapLoad: False } + 30900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 30900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:663 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 3090 +instret:664 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 3090 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4a <= 0000000020000f30000000001fffff44000000 + 30910 : [doFinishMem] DTlbResp { resp: <'h0000000080001538,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001538, check_high: 'h0000000008000153c, check_inclusive: True } }, specBits: 'h000 } + 30910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080001538, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 30910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 30910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:665 PC:0x1ffff0000000000000000000080000214 instr:0x32458693 iType:Alu [doCommitNormalInst [0]] 3091 +instret:666 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 3091 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7c <= 0000000000000008000000001fffff44000000 + 30920 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 30920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 30920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 30920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 30920 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } } + 30920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 30920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 05 <= 0000000000000040000000001fffff44000000 + 30930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 30930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30930 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0d <= 0000000000000019000000001fffff44000000 + 30930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 30930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 30930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 30930 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 30930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0a <= 0000000020000f70000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, paddr: 'h0000000080001538, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 30940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30940 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000000c00000001fffff44000000 + 30940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 30940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 30940 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } + 30940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003df0 +After delta: vaddr = 0x80003df0 + 30940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0c <= 0000000020000f78000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30950 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 0000000000000000800000001fffff44000000 + 30950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080003de0 o: 'h0000000080003de0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000064 o: 'h0000000000000064 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003df0 o: 'h0000000080003df0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003df0, write: True, capStore: False, potentialCapLoad: False } + 30950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 30950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 30950 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } + 30950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 30950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:667 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 3095 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 30960 : [doFinishMem] DTlbResp { resp: <'h0000000080003df0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003df0 o: 'h0000000080003df0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003df0, check_high: 'h00000000080003df4, check_inclusive: True } }, specBits: 'h000 } + 30960 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6b <= 0000000000000000400000001fffff44000000 + 30960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 30960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:668 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 3096 +instret:669 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 3096 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30970 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 30970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 30970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:670 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 3097 +instret:671 PC:0x1ffff0000000000000000000080000228 instr:0xa9c58593 iType:Alu [doCommitNormalInst [1]] 3097 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 43 <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 30980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 30980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 30980 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } + 30980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 30980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:672 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 3098 +instret:673 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 3098 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0e <= 0000000020000f70000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30990 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 0000000000000005000000001fffff44000000 + 30990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 30990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 30990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 30990 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } + 30990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:674 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 3099 +instret:675 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 3099 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 57 <= 0000000000000008000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003df0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 31000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31000 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7e <= 0000000000000000400000001fffff44000000 + 31000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003de8 +After delta: vaddr = 0x80003de8 + 31000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:676 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3100 +instret:677 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 3100 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h978, localHist: 'h01f, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 44 <= 0000000020000f78000000001fffff44000000 + 31010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080003de0 o: 'h0000000080003de0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003de8 o: 'h0000000080003de8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003de8, write: True, capStore: False, potentialCapLoad: False } + 31010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 31010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 31010 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } + 31010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003df0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:678 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 3101 +instret:679 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 3101 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31020 : [doFinishMem] DTlbResp { resp: <'h0000000080003de8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003de8 o: 'h0000000080003de8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003de8, check_high: 'h00000000080003df0, check_inclusive: True } }, specBits: 'h000 } + 31020 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 66 <= 0000000000000000800000001fffff44000000 + 31020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003df0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 31020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003df0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 31020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 31020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:680 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 3102 +instret:681 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 3102 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 75 <= 0000000000000001000000001fffff44000000 +[RFile] wr_ 1: r 45 <= 0000000000000008000000001fffff44000000 + 31030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 31030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001538 +After delta: vaddr = 0x80001538 + 31030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:682 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 3103 +instret:683 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 3103 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 67 <= 000000002000054e000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003de8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 31040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001538, write: False, capStore: False, potentialCapLoad: False } + 31040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 31040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 56 <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31050 : [doFinishMem] DTlbResp { resp: <'h0000000080001538,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001538 o: 'h0000000080001538 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001538, check_high: 'h0000000008000153c, check_inclusive: True } }, specBits: 'h000 } + 31050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080001538, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 31050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 31050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 31050 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } + 31050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:684 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 3105 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h4bc, localHist: 'h3fe, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5f <= 0000000020000f70000000001fffff44000000 + 31060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 31060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31060 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 41 <= 0000000000000000800000001fffff44000000 + 31060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 31060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080001538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 31060 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 31060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 31060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:685 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 3106 +instret:686 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 3106 +calling cycle +[RFile] wr_ 0: r 42 <= 0000000020000f78000000001fffff44000000 + 31070 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000019000000001fffff44000000 + 31070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 31070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 31070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 31070 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } + 31070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003de8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +instret:687 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 3107 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080001538, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 31080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31080 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4b <= 0000000000000000400000001fffff44000000 + 31080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003de8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 31080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003de8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 31080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 31090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 31090 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } + 31090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:688 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 3109 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 73 <= 0000000000000000c00000001fffff44000000 + 31100 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 55 <= 0000000000000000400000001fffff44000000 + 31100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 31100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 02 <= 0000000000000000800000001fffff44000000 + 31110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 31110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 31120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 31120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h25e, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h4; InstTag { way: 'h0, ptr: 'h18, t: 'h30 } + 31130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h010 } + 31130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h011 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 31130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +calling cycle +[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h18, t: 'h30 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 31150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 31150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 31150 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } + 31150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 31160 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 31200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 31210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 31220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 31220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, data: TaggedData { tag: False, data: } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 68 <= 0000000020000484000000001fffff44000000 + 31230 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5e <= 0000000000000000800000001fffff44000000 + 31230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 01 <= 000000002000054d000000001fffff44000000 + 31240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 31250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 64 <= 0000000000000002000000001fffff44000000 + 31260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 31260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x8000153c +After delta: vaddr = 0x8000153c + 31260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 60 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 6c <= 000000002000054f000000001fffff44000000 + 31270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h000000008000153c, write: False, capStore: False, potentialCapLoad: False } + 31270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 31270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 31270 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } + 31270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 40 <= 0000000020000f30000000001fffff44000000 + 31280 : [doFinishMem] DTlbResp { resp: <'h000000008000153c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h000000008000153c, check_high: 'h00000000080001540, check_inclusive: True } }, specBits: 'h000 } + 31280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h000000008000153c, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31280 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 54 <= 0000000000000000800000001fffff44000000 + 31280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 31280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4d <= 0000000000000010000000001fffff44000000 +[RFile] wr_ 2: r 4e <= 0000000000000000000000001fffff44000000 + 31290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 31290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 31290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 31290 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 31290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 31290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 31300 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 31300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31300 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000000000064000000001fffff44000000 + 31300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 31300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 31300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } +instret:689 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 3130 +instret:690 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 3130 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 63 <= 0000000000000040000000001fffff44000000 + 31310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 31310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 31310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 31310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 31310 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } + 31310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003de0 +After delta: vaddr = 0x80003de0 + 31310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } +instret:691 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 3131 +instret:692 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 3131 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5d <= 0000000020000f70000000001fffff44000000 + 31320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 31320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 31320 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 0000000000000000c00000001fffff44000000 + 31320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080003de0 o: 'h0000000080003de0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003de0 o: 'h0000000080003de0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003de0, write: True, capStore: False, potentialCapLoad: False } + 31320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 31320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 31320 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 31320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003e10 +After delta: vaddr = 0x80003e10 + 31320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:693 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 3132 +instret:694 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 3132 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 70 <= 0000000020000f80000000001fffff44000000 + 31330 : [doFinishMem] DTlbResp { resp: <'h0000000080003de0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003de0 o: 'h0000000080003de0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003de0, check_high: 'h00000000080003de8, check_inclusive: True } }, specBits: 'h000 } + 31330 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000000800000001fffff44000000 + 31330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080003e00 o: 'h0000000080003e00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000190 o: 'h0000000000000190 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003e10 o: 'h0000000080003e10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003e10, write: True, capStore: False, potentialCapLoad: False } + 31330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 31330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 31340 : [doFinishMem] DTlbResp { resp: <'h0000000080003e10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003e10 o: 'h0000000080003e10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003e10, check_high: 'h00000000080003e14, check_inclusive: True } }, specBits: 'h000 } + 31340 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000000800000001fffff44000000 + 31340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 31340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:695 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 3134 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31350 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003de0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 31350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 31350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 65 <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 31360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 31360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 31360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 31360 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 31360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 31360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003de0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +instret:696 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 3136 +instret:697 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 3136 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7b <= 0000000020000f70000000001fffff44000000 + 31370 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000005000000001fffff44000000 + 31370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 31370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003de0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 31370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080003de0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 31370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:698 PC:0x1ffff0000000000000000000080000272 instr:0x02a0006f iType:J [doCommitNormalInst [0]] 3137 +instret:699 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [1]] 3137 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 78 <= 0000000000000010000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 31380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 31380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31380 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000000000000800000001fffff44000000 + 31380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003e08 +After delta: vaddr = 0x80003e08 + 31380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:700 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [0]] 3138 +instret:701 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [1]] 3138 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'ha5e, localHist: 'h00f, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 58 <= 0000000020000f80000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080003e00 o: 'h0000000080003e00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003e08 o: 'h0000000080003e08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003e08, write: True, capStore: False, potentialCapLoad: False } + 31390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 31390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 31390 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } + 31390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:702 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [0]] 3139 +instret:703 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [1]] 3139 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h000000008000153c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31400 : [doFinishMem] DTlbResp { resp: <'h0000000080003e08,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003e08 o: 'h0000000080003e08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003e08, check_high: 'h00000000080003e10, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 31400 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 05 <= 0000000000000000800000001fffff44000000 + 31400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 31400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 47 <= 0000000000000002000000001fffff44000000 +[RFile] wr_ 1: r 46 <= 0000000000000010000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 31410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 31410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 31410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x8000153c +After delta: vaddr = 0x8000153c + 31410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5a <= 000000002000054f000000001fffff44000000 + 31420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 31420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h000000008000153c, write: False, capStore: False, potentialCapLoad: False } + 31420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 31420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 61 <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31430 : [doFinishMem] DTlbResp { resp: <'h000000008000153c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h000000008000153c, check_high: 'h00000000080001540, check_inclusive: True } }, specBits: 'h000 } + 31430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h000000008000153c, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 31430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 31430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 31430 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } + 31430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0f, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h52f, localHist: 'h3ff, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0a <= 0000000020000f70000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 31440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31440 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 0000000000000000800000001fffff44000000 + 31440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 31440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0f, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 31440 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 31440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 31440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +calling cycle +calling cycle + 31460 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 31460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 31460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 31460 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } } + 31460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 31470 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h297, localHist: 'h3fd, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 31530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 73 <= 0000000000000000c00000001fffff44000000 + 31550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 31550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 31560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 31560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 31560 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } + 31560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31570 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 55 <= 0000000000000000800000001fffff44000000 + 31570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 31580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h14b, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 31590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 31590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 31590 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } + 31590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +instret:704 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 3159 +instret:705 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 3159 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000204; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } + 31600 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 0000000000000000800000001fffff44000000 + 31600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:706 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 3162 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 31670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 31680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 31690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 31690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 68 <= 0000000020000484000000001fffff44000000 + 31700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 31700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 31700 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } + 31700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:707 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3170 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 01 <= 000000002000054d000000001fffff44000000 + 31710 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5e <= 0000000000000000800000001fffff44000000 + 31710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 31730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 31730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:708 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 3173 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 60 <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 64 <= 0000000000000002000000001fffff44000000 + 31740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 31740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 31740 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } + 31740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x8000153c +After delta: vaddr = 0x8000153c + 31740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6c <= 000000002000054f000000001fffff44000000 + 31750 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 54 <= 0000000000000000800000001fffff44000000 + 31750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h000000008000153c, write: False, capStore: False, potentialCapLoad: False } + 31750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 31750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:709 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 3175 +instret:710 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 3175 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 40 <= 0000000020000f30000000001fffff44000000 + 31760 : [doFinishMem] DTlbResp { resp: <'h000000008000153c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h000000008000153c, check_high: 'h00000000080001540, check_inclusive: True } }, specBits: 'h000 } + 31760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h000000008000153c, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 31760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 31760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:711 PC:0x1ffff0000000000000000000080000214 instr:0x32458693 iType:Alu [doCommitNormalInst [0]] 3176 +instret:712 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 3176 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4d <= 0000000000000010000000001fffff44000000 + 31770 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 31770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 31770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 31770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 31770 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 31770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 31770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 63 <= 0000000000000040000000001fffff44000000 + 31780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 31780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31780 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000000000064000000001fffff44000000 + 31780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 31780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 31780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 31780 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } + 31780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5d <= 0000000020000f70000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h000000008000153c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 31790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31790 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 0000000000000000c00000001fffff44000000 + 31790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 31790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 31790 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 31790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003e10 +After delta: vaddr = 0x80003e10 + 31790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 70 <= 0000000020000f80000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31800 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000000800000001fffff44000000 + 31800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080003e00 o: 'h0000000080003e00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000190 o: 'h0000000000000190 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003e10 o: 'h0000000080003e10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003e10, write: True, capStore: False, potentialCapLoad: False } + 31800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 31800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 31800 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 31800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 31800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:713 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 3180 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 31810 : [doFinishMem] DTlbResp { resp: <'h0000000080003e10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003e10 o: 'h0000000080003e10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003e10, check_high: 'h00000000080003e14, check_inclusive: True } }, specBits: 'h000 } + 31810 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000000800000001fffff44000000 + 31810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 31810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:714 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 3181 +instret:715 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 3181 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31820 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 31820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 31820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:716 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 3182 +instret:717 PC:0x1ffff0000000000000000000080000228 instr:0xa9c58593 iType:Alu [doCommitNormalInst [1]] 3182 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 65 <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 31830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 31830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 31830 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 31830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 31830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:718 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 3183 +instret:719 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 3183 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7b <= 0000000020000f70000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31840 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000005000000001fffff44000000 + 31840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 31840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 31840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 31840 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } + 31840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:720 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 3184 +instret:721 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 3184 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 78 <= 0000000000000010000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003e10, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 31850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31850 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000000000000800000001fffff44000000 + 31850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003e08 +After delta: vaddr = 0x80003e08 + 31850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:722 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3185 +instret:723 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 3185 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h94b, localHist: 'h00f, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 58 <= 0000000020000f80000000001fffff44000000 + 31860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080003e00 o: 'h0000000080003e00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003e08 o: 'h0000000080003e08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003e08, write: True, capStore: False, potentialCapLoad: False } + 31860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 31860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 31860 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } + 31860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003e10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:724 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 3186 +instret:725 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 3186 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31870 : [doFinishMem] DTlbResp { resp: <'h0000000080003e08,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003e08 o: 'h0000000080003e08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003e08, check_high: 'h00000000080003e10, check_inclusive: True } }, specBits: 'h000 } + 31870 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 05 <= 0000000000000000800000001fffff44000000 + 31870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003e10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 31870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003e10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 31870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 31870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:726 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 3187 +instret:727 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 3187 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 47 <= 0000000000000002000000001fffff44000000 +[RFile] wr_ 1: r 46 <= 0000000000000010000000001fffff44000000 + 31880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 31880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x8000153c +After delta: vaddr = 0x8000153c + 31880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:728 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 3188 +instret:729 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 3188 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5a <= 000000002000054f000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003e08, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 31890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h000000008000153c, write: False, capStore: False, potentialCapLoad: False } + 31890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 31890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 61 <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31900 : [doFinishMem] DTlbResp { resp: <'h000000008000153c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h000000008000153c, check_high: 'h00000000080001540, check_inclusive: True } }, specBits: 'h000 } + 31900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h000000008000153c, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 31900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 31900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 31900 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } + 31900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h15, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:730 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 3190 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h4a5, localHist: 'h3ff, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0a <= 0000000020000f70000000001fffff44000000 + 31910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 31910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31910 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 0000000000000000800000001fffff44000000 + 31910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h15, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 31910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h15, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 31910 : [Ld resp] 'h15; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 31910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 31910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:731 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 3191 +instret:732 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 3191 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0d <= 0000000020000f80000000001fffff44000000 + 31920 : [doRespLdMem] 'h15; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000000000064000000001fffff44000000 + 31920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 31920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 31920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 31920 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } } + 31920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003e08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +instret:733 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 3192 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h000000008000153c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 31930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31930 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0e <= 0000000000000000800000001fffff44000000 + 31930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003e08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 31930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080003e08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 31930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 31930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h031 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 31940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 31940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 31940 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } + 31940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31940 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080003e90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:734 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 3194 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h031, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 69 <= 0000000000000000c00000001fffff44000000 + 31950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h030 } + 31950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31950 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 57 <= 0000000000000000800000001fffff44000000 + 31950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080003e90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 31950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 31950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 31950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6f <= 0000000000000000c00000001fffff44000000 + 31960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 31960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 31960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 31960 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 31960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31960 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080003e88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31970 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080003e90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080003e90, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[RFile] wr_ 0: r 4a <= 0000000020000484000000001fffff44000000 + 31970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 31970 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000000800000001fffff44000000 + 31970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080003e88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 31970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 31970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7e <= 000000002000054d000000001fffff44000000 + 31980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 31990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 31990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 31990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 66 <= 0000000000000002000000001fffff44000000 + 32000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 32000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 32000 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } + 32000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x8000153c +After delta: vaddr = 0x8000153c + 32000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5f <= 000000002000054f000000001fffff44000000 +[RFile] wr_ 1: r 5c <= 0000000020001089000000001fffff44000000 + 32010 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4e <= 0000000000000000800000001fffff44000000 + 32010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h000000008000153c, write: False, capStore: False, potentialCapLoad: False } + 32010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 32010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4c <= 0000000020000f30000000001fffff44000000 +[RFile] wr_ 1: r 4b <= 0000000000000010000000001fffff44000000 + 32020 : [doFinishMem] DTlbResp { resp: <'h000000008000153c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h000000008000153c o: 'h000000008000153c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h000000008000153c, check_high: 'h00000000080001540, check_inclusive: True } }, specBits: 'h000 } + 32020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h000000008000153c, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 32020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 32020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 32030 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 32030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 32030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 32030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h000000008000153c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 32030 : [Ld resp] 'h03; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 32030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 32030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6a <= 0000000000000040000000001fffff44000000 + 32040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 32040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32040 : [doRespLdMem] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000064000000001fffff44000000 + 32040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 32040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 32040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 32040 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } + 32040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 41 <= 0000000020000f70000000001fffff44000000 + 32050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 32050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 32050 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 42 <= 0000000000000000c00000001fffff44000000 + 32050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 32050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 32050 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } + 32050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003e10 +After delta: vaddr = 0x80003e10 + 32050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5b <= 0000000020000f80000000001fffff44000000 + 32060 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 02 <= 0000000000000000800000001fffff44000000 + 32060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080003e00 o: 'h0000000080003e00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000190 o: 'h0000000000000190 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003e10 o: 'h0000000080003e10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003e10, write: True, capStore: False, potentialCapLoad: False } + 32060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 32060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 32070 : [doFinishMem] DTlbResp { resp: <'h0000000080003e10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003e10 o: 'h0000000080003e10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003e10, check_high: 'h00000000080003e14, check_inclusive: True } }, specBits: 'h000 } + 32070 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000000c00000001fffff44000000 + 32070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 32070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32080 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 32080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 32080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 51 <= 0000000000000040000000001fffff44000000 + 32090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 32090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 32090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 32090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 32090 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } + 32090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7a <= 0000000020000f70000000001fffff44000000 + 32100 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 0000000000000005000000001fffff44000000 + 32100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 32100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 73 <= 0000000000000018000000001fffff44000000 + 32110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 32110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32110 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6c <= 0000000000000000c00000001fffff44000000 + 32110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003e28 +After delta: vaddr = 0x80003e28 + 32110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'ha52, localHist: 'h007, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 55 <= 0000000020000f88000000001fffff44000000 + 32120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080003e20 o: 'h0000000080003e20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003e28 o: 'h0000000080003e28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003e28, write: True, capStore: False, potentialCapLoad: False } + 32120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 32120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 32120 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } + 32120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32130 : [doFinishMem] DTlbResp { resp: <'h0000000080003e28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003e28 o: 'h0000000080003e28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003e28, check_high: 'h00000000080003e30, check_inclusive: True } }, specBits: 'h000 } + 32130 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000000000000800000001fffff44000000 + 32130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 32130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 68 <= 0000000000000003000000001fffff44000000 +[RFile] wr_ 1: r 72 <= 0000000000000018000000001fffff44000000 +[RFile] wr_ 2: r 7f <= 0000000000000000000000001fffff44000000 + 32140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 32140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001540 +After delta: vaddr = 0x80001540 + 32140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 45 <= 0000000020000550000000001fffff44000000 + 32150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 32150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001540, write: False, capStore: False, potentialCapLoad: False } + 32150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 32150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } +instret:735 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 3215 +instret:736 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 3215 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5e <= 0000000000000040000000001fffff44000000 + 32160 : [doFinishMem] DTlbResp { resp: <'h0000000080001540,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001540, check_high: 'h00000000080001544, check_inclusive: True } }, specBits: 'h000 } + 32160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080001540, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 32160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 32160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 32160 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 32160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003e00 +After delta: vaddr = 0x80003e00 + 32160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:737 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 3216 +instret:738 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 3216 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h529, localHist: 'h3ff, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5d <= 0000000020000f70000000001fffff44000000 + 32170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 32170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 32170 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000000800000001fffff44000000 + 32170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080003e00 o: 'h0000000080003e00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003e00 o: 'h0000000080003e00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003e00, write: True, capStore: False, potentialCapLoad: False } + 32170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 32170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 32170 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } + 32170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:739 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 3217 +instret:740 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 3217 +calling cycle +[RFile] wr_ 0: r 74 <= 0000000020000f88000000001fffff44000000 + 32180 : [doFinishMem] DTlbResp { resp: <'h0000000080003e00,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003e00 o: 'h0000000080003e00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003e00, check_high: 'h00000000080003e08, check_inclusive: True } }, specBits: 'h000 } + 32180 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 54 <= 0000000000000190000000001fffff44000000 + 32180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 32190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 32190 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7b <= 0000000000000000c00000001fffff44000000 + 32190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32190 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:741 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 3219 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003e00, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 32200 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000000000000c00000001fffff44000000 + 32200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 32200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 32200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003e00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 01 <= 0000000000000000c00000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003e00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 32210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003e00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 32210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 32210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:742 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 3221 +instret:743 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 3221 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6e <= 0000000000000001000000001fffff44000000 + 32220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 32220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +instret:744 PC:0x1ffff0000000000000000000080000272 instr:0x02a0006f iType:J [doCommitNormalInst [0]] 3222 +instret:745 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [1]] 3222 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } +[ALU redirect - 0] 'h1ffff0000000000000000000080000204; 'h4; InstTag { way: 'h0, ptr: 'h0f, t: 'h1e } + 32230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 32230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 32230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32230 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080003e80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:746 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [0]] 3223 +instret:747 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [1]] 3223 +calling cycle +[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h0f, t: 'h1e } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080003e80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 32250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +instret:748 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [0]] 3225 +instret:749 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [1]] 3225 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h000000008000153c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 32260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +calling cycle +calling cycle + 32280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 32280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 32280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'ha94, localHist: 'h3fe, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 32350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +calling cycle + 32360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[RFile] wr_ 1: r 69 <= 0000000000000000c00000001fffff44000000 + 32370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 32370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 32380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 32380 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } + 32380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32390 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 57 <= 0000000000000000c00000001fffff44000000 + 32390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +instret:750 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 3241 +instret:751 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 3241 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000204; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } + 32420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 32420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 32440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 32440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 32440 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } + 32440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:752 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 3244 +calling cycle + 32450 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080003e90, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 32450 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle + 32460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32460 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 32460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080003e90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 32460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 32490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000324 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 32500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 32510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 32510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8208 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4a <= 0000000020000484000000001fffff44000000 + 32520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 32520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8208 } + 32520 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 32520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:753 PC:0x1ffff0000000000000000000080000204 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3252 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7e <= 000000002000054d000000001fffff44000000 + 32530 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000000c00000001fffff44000000 + 32530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 32550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 32550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } +instret:754 PC:0x1ffff0000000000000000000080000208 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 3255 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5c <= 0000000020001089000000001fffff44000000 +[RFile] wr_ 1: r 66 <= 0000000000000003000000001fffff44000000 + 32560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 32560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821c } + 32560 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } + 32560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001540 +After delta: vaddr = 0x80001540 + 32560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5f <= 0000000020000550000000001fffff44000000 + 32570 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4e <= 0000000000000000800000001fffff44000000 + 32570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001540, write: False, capStore: False, potentialCapLoad: False } + 32570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 32570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:755 PC:0x1ffff000000000000000000008000020c instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 3257 +instret:756 PC:0x1ffff0000000000000000000080000210 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 3257 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4c <= 0000000020000f30000000001fffff44000000 + 32580 : [doFinishMem] DTlbResp { resp: <'h0000000080001540,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001540, check_high: 'h00000000080001544, check_inclusive: True } }, specBits: 'h000 } + 32580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080001540, shiftedBE: tagged DataMemAccess , pcHash: 'h821a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 32580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 32580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } +instret:757 PC:0x1ffff0000000000000000000080000214 instr:0x32458693 iType:Alu [doCommitNormalInst [0]] 3258 +instret:758 PC:0x1ffff0000000000000000000080000218 instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 3258 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4b <= 0000000000000018000000001fffff44000000 + 32590 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 32590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8234 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 32590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 32590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821a } + 32590 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 32590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 32590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6a <= 0000000000000040000000001fffff44000000 + 32600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 32600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32600 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000190000000001fffff44000000 + 32600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 32600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 32600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8234 } + 32600 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } + 32600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 41 <= 0000000020000f70000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080001540, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 32610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32610 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 42 <= 0000000000000000c00000001fffff44000000 + 32610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 32610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 32610 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } + 32610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003e30 +After delta: vaddr = 0x80003e30 + 32610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5b <= 0000000020000f88000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32620 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 02 <= 0000000000000000800000001fffff44000000 + 32620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080003e20 o: 'h0000000080003e20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000640 o: 'h0000000000000640 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003e30 o: 'h0000000080003e30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003e30, write: True, capStore: False, potentialCapLoad: False } + 32620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 32620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8240 } + 32620 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } + 32620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 32620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32620 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:759 PC:0x1ffff000000000000000000008000021a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 3262 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 32630 : [doFinishMem] DTlbResp { resp: <'h0000000080003e30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003e30 o: 'h0000000080003e30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003e30, check_high: 'h00000000080003e34, check_inclusive: True } }, specBits: 'h000 } + 32630 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000000c00000001fffff44000000 + 32630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 32630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 32630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 32630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:760 PC:0x1ffff000000000000000000008000021c instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 3263 +instret:761 PC:0x1ffff0000000000000000000080000220 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 3263 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32640 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 32640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 32640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } +instret:762 PC:0x1ffff0000000000000000000080000224 instr:0x00004597 iType:Auipc [doCommitNormalInst [0]] 3264 +instret:763 PC:0x1ffff0000000000000000000080000228 instr:0xa9c58593 iType:Alu [doCommitNormalInst [1]] 3264 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 51 <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 32650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 32650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 32650 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } + 32650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 32650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } +instret:764 PC:0x1ffff000000000000000000008000022c instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 3265 +instret:765 PC:0x1ffff000000000000000000008000022e instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 3265 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7a <= 0000000020000f70000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32660 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 0000000000000005000000001fffff44000000 + 32660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 32660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 32660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 32660 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } + 32660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:766 PC:0x1ffff0000000000000000000080000230 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 3266 +instret:767 PC:0x1ffff0000000000000000000080000232 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 3266 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 73 <= 0000000000000018000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003e30, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8232 } + 32670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h825e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32670 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6c <= 0000000000000000c00000001fffff44000000 + 32670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003e28 +After delta: vaddr = 0x80003e28 + 32670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } +instret:768 PC:0x1ffff0000000000000000000080000234 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3267 +instret:769 PC:0x1ffff0000000000000000000080000238 instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 3267 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hd4a, localHist: 'h003, globalTaken: True, localTaken: False, pcIndex: 'h138 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 55 <= 0000000020000f88000000001fffff44000000 + 32680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080003e20 o: 'h0000000080003e20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003e28 o: 'h0000000080003e28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003e28, write: True, capStore: False, potentialCapLoad: False } + 32680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 32680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825e } + 32680 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } + 32680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003e30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +instret:770 PC:0x1ffff000000000000000000008000023c instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 3268 +instret:771 PC:0x1ffff000000000000000000008000023e instr:0x0000962e iType:Alu [doCommitNormalInst [1]] 3268 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000002a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32690 : [doFinishMem] DTlbResp { resp: <'h0000000080003e28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003e28 o: 'h0000000080003e28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003e28, check_high: 'h00000000080003e30, check_inclusive: True } }, specBits: 'h000 } + 32690 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000000000000800000001fffff44000000 + 32690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003e30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } + 32690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003e30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8232 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 32690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 32690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:772 PC:0x1ffff0000000000000000000080000240 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 3269 +instret:773 PC:0x1ffff0000000000000000000080000244 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 3269 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 68 <= 0000000000000003000000001fffff44000000 +[RFile] wr_ 1: r 72 <= 0000000000000018000000001fffff44000000 + 32700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 32700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001540 +After delta: vaddr = 0x80001540 + 32700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:774 PC:0x1ffff0000000000000000000080000246 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 3270 +instret:775 PC:0x1ffff0000000000000000000080000248 instr:0x0000e608 iType:St [doCommitNormalInst [1]] 3270 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 45 <= 0000000020000550000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003e28, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8248 } + 32710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h826c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001540, write: False, capStore: False, potentialCapLoad: False } + 32710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 32710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5e <= 0000000000000040000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32720 : [doFinishMem] DTlbResp { resp: <'h0000000080001540,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001540 o: 'h0000000080001540 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001540, check_high: 'h00000000080001544, check_inclusive: True } }, specBits: 'h000 } + 32720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080001540, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 32720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 32720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826c } + 32720 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 32720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } +instret:776 PC:0x1ffff000000000000000000008000024a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 3272 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h6a5, localHist: 'h3ff, globalTaken: True, localTaken: False, pcIndex: 'h0ff }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5d <= 0000000020000f70000000001fffff44000000 + 32730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h007 } + 32730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h82a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32730 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000000800000001fffff44000000 + 32730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 32730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080001540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 32730 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } + 32730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 32730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:777 PC:0x1ffff000000000000000000008000024e instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 3273 +instret:778 PC:0x1ffff0000000000000000000080000252 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 3273 +calling cycle +[RFile] wr_ 0: r 74 <= 0000000020000f88000000001fffff44000000 + 32740 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 54 <= 0000000000000190000000001fffff44000000 + 32740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 32740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 32740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 32740 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } + 32740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003e28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +instret:779 PC:0x1ffff0000000000000000000080000256 instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 3274 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080001540, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h009 } + 32750 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7b <= 0000000000000000c00000001fffff44000000 + 32750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003e28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } + 32750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080003e28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8248 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 32750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 32760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:780 PC:0x1ffff0000000000000000000080000258 instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 3276 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 01 <= 0000000000000000c00000001fffff44000000 + 32770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 32770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6e <= 0000000000000001000000001fffff44000000 + 32780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 32780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 32790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 32790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h352, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 32800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h010 } + 32800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h011 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 32800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h013, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h011 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 32810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 32810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 32810 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } + 32810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7f <= 0000000000000000800000001fffff44000000 + 32820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h010 } + 32820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 32820 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 05 <= 0000000000000000800000001fffff44000000 + 32820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 32820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 32830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 32830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 32830 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 32830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 32830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h1a9, localHist: 'h2aa, globalTaken: True, localTaken: True, pcIndex: 'h169 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6b <= 0000000000000000000000001fffff44000000 + 32840 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000000800000001fffff44000000 + 32840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: True, capStore: False, potentialCapLoad: False } + 32840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 32840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 40 <= 0000000000000000c00000001fffff44000000 + 32850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h012 } + 32850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: True, capStore: False, potentialCapLoad: False } + 32850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01a } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 32850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 32860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h010 } + 32860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01a } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 32860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03b } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff9dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 44 <= 0000000000000000c00000001fffff44000000 +[ALU redirect - 0] 'h1ffff00000000000000000000800001e8; 'h1; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } + 32870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h012 } + 32870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 32870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h033 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[ROB incorrectSpec] 'h1 ; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 32890 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +[RFile] wr_ 2: r 60 <= 0000000000000000000000001fffff44000000 +calling cycle + 32970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:781 PC:0x1ffff000000000000000000008000025a instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 3297 +instret:782 PC:0x1ffff000000000000000000008000025e instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 3297 +calling cycle + 32980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003e20 +After delta: vaddr = 0x80003e20 +instret:783 PC:0x1ffff0000000000000000000080000262 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 3298 +instret:784 PC:0x1ffff0000000000000000000080000264 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 3298 +calling cycle + 32990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080003e20 o: 'h0000000080003e20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003e20 o: 'h0000000080003e20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003e20, write: True, capStore: False, potentialCapLoad: False } +instret:785 PC:0x1ffff0000000000000000000080000266 instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 3299 +instret:786 PC:0x1ffff0000000000000000000080000268 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 3299 +calling cycle + 33000 : [doFinishMem] DTlbResp { resp: <'h0000000080003e20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003e20 o: 'h0000000080003e20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003e20, check_high: 'h00000000080003e28, check_inclusive: True } }, specBits: 'h000 } +calling cycle +instret:787 PC:0x1ffff000000000000000000008000026a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 3301 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003e20, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826a } + 33020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003e20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003e20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } + 33030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080003e20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:788 PC:0x1ffff000000000000000000008000026c instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 3303 +instret:789 PC:0x1ffff0000000000000000000080000270 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 3303 +calling cycle +instret:790 PC:0x1ffff0000000000000000000080000272 instr:0x02a0006f iType:J [doCommitNormalInst [0]] 3304 +instret:791 PC:0x1ffff000000000000000000008000029c instr:0x0040006f iType:J [doCommitNormalInst [1]] 3304 +calling cycle +instret:792 PC:0x1ffff00000000000000000000800002a0 instr:0xfc842503 iType:Ld [doCommitNormalInst [0]] 3305 +instret:793 PC:0x1ffff00000000000000000000800002a4 instr:0x00002505 iType:Alu [doCommitNormalInst [1]] 3305 +calling cycle +instret:794 PC:0x1ffff00000000000000000000800002a6 instr:0xfca42423 iType:St [doCommitNormalInst [0]] 3306 +instret:795 PC:0x1ffff00000000000000000000800002aa instr:0xf4dff06f iType:J [doCommitNormalInst [1]] 3306 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a6 } + 33070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +calling cycle + 33080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } + 33080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 33090 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } +calling cycle + 33100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 33100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f6 } + 33100 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 33100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 33110 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000000000001000000001fffff44000000 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:796 PC:0x1ffff00000000000000000000800001f6 instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 3313 +instret:797 PC:0x1ffff00000000000000000000800001fa instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 3313 +calling cycle +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } +instret:798 PC:0x1ffff00000000000000000000800001fc instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 3315 +instret:799 PC:0x1ffff0000000000000000000080000200 instr:0x0ae0006f iType:J [doCommitNormalInst [1]] 3315 +calling cycle +instret:800 PC:0x1ffff00000000000000000000800002ae instr:0x0040006f iType:J [doCommitNormalInst [0]] 3316 +instret:801 PC:0x1ffff00000000000000000000800002b2 instr:0xfcc42503 iType:Ld [doCommitNormalInst [1]] 3316 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +instret:802 PC:0x1ffff00000000000000000000800002b6 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 3317 +instret:803 PC:0x1ffff00000000000000000000800002b8 instr:0xfca42623 iType:St [doCommitNormalInst [1]] 3317 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82b8 } + 33180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } +instret:804 PC:0x1ffff00000000000000000000800002bc instr:0xf1fff06f iType:J [doCommitNormalInst [0]] 3318 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } + 33190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 33190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h9a9, localHist: 'h3ff, globalTaken: True, localTaken: False, pcIndex: 'h0fe }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6b <= 0000000000000000000000001fffff44000000 + 33200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 33200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 33210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 44 <= 0000000000000000c00000001fffff44000000 + 33220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 33220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 33230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff1e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 33240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h4d4, localHist: 'h3fa, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 33250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h82b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 33250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } +calling cycle +calling cycle + 33270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 33270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b2 } + 33270 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } + 33270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 33280 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h26a, localHist: 'h3fa, globalTaken: True, localTaken: False, pcIndex: 'h0f0 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 33340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7f <= 0000000000000000800000001fffff44000000 + 33360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 33360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 33370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81da } + 33370 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 33370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 33370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h135, localHist: 'h2aa, globalTaken: True, localTaken: True, pcIndex: 'h169 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6b <= 0000000000000000000000001fffff44000000 + 33380 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000000c00000001fffff44000000 + 33380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: True, capStore: False, potentialCapLoad: False } + 33380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h001 } + 33390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 33390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 44 <= 0000000000000000c00000001fffff44000000 + 33400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h001 } + 33400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 33400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 +instret:805 PC:0x1ffff00000000000000000000800001da instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 3340 +instret:806 PC:0x1ffff00000000000000000000800001de instr:0x00004509 iType:Alu [doCommitNormalInst [1]] 3340 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff9dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 33410 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000000000000001fffff44000000 + 33410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h018 } + 33420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 33420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:807 PC:0x1ffff00000000000000000000800001e0 instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 3342 +instret:808 PC:0x1ffff00000000000000000000800001e4 instr:0x0dc0006f iType:J [doCommitNormalInst [1]] 3342 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000036 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h018, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 47 <= 00000000200010b9000000001fffff44000000 + 33430 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 67 <= 0000000000000000000000001fffff44000000 + 33430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 +instret:809 PC:0x1ffff00000000000000000000800002c0 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 3343 +instret:810 PC:0x1ffff00000000000000000000800002c2 instr:0xfca42223 iType:St [doCommitNormalInst [1]] 3343 +calling cycle +[RFile] wr_ 0: r 69 <= 0000000020000f30000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82c2 } + 33440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } + 33440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82c2 } +instret:811 PC:0x1ffff00000000000000000000800002c6 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3344 +instret:812 PC:0x1ffff00000000000000000000800002ca instr:0xfc442583 iType:Ld [doCommitNormalInst [1]] 3344 +calling cycle +[RFile] wr_ 0: r 66 <= 00000000200000bc800000001fffff44000000 + 33450 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 33450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h82ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82c2 } + 33450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82c2 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } +instret:813 PC:0x1ffff00000000000000000000800002ce instr:0x0000450d iType:Alu [doCommitNormalInst [0]] 3345 +instret:814 PC:0x1ffff00000000000000000000800002d0 instr:0x00b55463 iType:Br [doCommitNormalInst [1]] 3345 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffe1c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 49 <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 5f <= 00000000200000be800000001fffff44000000 +[ALU redirect - 1] 'h1ffff0000000000000000000080000328; 'h0; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } + 33460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 33460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 33460 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } + 33460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:815 PC:0x1ffff00000000000000000000800002d8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3346 +instret:816 PC:0x1ffff00000000000000000000800002dc instr:0xfc442503 iType:Ld [doCommitNormalInst [1]] 3346 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +[RFile] wr_ 1: r 57 <= 0000000020000f30000000001fffff44000000 + 33480 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 61 <= 0000000000000000000000001fffff44000000 +instret:817 PC:0x1ffff00000000000000000000800002e0 instr:0x00551593 iType:Alu [doCommitNormalInst [0]] 3348 +instret:818 PC:0x1ffff00000000000000000000800002e4 instr:0x00004517 iType:Auipc [doCommitNormalInst [1]] 3348 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } +instret:819 PC:0x1ffff00000000000000000000800002e8 instr:0x9dc50513 iType:Alu [doCommitNormalInst [0]] 3349 +instret:820 PC:0x1ffff00000000000000000000800002ec instr:0x0000952e iType:Alu [doCommitNormalInst [1]] 3349 +calling cycle +instret:821 PC:0x1ffff00000000000000000000800002ee instr:0xfd04258f iType:Ld [doCommitNormalInst [0]] 3350 +instret:822 PC:0x1ffff00000000000000000000800002f2 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 3350 +calling cycle +instret:823 PC:0x1ffff00000000000000000000800002f6 instr:0x036080e7 iType:Jr [doCommitNormalInst [0]] 3351 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 33540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4a <= 00000000200003cc000000001fffff44000000 + 33550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800002fa o: 'h00000000800002fa b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 33550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 33550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5c <= 00000000200003e4000000001fffff44000000 + 33560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 33560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 33560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 33560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:824 PC:0x1ffff0000000000000000000080000328 instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 3356 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 33570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 33570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 33570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 33570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:825 PC:0x1ffff000000000000000000008000032a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 3357 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 33580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h832a } + 33580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 33580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 33580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +instret:826 PC:0x1ffff000000000000000000008000032c instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 3358 +instret:827 PC:0x1ffff000000000000000000008000032e instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 3358 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 33590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 33590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } + 33590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:828 PC:0x1ffff0000000000000000000080000330 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 3359 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 33600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h832c } + 33600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8338 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 33600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 33600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } +instret:829 PC:0x1ffff0000000000000000000080000334 instr:0xfcb44823 iType:St [doCommitNormalInst [0]] 3360 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 33610 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 41 <= 0000000020000f30000000001fffff44000000 + 33610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 33610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } + 33610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8330 } + 33620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8342 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 33620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cc0 +After delta: vaddr = 0x80003cc0 + 33620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 33630 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000020000f30000000001fffff44000000 + 33630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cc0, write: False, capStore: False, potentialCapLoad: False } + 33630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 33630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 33630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:830 PC:0x1ffff0000000000000000000080000338 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3363 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 33640 : [doFinishMem] DTlbResp { resp: <'h0000000080003cc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cc0, check_high: 'h00000000080003cc8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8334 } + 33640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080003cc0, shiftedBE: tagged DataMemAccess , pcHash: 'h833c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 33640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cc8 +After delta: vaddr = 0x80003cc8 + 33640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080003cc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 33650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h834c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cc8 o: 'h0000000080003cc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cc8, write: False, capStore: False, potentialCapLoad: False } + 33650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080003cc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 33650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080003cc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 33650 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } + 33650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33660 : [doFinishMem] DTlbResp { resp: <'h0000000080003cc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cc8 o: 'h0000000080003cc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cc8, check_high: 'h00000000080003cd0, check_inclusive: True } }, specBits: 'h000 } + 33660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080003cc8, shiftedBE: tagged DataMemAccess , pcHash: 'h8346 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33660 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 0000000000000000000000001fffff44000000 + 33660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } + 33660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h834c } + 33660 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } + 33660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 33660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080003cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h89a, localHist: 'h02a, globalTaken: True, localTaken: False, pcIndex: 'h1b4 }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 56 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080003cc0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33670 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4b <= 0000000020000f30000000001fffff44000000 + 33670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } + 33670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080003cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 33670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080003cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 33670 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } + 33670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 33670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0e, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000018e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 33680 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 02 <= 0000000000000000c00000001fffff44000000 + 33680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 33680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } + 33680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cd0 +After delta: vaddr = 0x80003cd0 + 33680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:831 PC:0x1ffff000000000000000000008000033c instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 3368 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 33690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cd0 o: 'h0000000080003cd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cd0, write: False, capStore: False, potentialCapLoad: False } + 33690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 33690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 33700 : [doFinishMem] DTlbResp { resp: <'h0000000080003cd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cd0 o: 'h0000000080003cd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cd0, check_high: 'h00000000080003cd4, check_inclusive: True } }, specBits: 'h000 } + 33700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080003cd0, shiftedBE: tagged DataMemAccess , pcHash: 'h8350 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } + 33700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 33700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080003cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } +instret:832 PC:0x1ffff000000000000000000008000033e instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3370 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h833e } + 33710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 33710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080003cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } + 33710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080003cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } + 33710 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } + 33710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 33710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } +calling cycle +[RFile] wr_ 1: r 4c <= 00000000200003e4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080003cc8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 33720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8360 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 33720 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000006400000001fffff44000000 + 33720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 33720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } + 33720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 33720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:833 PC:0x1ffff0000000000000000000080000342 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3372 +calling cycle + 33730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 33730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8364 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33730 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000000000000000000000001fffff44000000 + 33730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 33730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffbc, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f4c +After delta: vaddr = 0x80000f4c + 33730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8364 } +instret:834 PC:0x1ffff0000000000000000000080000346 instr:0x00006508 iType:Ld [doCommitNormalInst [0]] 3373 +instret:835 PC:0x1ffff0000000000000000000080000348 instr:0xfca43023 iType:St [doCommitNormalInst [1]] 3373 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8348 } + 33740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h84fa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffbc, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000019 o: 'h0000000000000019 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } + 33740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8364 } + 33740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8364 } + 33740 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } + 33740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 33740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080003cd0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 33750 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7e <= 0000000000000000000000001fffff44000000 + 33750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + 33750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fa } + 33750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fa } + 33750 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } + 33750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } +instret:836 PC:0x1ffff000000000000000000008000034c instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3375 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h03, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h002 } + 33760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h84fc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33760 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 54 <= 00000000200000be800000001fffff44000000 + 33760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } + 33760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fc } +instret:837 PC:0x1ffff0000000000000000000080000350 instr:0x00004908 iType:Ld [doCommitNormalInst [0]] 3376 +instret:838 PC:0x1ffff0000000000000000000080000352 instr:0xfaa42e23 iType:St [doCommitNormalInst [1]] 3376 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8352 } + 33770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fc } + 33770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fc } + 33770 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } + 33770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } +instret:839 PC:0x1ffff0000000000000000000080000356 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 3377 +instret:840 PC:0x1ffff0000000000000000000080000358 instr:0xfaa42c23 iType:St [doCommitNormalInst [1]] 3377 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33780 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 00000000200003f4000000001fffff44000000 + 33780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } + 33780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:841 PC:0x1ffff000000000000000000008000035c instr:0x0040006f iType:J [doCommitNormalInst [0]] 3378 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8358 } + 33790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 33790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } +instret:842 PC:0x1ffff0000000000000000000080000360 instr:0xfb842503 iType:Ld [doCommitNormalInst [0]] 3379 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 33800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } + 33800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:843 PC:0x1ffff0000000000000000000080000364 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 3380 +instret:844 PC:0x1ffff0000000000000000000080000368 instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 3380 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h44d, localHist: 'h2aa, globalTaken: True, localTaken: True, pcIndex: 'h168 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 33810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82fe } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 33810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } +instret:845 PC:0x1ffff000000000000000000008000036c instr:0x18e0006f iType:J [doCommitNormalInst [0]] 3381 +instret:846 PC:0x1ffff00000000000000000000800004fa instr:0x000060e6 iType:Ld [doCommitNormalInst [1]] 3381 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 33820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 33820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 33820 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } + 33820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:847 PC:0x1ffff00000000000000000000800004fc instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 3382 +instret:848 PC:0x1ffff00000000000000000000800004fe instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 3382 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6d <= 0000000000000000c00000001fffff44000000 + 33830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 33830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33830 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000000000000000000001fffff44000000 + 33830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 33830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } +instret:849 PC:0x1ffff0000000000000000000080000500 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 3383 +instret:850 PC:0x1ffff00000000000000000000800002fa instr:0x0040006f iType:J [doCommitNormalInst [1]] 3383 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff9dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 33840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 33840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 33840 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 33840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } + 33850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33850 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000000000000001fffff44000000 + 33850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 33850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } +instret:851 PC:0x1ffff00000000000000000000800002fe instr:0xfc442503 iType:Ld [doCommitNormalInst [0]] 3385 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000036 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6e <= 00000000200010b9000000001fffff44000000 +[RFile] wr_ 1: r 60 <= 0000000000000000400000001fffff44000000 + 33860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: True, capStore: False, potentialCapLoad: False } + 33860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 33860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 33860 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } + 33860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5a <= 0000000020000f30000000001fffff44000000 + 33870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 33870 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 0000000000000000000000001fffff44000000 + 33870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } + 33870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:852 PC:0x1ffff0000000000000000000080000302 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 3387 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 01 <= 00000000200000bc800000001fffff44000000 + 33880 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h001 } + 33880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h82ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 33880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } +instret:853 PC:0x1ffff0000000000000000000080000304 instr:0xfca42223 iType:St [doCommitNormalInst [0]] 3388 +instret:854 PC:0x1ffff0000000000000000000080000308 instr:0xfc3ff06f iType:J [doCommitNormalInst [1]] 3388 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 71 <= 00000000200003cc000000001fffff44000000 +[RFile] wr_ 1: r 05 <= 00000000200000be800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8304 } + 33890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800002fa o: 'h00000000800002fa b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 33890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 33890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 33890 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 33890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 33890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 74 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 33900 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000000000000000000001fffff44000000 + 33900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 33900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } + 33900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 33900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 33900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 40 <= 00000000200003e4000000001fffff44000000 +[RFile] wr_ 1: r 76 <= 0000000020000f30000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 33910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 33910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 33910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 33910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 33920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 33920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 33920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 33930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 33930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 33940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8338 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 33940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 33950 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000020000f30000000001fffff44000000 + 33950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 33950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 33960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 33960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cc0 +After delta: vaddr = 0x80003cc0 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 33970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 33970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8342 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 33970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cc0, write: False, capStore: False, potentialCapLoad: False } + 33970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 33980 : [doFinishMem] DTlbResp { resp: <'h0000000080003cc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cc0, check_high: 'h00000000080003cc8, check_inclusive: True } }, specBits: 'h000 } + 33980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080003cc0, shiftedBE: tagged DataMemAccess , pcHash: 'h833c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 33980 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000020000f30000000001fffff44000000 + 33980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 33980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 33980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080003cc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 33990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 33990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080003cc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 33990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080003cc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 33990 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } + 33990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cc8 +After delta: vaddr = 0x80003cc8 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 34000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h834c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34000 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 0000000000000000000000001fffff44000000 + 34000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cc8 o: 'h0000000080003cc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cc8, write: False, capStore: False, potentialCapLoad: False } + 34000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080003cc0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34010 : [doFinishMem] DTlbResp { resp: <'h0000000080003cc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cc8 o: 'h0000000080003cc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cc8, check_high: 'h00000000080003cd0, check_inclusive: True } }, specBits: 'h000 } + 34010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080003cc8, shiftedBE: tagged DataMemAccess , pcHash: 'h8346 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34010 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6f <= 0000000020000f30000000001fffff44000000 + 34010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 34010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080003cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'ha26, localHist: 'h015, globalTaken: True, localTaken: False, pcIndex: 'h1b4 }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 67 <= 0000000000000000000000001fffff44000000 + 34020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 34020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080003cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 34020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080003cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 34020 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } + 34020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cd0 +After delta: vaddr = 0x80003cd0 + 34020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0e, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000018e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 34030 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6b <= 0000000000000000c00000001fffff44000000 + 34030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080003cc0 o: 'h0000000080003cc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cd0 o: 'h0000000080003cd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cd0, write: False, capStore: False, potentialCapLoad: False } + 34030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 34030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34040 : [doFinishMem] DTlbResp { resp: <'h0000000080003cd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cd0 o: 'h0000000080003cd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cd0, check_high: 'h00000000080003cd4, check_inclusive: True } }, specBits: 'h000 } + 34040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080003cd0, shiftedBE: tagged DataMemAccess , pcHash: 'h8350 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } + 34040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 34040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080003cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 34050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } + 34050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080003cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } + 34050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080003cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } + 34050 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 34050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 34050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080003cc8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } + 34060 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000000000006400000001fffff44000000 + 34060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 34060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 34060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 00000000200003e4000000001fffff44000000 + 34070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 34070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8360 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 34070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffbc, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f4c +After delta: vaddr = 0x80000f4c + 34070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h03, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 34080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8364 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34080 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 0000000000000000000000001fffff44000000 + 34080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffbc, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000019 o: 'h0000000000000019 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } + 34080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 34080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h513, localHist: 'h355, globalTaken: True, localTaken: True, pcIndex: 'h169 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080003cd0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 34090 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0b <= 0000000000000000000000001fffff44000000 + 34090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 34090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 34100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } + 34100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h84fa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h002 } + 34110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h84fc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34110 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 00000000200000be800000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff9dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34120 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4e <= 00000000200003f4000000001fffff44000000 + 34120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h033, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h033, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 51 <= 0000000000000000c00000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000036 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h031, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h033, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h011, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 42 <= 00000000200010b9000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 34150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82fe } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 55 <= 0000000020000f30000000001fffff44000000 + 34160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 34160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 34160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 34160 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } + 34160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 34160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 45 <= 00000000200000bc800000001fffff44000000 +[RFile] wr_ 1: r 5f <= 00000000200003cc000000001fffff44000000 + 34170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h010 } + 34170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34170 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 57 <= 0000000000000000400000001fffff44000000 + 34170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } + 34170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 34170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 34170 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 34170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h012 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 34170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 64 <= 00000000200000be800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34180 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h010 } + 34180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h82ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34180 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000000000000400000001fffff44000000 + 34180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800002fa o: 'h00000000800002fa b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 34180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 34180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 34180 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 34180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h012 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 34180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6c <= 00000000200003e4000000001fffff44000000 + 34190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h010 } + 34190 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 0000000000000000400000001fffff44000000 + 34190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 34190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 34190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 34190 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } + 34190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 41 <= 0000000000000000800000001fffff44000000 + 34200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h010 } + 34200 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 61 <= 0000000000000000000000001fffff44000000 + 34200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: True, capStore: False, potentialCapLoad: False } + 34200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 34200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 34210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 34210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 34210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 34210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'ha89, localHist: 'h355, globalTaken: True, localTaken: True, pcIndex: 'h168 }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 34310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6d <= 0000000000000000c00000001fffff44000000 + 34330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 34330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff9dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 34340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 34340 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 34340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } + 34350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34350 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000000400000001fffff44000000 + 34350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000036 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6e <= 00000000200010b9000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 34360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 34360 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } + 34360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5a <= 0000000020000f30000000001fffff44000000 + 34370 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 0000000000000000400000001fffff44000000 + 34370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } + 34370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:855 PC:0x1ffff00000000000000000000800002ca instr:0xfc442583 iType:Ld [doCommitNormalInst [0]] 3437 +instret:856 PC:0x1ffff00000000000000000000800002ce instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 3437 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 01 <= 00000000200000bc800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34380 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h001 } + 34380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h82ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 34380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 71 <= 00000000200003cc000000001fffff44000000 +[RFile] wr_ 1: r 05 <= 00000000200000be800000001fffff44000000 + 34390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800002fa o: 'h00000000800002fa b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 34390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 34390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 34390 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 34390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 34390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:857 PC:0x1ffff00000000000000000000800002d0 instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 3439 +instret:858 PC:0x1ffff00000000000000000000800002d8 instr:0x0040006f iType:J [doCommitNormalInst [1]] 3439 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 74 <= 0000000000000008000000001fffff44000000 + 34400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 34400 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000000000000000000001fffff44000000 + 34400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 34400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 34400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:859 PC:0x1ffff00000000000000000000800002dc instr:0xfc442503 iType:Ld [doCommitNormalInst [0]] 3440 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 76 <= 0000000020000f38000000001fffff44000000 +[RFile] wr_ 1: r 40 <= 00000000200003e4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 34410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 34410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 34410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 34410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:860 PC:0x1ffff00000000000000000000800002e0 instr:0x00551593 iType:Alu [doCommitNormalInst [0]] 3441 +instret:861 PC:0x1ffff00000000000000000000800002e4 instr:0x00004517 iType:Auipc [doCommitNormalInst [1]] 3441 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 34420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 34420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 34420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +instret:862 PC:0x1ffff00000000000000000000800002e8 instr:0x9dc50513 iType:Alu [doCommitNormalInst [0]] 3442 +instret:863 PC:0x1ffff00000000000000000000800002ec instr:0x0000952e iType:Alu [doCommitNormalInst [1]] 3442 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 34430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 34430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +instret:864 PC:0x1ffff00000000000000000000800002ee instr:0xfd04258f iType:Ld [doCommitNormalInst [0]] 3443 +instret:865 PC:0x1ffff00000000000000000000800002f2 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 3443 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 34440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8338 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:866 PC:0x1ffff00000000000000000000800002f6 instr:0x036080e7 iType:Jr [doCommitNormalInst [0]] 3444 +instret:867 PC:0x1ffff0000000000000000000080000328 instr:0x0000711d iType:Alu [doCommitNormalInst [1]] 3444 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 34450 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000020000f38000000001fffff44000000 + 34450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 34450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:868 PC:0x1ffff000000000000000000008000032a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 3445 +instret:869 PC:0x1ffff000000000000000000008000032c instr:0x0000e8a2 iType:St [doCommitNormalInst [1]] 3445 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h832a } + 34460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 34460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ce0 +After delta: vaddr = 0x80003ce0 + 34460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +instret:870 PC:0x1ffff000000000000000000008000032e instr:0x00001080 iType:Alu [doCommitNormalInst [0]] 3446 +instret:871 PC:0x1ffff0000000000000000000080000330 instr:0xfea43423 iType:St [doCommitNormalInst [1]] 3446 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 34470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8342 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ce0, write: False, capStore: False, potentialCapLoad: False } + 34470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } + 34470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 34470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:872 PC:0x1ffff0000000000000000000080000334 instr:0xfcb44823 iType:St [doCommitNormalInst [0]] 3447 +instret:873 PC:0x1ffff0000000000000000000080000338 instr:0xfe843503 iType:Ld [doCommitNormalInst [1]] 3447 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 34480 : [doFinishMem] DTlbResp { resp: <'h0000000080003ce0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ce0, check_high: 'h00000000080003ce8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h832c } + 34480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080003ce0, shiftedBE: tagged DataMemAccess , pcHash: 'h833c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34480 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000020000f38000000001fffff44000000 + 34480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 34480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080003ce0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 34490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 34490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080003ce0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 34490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080003ce0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 34490 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } + 34490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ce8 +After delta: vaddr = 0x80003ce8 + 34490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 34500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h834c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34500 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 0000000000000000000000001fffff44000000 + 34500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ce8 o: 'h0000000080003ce8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ce8, write: False, capStore: False, potentialCapLoad: False } + 34500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } + 34500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 34500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080003ce0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34510 : [doFinishMem] DTlbResp { resp: <'h0000000080003ce8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ce8 o: 'h0000000080003ce8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ce8, check_high: 'h00000000080003cf0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8330 } + 34510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080003ce8, shiftedBE: tagged DataMemAccess , pcHash: 'h8346 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34510 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6f <= 0000000020000f38000000001fffff44000000 + 34510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 34510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080003ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hd44, localHist: 'h00a, globalTaken: True, localTaken: False, pcIndex: 'h1b4 }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 67 <= 0000000000000000000000001fffff44000000 + 34520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 34520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080003ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 34520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080003ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 34520 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } + 34520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cf0 +After delta: vaddr = 0x80003cf0 + 34520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } +instret:874 PC:0x1ffff000000000000000000008000033c instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 3452 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0e, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000018e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 34530 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6b <= 0000000000000000c00000001fffff44000000 + 34530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cf0 o: 'h0000000080003cf0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cf0, write: False, capStore: False, potentialCapLoad: False } + 34530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 34530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 34530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 34530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34540 : [doFinishMem] DTlbResp { resp: <'h0000000080003cf0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cf0 o: 'h0000000080003cf0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cf0, check_high: 'h00000000080003cf4, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8334 } + 34540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080003cf0, shiftedBE: tagged DataMemAccess , pcHash: 'h8350 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } + 34540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 34540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080003cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } +instret:875 PC:0x1ffff000000000000000000008000033e instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3454 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 34550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } + 34550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080003cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } + 34550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080003cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } + 34550 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 34550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 34550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080003ce8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } + 34560 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000000000019000000001fffff44000000 + 34560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 34560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } + 34560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 34560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 34560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:876 PC:0x1ffff0000000000000000000080000342 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3456 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 00000000200003e4000000001fffff44000000 + 34570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h833e } + 34570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8360 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 34570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffbc, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f4c +After delta: vaddr = 0x80000f4c + 34570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } +instret:877 PC:0x1ffff0000000000000000000080000346 instr:0x00006508 iType:Ld [doCommitNormalInst [0]] 3457 +instret:878 PC:0x1ffff0000000000000000000080000348 instr:0xfca43023 iType:St [doCommitNormalInst [1]] 3457 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h03, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 34580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8364 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34580 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 0000000000000000000000001fffff44000000 + 34580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffbc, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000064 o: 'h0000000000000064 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } + 34580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } + 34580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 34580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 34580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h6a2, localHist: 'h3aa, globalTaken: True, localTaken: True, pcIndex: 'h169 }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080003cf0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8348 } + 34590 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0b <= 0000000000000000000000001fffff44000000 + 34590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 34590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 34590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } +instret:879 PC:0x1ffff000000000000000000008000034c instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3459 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 34600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } + 34600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h84fa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + 34600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } + 34600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 34600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fa } +instret:880 PC:0x1ffff0000000000000000000080000350 instr:0x00004908 iType:Ld [doCommitNormalInst [0]] 3460 +instret:881 PC:0x1ffff0000000000000000000080000352 instr:0xfaa42e23 iType:St [doCommitNormalInst [1]] 3460 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8352 } + 34610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h84fc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fa } + 34610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fa } + 34610 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 34610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fc } +instret:882 PC:0x1ffff0000000000000000000080000356 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 3461 +instret:883 PC:0x1ffff0000000000000000000080000358 instr:0xfaa42c23 iType:St [doCommitNormalInst [1]] 3461 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff9dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34620 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 00000000200000be800000001fffff44000000 + 34620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fc } + 34620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fc } + 34620 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } + 34620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } +instret:884 PC:0x1ffff000000000000000000008000035c instr:0x0040006f iType:J [doCommitNormalInst [0]] 3462 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h033, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h033, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 51 <= 0000000000000000c00000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34630 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4e <= 00000000200003f4000000001fffff44000000 + 34630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } + 34630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 34630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:885 PC:0x1ffff0000000000000000000080000360 instr:0xfb842503 iType:Ld [doCommitNormalInst [0]] 3463 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000036 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h031, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h033, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 42 <= 00000000200010b9000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8358 } + 34640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } +instret:886 PC:0x1ffff0000000000000000000080000364 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 3464 +instret:887 PC:0x1ffff0000000000000000000080000368 instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 3464 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 55 <= 0000000020000f30000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } + 34650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 34650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h011, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:888 PC:0x1ffff000000000000000000008000036c instr:0x18e0006f iType:J [doCommitNormalInst [0]] 3465 +instret:889 PC:0x1ffff00000000000000000000800004fa instr:0x000060e6 iType:Ld [doCommitNormalInst [1]] 3465 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 45 <= 00000000200000bc800000001fffff44000000 + 34660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 34660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82fe } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } +instret:890 PC:0x1ffff00000000000000000000800004fc instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 3466 +instret:891 PC:0x1ffff00000000000000000000800004fe instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 3466 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 64 <= 00000000200000be800000001fffff44000000 +[RFile] wr_ 1: r 5f <= 00000000200003cc000000001fffff44000000 + 34670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 34670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 34670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 34670 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } + 34670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 34670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } +instret:892 PC:0x1ffff0000000000000000000080000500 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 3467 +instret:893 PC:0x1ffff00000000000000000000800002fa instr:0x0040006f iType:J [doCommitNormalInst [1]] 3467 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 34680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h010 } + 34680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34680 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 57 <= 0000000000000000400000001fffff44000000 + 34680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } + 34680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 34680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 34680 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 34680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 34680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6c <= 00000000200003e4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34690 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h010 } + 34690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h82ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34690 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000000000000400000001fffff44000000 + 34690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800002fa o: 'h00000000800002fa b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 34690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 34690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 34690 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 34690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 34690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 34700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h010 } + 34700 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 0000000000000000400000001fffff44000000 + 34700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 34700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 34700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 34700 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } + 34700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:894 PC:0x1ffff00000000000000000000800002fe instr:0xfc442503 iType:Ld [doCommitNormalInst [0]] 3470 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 41 <= 0000000000000000800000001fffff44000000 + 34710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h010 } + 34710 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 61 <= 0000000000000000000000001fffff44000000 + 34710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: True, capStore: False, potentialCapLoad: False } + 34710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 34710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 34720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 34720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 34720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:895 PC:0x1ffff0000000000000000000080000302 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 3472 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 75 <= 0000000000000008000000001fffff44000000 + 34730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 34730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8338 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 34730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 34730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8338 } +instret:896 PC:0x1ffff0000000000000000000080000304 instr:0xfca42223 iType:St [doCommitNormalInst [0]] 3473 +instret:897 PC:0x1ffff0000000000000000000080000308 instr:0xfc3ff06f iType:J [doCommitNormalInst [1]] 3473 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 56 <= 0000000020000f38000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 34740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8304 } + 34740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 34740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8338 } + 34740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8338 } + 34740 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } + 34740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 34740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 34750 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000020000f38000000001fffff44000000 + 34750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 34750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } + 34750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 34750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 34760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 34760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8342 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ce0 +After delta: vaddr = 0x80003ce0 + 34760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 34770 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7e <= 0000000020000f38000000001fffff44000000 + 34770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ce0, write: False, capStore: False, potentialCapLoad: False } + 34770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 34770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34780 : [doFinishMem] DTlbResp { resp: <'h0000000080003ce0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ce0, check_high: 'h00000000080003ce8, check_inclusive: True } }, specBits: 'h000 } + 34780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080003ce0, shiftedBE: tagged DataMemAccess , pcHash: 'h833c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 34780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003ce8 +After delta: vaddr = 0x80003ce8 + 34780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080003ce0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 34790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 34790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h834c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003ce8 o: 'h0000000080003ce8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003ce8, write: False, capStore: False, potentialCapLoad: False } + 34790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080003ce0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 34790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080003ce0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 34790 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } + 34790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 34790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hb51, localHist: 'h005, globalTaken: True, localTaken: False, pcIndex: 'h1b4 }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 58 <= 0000000000000000000000001fffff44000000 + 34800 : [doFinishMem] DTlbResp { resp: <'h0000000080003ce8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003ce8 o: 'h0000000080003ce8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003ce8, check_high: 'h00000000080003cf0, check_inclusive: True } }, specBits: 'h000 } + 34800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080003ce8, shiftedBE: tagged DataMemAccess , pcHash: 'h8346 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34800 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 65 <= 0000000000000000000000001fffff44000000 + 34800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } + 34800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 34800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080003ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0e, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000018e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 34810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 34810 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 0000000020000f38000000001fffff44000000 + 34810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 34810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080003ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 34810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080003ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 34810 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } + 34810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 34810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080003ce0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 34820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8360 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34820 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 60 <= 0000000000000000c00000001fffff44000000 + 34820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 34820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003cf0 +After delta: vaddr = 0x80003cf0 + 34820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 34830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 34830 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000000000000000000001fffff44000000 + 34830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080003ce0 o: 'h0000000080003ce0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003cf0 o: 'h0000000080003cf0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003cf0, write: False, capStore: False, potentialCapLoad: False } + 34830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 34830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 34840 : [doFinishMem] DTlbResp { resp: <'h0000000080003cf0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003cf0 o: 'h0000000080003cf0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003cf0, check_high: 'h00000000080003cf4, check_inclusive: True } }, specBits: 'h000 } + 34840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080003cf0, shiftedBE: tagged DataMemAccess , pcHash: 'h8350 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } + 34840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 34840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080003cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 63 <= 00000000200003e4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } + 34850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 34850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080003cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } + 34850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080003cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } + 34850 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 34850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 34850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h03, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080003ce8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 34860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8364 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34860 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000019000000001fffff44000000 + 34860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 34860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 34860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h5a8, localHist: 'h3d5, globalTaken: True, localTaken: True, pcIndex: 'h169 }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 34870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } + 34870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h84fa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34870 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 54 <= 0000000000000000000000001fffff44000000 + 34870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + 34870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffbc, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f4c +After delta: vaddr = 0x80000f4c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h002 } + 34880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h84fc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 34880 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 00000000200000be800000001fffff44000000 + 34880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffbc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000064 o: 'h0000000000000064 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080003cf0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 34890 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 00000000200003f4000000001fffff44000000 + 34890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff9dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 34900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h033, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h033, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0d <= 0000000000000000c00000001fffff44000000 + 34910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h031, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000036 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h031, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h033, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 34920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82fe } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h030 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h032, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 47 <= 00000000200010b9000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 34930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 34930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 34930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 34930 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 34930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 34930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 69 <= 0000000020000f30000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h010 } + 34940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34940 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000000800000001fffff44000000 + 34940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } + 34940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 34940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 34940 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 34940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 66 <= 00000000200000bc800000001fffff44000000 +[RFile] wr_ 1: r 05 <= 00000000200003cc000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34950 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h010 } + 34950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h82ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 34950 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000000800000001fffff44000000 + 34950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 34950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 34950 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 34950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h012 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 34950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 34950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7d <= 00000000200000be800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 34960 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000000800000001fffff44000000 + 34960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800002fa o: 'h00000000800002fa b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 34960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 34960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 34960 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 34960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 34960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h012, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6a <= 00000000200003e4000000001fffff44000000 +[RFile] wr_ 1: r 7f <= 0000000000000000c00000001fffff44000000 + 34970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h010 } + 34970 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000000000000000000001fffff44000000 + 34970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: True, capStore: False, potentialCapLoad: False } + 34970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 34970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 34980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 34980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 34980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 34980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 44 <= 0000000000000010000000001fffff44000000 + 34990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 34990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 34990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 34990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'had4, localHist: 'h3aa, globalTaken: True, localTaken: True, pcIndex: 'h168 }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 35090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 35100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 51 <= 0000000000000000c00000001fffff44000000 + 35110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 35110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 35110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff9dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 35120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 35120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 35120 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 35120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } + 35130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35130 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000000000000800000001fffff44000000 + 35130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000036 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 42 <= 00000000200010b9000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 35140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 35140 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 35140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 55 <= 0000000020000f30000000001fffff44000000 + 35150 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 0000000000000000800000001fffff44000000 + 35150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } + 35150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:898 PC:0x1ffff00000000000000000000800002ca instr:0xfc442583 iType:Ld [doCommitNormalInst [0]] 3515 +instret:899 PC:0x1ffff00000000000000000000800002ce instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 3515 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 45 <= 00000000200000bc800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35160 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h001 } + 35160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h82ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 35160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5f <= 00000000200003cc000000001fffff44000000 +[RFile] wr_ 1: r 64 <= 00000000200000be800000001fffff44000000 + 35170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800002fa o: 'h00000000800002fa b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 35170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 35170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 35170 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } + 35170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 35170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:900 PC:0x1ffff00000000000000000000800002d0 instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 3517 +instret:901 PC:0x1ffff00000000000000000000800002d8 instr:0x0040006f iType:J [doCommitNormalInst [1]] 3517 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 75 <= 0000000000000010000000001fffff44000000 + 35180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 35180 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 61 <= 0000000000000000000000001fffff44000000 + 35180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 35180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 35180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:902 PC:0x1ffff00000000000000000000800002dc instr:0xfc442503 iType:Ld [doCommitNormalInst [0]] 3518 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 56 <= 0000000020000f40000000001fffff44000000 +[RFile] wr_ 1: r 6c <= 00000000200003e4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 35190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 35190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 35190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 35190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:903 PC:0x1ffff00000000000000000000800002e0 instr:0x00551593 iType:Alu [doCommitNormalInst [0]] 3519 +instret:904 PC:0x1ffff00000000000000000000800002e4 instr:0x00004517 iType:Auipc [doCommitNormalInst [1]] 3519 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 35200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 35200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 35200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +instret:905 PC:0x1ffff00000000000000000000800002e8 instr:0x9dc50513 iType:Alu [doCommitNormalInst [0]] 3520 +instret:906 PC:0x1ffff00000000000000000000800002ec instr:0x0000952e iType:Alu [doCommitNormalInst [1]] 3520 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 35210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 35210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +instret:907 PC:0x1ffff00000000000000000000800002ee instr:0xfd04258f iType:Ld [doCommitNormalInst [0]] 3521 +instret:908 PC:0x1ffff00000000000000000000800002f2 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 3521 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 35220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8338 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 35220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:909 PC:0x1ffff00000000000000000000800002f6 instr:0x036080e7 iType:Jr [doCommitNormalInst [0]] 3522 +instret:910 PC:0x1ffff0000000000000000000080000328 instr:0x0000711d iType:Alu [doCommitNormalInst [1]] 3522 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 35230 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000020000f40000000001fffff44000000 + 35230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 35230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:911 PC:0x1ffff000000000000000000008000032a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 3523 +instret:912 PC:0x1ffff000000000000000000008000032c instr:0x0000e8a2 iType:St [doCommitNormalInst [1]] 3523 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h832a } + 35240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 35240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d00 +After delta: vaddr = 0x80003d00 + 35240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +instret:913 PC:0x1ffff000000000000000000008000032e instr:0x00001080 iType:Alu [doCommitNormalInst [0]] 3524 +instret:914 PC:0x1ffff0000000000000000000080000330 instr:0xfea43423 iType:St [doCommitNormalInst [1]] 3524 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 35250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8342 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 35250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d00, write: False, capStore: False, potentialCapLoad: False } + 35250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } + 35250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:915 PC:0x1ffff0000000000000000000080000334 instr:0xfcb44823 iType:St [doCommitNormalInst [0]] 3525 +instret:916 PC:0x1ffff0000000000000000000080000338 instr:0xfe843503 iType:Ld [doCommitNormalInst [1]] 3525 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 35260 : [doFinishMem] DTlbResp { resp: <'h0000000080003d00,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d00, check_high: 'h00000000080003d08, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h832c } + 35260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080003d00, shiftedBE: tagged DataMemAccess , pcHash: 'h833c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35260 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7e <= 0000000020000f40000000001fffff44000000 + 35260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 35260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080003d00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 35270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 35270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080003d00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 35270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080003d00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 35270 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } + 35270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d08 +After delta: vaddr = 0x80003d08 + 35270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 35280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h834c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 35280 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 65 <= 0000000000000000000000001fffff44000000 + 35280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d08 o: 'h0000000080003d08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d08, write: False, capStore: False, potentialCapLoad: False } + 35280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } + 35280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080003d00, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35290 : [doFinishMem] DTlbResp { resp: <'h0000000080003d08,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d08 o: 'h0000000080003d08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d08, check_high: 'h00000000080003d10, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8330 } + 35290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080003d08, shiftedBE: tagged DataMemAccess , pcHash: 'h8346 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35290 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 0000000020000f40000000001fffff44000000 + 35290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 35290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080003d08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hd6a, localHist: 'h002, globalTaken: True, localTaken: False, pcIndex: 'h1b4 }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 58 <= 0000000000000000000000001fffff44000000 + 35300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 35300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080003d08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 35300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080003d08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 35300 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } + 35300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d10 +After delta: vaddr = 0x80003d10 + 35300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } +instret:917 PC:0x1ffff000000000000000000008000033c instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 3530 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0e, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000018e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 35310 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 60 <= 0000000000000000c00000001fffff44000000 + 35310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080003d00 o: 'h0000000080003d00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d10 o: 'h0000000080003d10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d10, write: False, capStore: False, potentialCapLoad: False } + 35310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 35310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 35310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35310 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080003d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35320 : [doFinishMem] DTlbResp { resp: <'h0000000080003d10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d10 o: 'h0000000080003d10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d10, check_high: 'h00000000080003d14, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8334 } + 35320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080003d10, shiftedBE: tagged DataMemAccess , pcHash: 'h8350 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } + 35320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080003d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 35320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080003d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 35320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 35320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080003d10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } +instret:918 PC:0x1ffff000000000000000000008000033e instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3532 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 35330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } + 35330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080003d10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } + 35330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080003d10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } + 35330 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 35330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 35330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080003d08, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } + 35340 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000064000000001fffff44000000 + 35340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 35340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } + 35340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 35340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35340 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080003d80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:919 PC:0x1ffff0000000000000000000080000342 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3534 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 63 <= 00000000200003e4000000001fffff44000000 + 35350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h833e } + 35350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8360 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 35350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 35350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080003d80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 35350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080003d80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 35350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffbc, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f4c +After delta: vaddr = 0x80000f4c + 35350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } +instret:920 PC:0x1ffff0000000000000000000080000346 instr:0x00006508 iType:Ld [doCommitNormalInst [0]] 3535 +instret:921 PC:0x1ffff0000000000000000000080000348 instr:0xfca43023 iType:St [doCommitNormalInst [1]] 3535 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h03, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 35360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8364 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 35360 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000000000000000000001fffff44000000 + 35360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffbc, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000190 o: 'h0000000000000190 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } + 35360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } + 35360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 35360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h6b5, localHist: 'h3ea, globalTaken: True, localTaken: False, pcIndex: 'h169 }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080003d10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8348 } + 35370 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 54 <= 0000000000000000000000001fffff44000000 + 35370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 35370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 35370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } +instret:922 PC:0x1ffff000000000000000000008000034c instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3537 +calling cycle + 35380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } + 35380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h84fa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + 35380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } + 35380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fa } +instret:923 PC:0x1ffff0000000000000000000080000350 instr:0x00004908 iType:Ld [doCommitNormalInst [0]] 3538 +instret:924 PC:0x1ffff0000000000000000000080000352 instr:0xfaa42e23 iType:St [doCommitNormalInst [1]] 3538 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000038 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8352 } + 35390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h84fc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fa } + 35390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fa } + 35390 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 35390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fc } +instret:925 PC:0x1ffff0000000000000000000080000356 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 3539 +instret:926 PC:0x1ffff0000000000000000000080000358 instr:0xfaa42c23 iType:St [doCommitNormalInst [1]] 3539 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35400 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 00000000200000be800000001fffff44000000 + 35400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fc } + 35400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fc } + 35400 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 35400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } +instret:927 PC:0x1ffff000000000000000000008000035c instr:0x0040006f iType:J [doCommitNormalInst [0]] 3540 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffe1c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0d <= 0000000000000000c00000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35410 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 00000000200003f4000000001fffff44000000 + 35410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } + 35410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:928 PC:0x1ffff0000000000000000000080000360 instr:0xfb842503 iType:Ld [doCommitNormalInst [0]] 3541 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8358 } + 35420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 35420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } +instret:929 PC:0x1ffff0000000000000000000080000364 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 3542 +instret:930 PC:0x1ffff0000000000000000000080000368 instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 3542 +calling cycle +[RFile] wr_ 0: r 44 <= 00000000200000c4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 35430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } + 35430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 35430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h011, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:931 PC:0x1ffff000000000000000000008000036c instr:0x18e0006f iType:J [doCommitNormalInst [0]] 3543 +instret:932 PC:0x1ffff00000000000000000000800004fa instr:0x000060e6 iType:Ld [doCommitNormalInst [1]] 3543 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 47 <= 00000000200000c6000000001fffff44000000 +[ALU redirect - 0] 'h1ffff000000000000000000008000012c; 'h2; InstTag { way: 'h1, ptr: 'h18, t: 'h31 } + 35440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 35440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82fe } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 35440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 35440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 35440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } +instret:933 PC:0x1ffff00000000000000000000800004fc instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 3544 +instret:934 PC:0x1ffff00000000000000000000800004fe instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 3544 +calling cycle +[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h18, t: 'h31 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 35460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 35460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } + 35460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 35460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 35460 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 35460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } +instret:935 PC:0x1ffff0000000000000000000080000500 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 3546 +instret:936 PC:0x1ffff00000000000000000000800002fa instr:0x0040006f iType:J [doCommitNormalInst [1]] 3546 +calling cycle + 35470 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h010 } + 35470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h830c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 35470 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000000800000001fffff44000000 + 35470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 35470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 35470 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 35470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h830c } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 35480 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000000800000001fffff44000000 + 35480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h830c } + 35480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h830c } + 35480 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 35480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 35480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 35490 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000000000000001fffff44000000 + 35490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 +instret:937 PC:0x1ffff00000000000000000000800002fe instr:0xfc442503 iType:Ld [doCommitNormalInst [0]] 3549 +calling cycle +[RFile] wr_ 1: r 7f <= 0000000000000000c00000001fffff44000000 + 35500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: True, capStore: False, potentialCapLoad: False } +calling cycle +[ALU redirect - 1] 'h1ffff00000000000000000000800002d8; 'h4; InstTag { way: 'h1, ptr: 'h16, t: 'h2d } + 35510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } +instret:938 PC:0x1ffff0000000000000000000080000302 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 3551 +calling cycle +[ROB incorrectSpec] 'h4 ; InstTag { way: 'h1, ptr: 'h16, t: 'h2d } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:939 PC:0x1ffff0000000000000000000080000304 instr:0xfca42223 iType:St [doCommitNormalInst [0]] 3553 +instret:940 PC:0x1ffff0000000000000000000080000308 instr:0xfc3ff06f iType:J [doCommitNormalInst [1]] 3553 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8304 } + 35540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } +calling cycle + 35550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 35550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } + 35550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 35550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 35550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 36030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hb5a, localHist: 'h3d5, globalTaken: True, localTaken: True, pcIndex: 'h168 }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 36040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 36050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 36050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0d <= 0000000000000000c00000001fffff44000000 + 36060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 36060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 36060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff9dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 36070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 36070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 36070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 36070 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 36070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 36080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } + 36080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36080 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000000c00000001fffff44000000 + 36080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 36080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000036 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 47 <= 00000000200010b9000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 36090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 36090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82dc } + 36090 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 36090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 69 <= 0000000020000f30000000001fffff44000000 + 36100 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000000c00000001fffff44000000 + 36100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } +instret:941 PC:0x1ffff00000000000000000000800002ca instr:0xfc442583 iType:Ld [doCommitNormalInst [0]] 3610 +instret:942 PC:0x1ffff00000000000000000000800002ce instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 3610 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 66 <= 00000000200000bc800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 36110 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h001 } + 36110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h82ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 36110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7d <= 00000000200000be800000001fffff44000000 + 36120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 36120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ee } + 36120 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 36120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 36120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:943 PC:0x1ffff00000000000000000000800002d0 instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 3612 +instret:944 PC:0x1ffff00000000000000000000800002d8 instr:0x0040006f iType:J [doCommitNormalInst [1]] 3612 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 44 <= 0000000000000018000000001fffff44000000 +[RFile] wr_ 1: r 05 <= 00000000200003cc000000001fffff44000000 + 36130 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000000000000000000001fffff44000000 + 36130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800002fa o: 'h00000000800002fa b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 36130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 36130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:945 PC:0x1ffff00000000000000000000800002dc instr:0xfc442503 iType:Ld [doCommitNormalInst [0]] 3613 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 67 <= 0000000020000f48000000001fffff44000000 +[RFile] wr_ 1: r 6a <= 00000000200003e4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 36140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 36140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 36140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 36140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:946 PC:0x1ffff00000000000000000000800002e0 instr:0x00551593 iType:Alu [doCommitNormalInst [0]] 3614 +instret:947 PC:0x1ffff00000000000000000000800002e4 instr:0x00004517 iType:Auipc [doCommitNormalInst [1]] 3614 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 36150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 36150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 36150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 36150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:948 PC:0x1ffff00000000000000000000800002e8 instr:0x9dc50513 iType:Alu [doCommitNormalInst [0]] 3615 +instret:949 PC:0x1ffff00000000000000000000800002ec instr:0x0000952e iType:Alu [doCommitNormalInst [1]] 3615 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 36160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 36160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 36160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +instret:950 PC:0x1ffff00000000000000000000800002ee instr:0xfd04258f iType:Ld [doCommitNormalInst [0]] 3616 +instret:951 PC:0x1ffff00000000000000000000800002f2 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 3616 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 36170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 36170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 36170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:952 PC:0x1ffff00000000000000000000800002f6 instr:0x036080e7 iType:Jr [doCommitNormalInst [0]] 3617 +instret:953 PC:0x1ffff0000000000000000000080000328 instr:0x0000711d iType:Alu [doCommitNormalInst [1]] 3617 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 36180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 36180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8338 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 36180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +instret:954 PC:0x1ffff000000000000000000008000032a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 3618 +instret:955 PC:0x1ffff000000000000000000008000032c instr:0x0000e8a2 iType:St [doCommitNormalInst [1]] 3618 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h832a } + 36190 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 57 <= 0000000020000f48000000001fffff44000000 + 36190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 36190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 36190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +instret:956 PC:0x1ffff000000000000000000008000032e instr:0x00001080 iType:Alu [doCommitNormalInst [0]] 3619 +instret:957 PC:0x1ffff0000000000000000000080000330 instr:0xfea43423 iType:St [doCommitNormalInst [1]] 3619 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 36200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 36200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8342 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 36200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } + 36200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 36200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d20 +After delta: vaddr = 0x80003d20 + 36200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:958 PC:0x1ffff0000000000000000000080000334 instr:0xfcb44823 iType:St [doCommitNormalInst [0]] 3620 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h832c } + 36210 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0b <= 0000000020000f48000000001fffff44000000 + 36210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d20, write: False, capStore: False, potentialCapLoad: False } + 36210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 36210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 36210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } +instret:959 PC:0x1ffff0000000000000000000080000338 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3621 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 36220 : [doFinishMem] DTlbResp { resp: <'h0000000080003d20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d20, check_high: 'h00000000080003d28, check_inclusive: True } }, specBits: 'h000 } + 36220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080003d20, shiftedBE: tagged DataMemAccess , pcHash: 'h833c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 36220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } + 36220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832c } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 36220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d28 +After delta: vaddr = 0x80003d28 + 36220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003d20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 36230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8330 } + 36230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h834c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 36230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d28 o: 'h0000000080003d28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d28, write: False, capStore: False, potentialCapLoad: False } + 36230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003d20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 36230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080003d20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 36230 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 36230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 36230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 36240 : [doFinishMem] DTlbResp { resp: <'h0000000080003d28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d28 o: 'h0000000080003d28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d28, check_high: 'h00000000080003d30, check_inclusive: True } }, specBits: 'h000 } + 36240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080003d28, shiftedBE: tagged DataMemAccess , pcHash: 'h8346 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36240 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000000000000001fffff44000000 + 36240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 36240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 36240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 36240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 36240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080003d28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdad, localHist: 'h001, globalTaken: True, localTaken: False, pcIndex: 'h1b4 }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7a <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080003d20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8334 } + 36250 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4b <= 0000000020000f48000000001fffff44000000 + 36250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } + 36250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080003d28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 36250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080003d28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8346 } + 36250 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } + 36250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 36250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 36250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0e, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000018e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 36260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 36260 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 41 <= 0000000000000000c00000001fffff44000000 + 36260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 36260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } + 36260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8334 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 36260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80003d30 +After delta: vaddr = 0x80003d30 + 36260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:960 PC:0x1ffff000000000000000000008000033c instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 3626 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 36270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 36270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080003d20 o: 'h0000000080003d20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003d30 o: 'h0000000080003d30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080003d30, write: False, capStore: False, potentialCapLoad: False } + 36270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + 36270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 36270 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003d68, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 36280 : [doFinishMem] DTlbResp { resp: <'h0000000080003d30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080003d30 o: 'h0000000080003d30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003d30, check_high: 'h00000000080003d34, check_inclusive: True } }, specBits: 'h000 } + 36280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080003d30, shiftedBE: tagged DataMemAccess , pcHash: 'h8350 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } + 36280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003d68, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 36280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080003d68, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 36280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 36280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 36280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080003d30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } +instret:961 PC:0x1ffff000000000000000000008000033e instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3628 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 36290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h833e } + 36290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 36290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080003d30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } + 36290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080003d30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8350 } + 36290 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 36290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 36290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 36290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4e <= 00000000200003e4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080003d28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 36300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } + 36300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8360 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 36300 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 0000000000000190000000001fffff44000000 + 36300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 36300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } + 36300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833e } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 36300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 36300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffbc, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 36300 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080003da8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:962 PC:0x1ffff0000000000000000000080000342 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3630 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h03, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 36310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 36310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8364 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36310 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 + 36310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 36310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080003da8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 36310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080003da8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 36310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffbc, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f4c +After delta: vaddr = 0x80000f4c + 36310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 36310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8364 } +instret:963 PC:0x1ffff0000000000000000000080000346 instr:0x00006508 iType:Ld [doCommitNormalInst [0]] 3631 +instret:964 PC:0x1ffff0000000000000000000080000348 instr:0xfca43023 iType:St [doCommitNormalInst [1]] 3631 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h6d6, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h169 }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 36320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8348 } + 36320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h84fa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffbc, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000640 o: 'h0000000000000640 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } + 36320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8364 } + 36320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8364 } + 36320 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 36320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 36320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fa } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080003d30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 36330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 36330 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 0000000000000000000000001fffff44000000 + 36330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + 36330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fa } + 36330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fa } + 36330 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } + 36330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } +instret:965 PC:0x1ffff000000000000000000008000034c instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 3633 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000038 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 36340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h002 } + 36340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h84fc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36340 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5c <= 00000000200000be800000001fffff44000000 + 36340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } + 36340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8348 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 36340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fc } +instret:966 PC:0x1ffff0000000000000000000080000350 instr:0x00004908 iType:Ld [doCommitNormalInst [0]] 3634 +instret:967 PC:0x1ffff0000000000000000000080000352 instr:0xfaa42e23 iType:St [doCommitNormalInst [1]] 3634 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7b <= 0000000000000000c00000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8352 } + 36350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fc } + 36350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fc } + 36350 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 36350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } +instret:968 PC:0x1ffff0000000000000000000080000356 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 3635 +instret:969 PC:0x1ffff0000000000000000000080000358 instr:0xfaa42c23 iType:St [doCommitNormalInst [1]] 3635 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffe1c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 36360 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 00000000200003f4000000001fffff44000000 + 36360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } + 36360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8352 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 36360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 36360 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080003d70, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:970 PC:0x1ffff000000000000000000008000035c instr:0x0040006f iType:J [doCommitNormalInst [0]] 3636 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8358 } + 36370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080003d70, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 36370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080003d70, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 36370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 36370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 36370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } +instret:971 PC:0x1ffff0000000000000000000080000360 instr:0xfb842503 iType:Ld [doCommitNormalInst [0]] 3637 +calling cycle +[RFile] wr_ 0: r 6d <= 00000000200000c4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 36380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 36380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } + 36380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8358 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 36380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 36380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 36380 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080003db0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:972 PC:0x1ffff0000000000000000000080000364 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 3638 +instret:973 PC:0x1ffff0000000000000000000080000368 instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 3638 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[RFile] wr_ 0: r 6e <= 00000000200000c6000000001fffff44000000 +[ALU redirect - 0] 'h1ffff000000000000000000008000012c; 'h2; InstTag { way: 'h1, ptr: 'h18, t: 'h31 } + 36390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 36390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82fe } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 36390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080003db0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 36390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080003db0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 36390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 36390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 36390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } +instret:974 PC:0x1ffff000000000000000000008000036c instr:0x18e0006f iType:J [doCommitNormalInst [0]] 3639 +instret:975 PC:0x1ffff00000000000000000000800004fa instr:0x000060e6 iType:Ld [doCommitNormalInst [1]] 3639 +calling cycle +[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h18, t: 'h31 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 36410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 36410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } + 36410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 36410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82fe } + 36410 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } + 36410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } +instret:976 PC:0x1ffff00000000000000000000800004fc instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 3641 +instret:977 PC:0x1ffff00000000000000000000800004fe instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 3641 +calling cycle + 36420 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h010 } + 36420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h830c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 36420 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 56 <= 0000000000000000c00000001fffff44000000 + 36420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 36420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 36420 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } + 36420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h830c } +instret:978 PC:0x1ffff0000000000000000000080000500 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 3642 +instret:979 PC:0x1ffff00000000000000000000800002fa instr:0x0040006f iType:J [doCommitNormalInst [1]] 3642 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 36430 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7e <= 0000000000000000c00000001fffff44000000 + 36430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h830c } + 36430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h830c } + 36430 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 36430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 36440 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000000000000001fffff44000000 + 36440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 +instret:980 PC:0x1ffff00000000000000000000800002fe instr:0xfc442503 iType:Ld [doCommitNormalInst [0]] 3644 +calling cycle +[RFile] wr_ 1: r 70 <= 0000000000000001000000001fffff44000000 + 36450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: True, capStore: False, potentialCapLoad: False } +calling cycle +[ALU redirect - 1] 'h1ffff00000000000000000000800002d8; 'h4; InstTag { way: 'h1, ptr: 'h16, t: 'h2d } + 36460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } +instret:981 PC:0x1ffff0000000000000000000080000302 instr:0x00002505 iType:Alu [doCommitNormalInst [0]] 3646 +calling cycle +[ROB incorrectSpec] 'h4 ; InstTag { way: 'h1, ptr: 'h16, t: 'h2d } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:982 PC:0x1ffff0000000000000000000080000304 instr:0xfca42223 iType:St [doCommitNormalInst [0]] 3648 +instret:983 PC:0x1ffff0000000000000000000080000308 instr:0xfc3ff06f iType:J [doCommitNormalInst [1]] 3648 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8304 } + 36490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } +calling cycle + 36500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } + 36500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f94, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8304 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 36500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 37010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hb6b, localHist: 'h3ea, globalTaken: True, localTaken: False, pcIndex: 'h168 }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 37020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 +calling cycle + 37030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[RFile] wr_ 1: r 7b <= 0000000000000000c00000001fffff44000000 + 37040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 37040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 37040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000038 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 37050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 37050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f94, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ca } + 37050 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } + 37050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 37060 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7e <= 0000000000000001000000001fffff44000000 + 37060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffe1c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f94, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 37070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 +calling cycle + 37080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } +instret:984 PC:0x1ffff00000000000000000000800002ca instr:0xfc442583 iType:Ld [doCommitNormalInst [0]] 3708 +instret:985 PC:0x1ffff00000000000000000000800002ce instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 3708 +calling cycle +[RFile] wr_ 0: r 6d <= 00000000200000c4000000001fffff44000000 + 37090 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h001 } + 37090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h830c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 37090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h830c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6e <= 00000000200000c6000000001fffff44000000 +[ALU redirect - 1] 'h1ffff000000000000000000008000012c; 'h2; InstTag { way: 'h0, ptr: 'h03, t: 'h06 } + 37100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h830c } + 37100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h830c } + 37100 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 37100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 37100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:986 PC:0x1ffff00000000000000000000800002d0 instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 3710 +instret:987 PC:0x1ffff00000000000000000000800002d4 instr:0x0380006f iType:J [doCommitNormalInst [1]] 3710 +calling cycle +[ROB incorrectSpec] 'h2 ; InstTag { way: 'h0, ptr: 'h03, t: 'h06 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 37120 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000000000000001fffff44000000 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } +calling cycle +instret:988 PC:0x1ffff000000000000000000008000030c instr:0xfd04250f iType:Ld [doCommitNormalInst [0]] 3714 +instret:989 PC:0x1ffff0000000000000000000080000310 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 3714 +calling cycle +instret:990 PC:0x1ffff0000000000000000000080000314 instr:0xe1c080e7 iType:Jr [doCommitNormalInst [0]] 3715 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 37170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 37180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 37180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5a <= 00000000200003d8000000001fffff44000000 + 37190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000318 o: 'h0000000080000318 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 37190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 37190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h5b5, localHist: 'h2aa, globalTaken: True, localTaken: True, pcIndex: 'h0a0 }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 01 <= 00000000200003e4000000001fffff44000000 + 37200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 37200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 37200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 + 37200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:991 PC:0x1ffff000000000000000000008000012c instr:0x00007179 iType:Alu [doCommitNormalInst [0]] 3720 +calling cycle + 37210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 37210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: True, capStore: False, potentialCapLoad: True } + 37210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 +instret:992 PC:0x1ffff000000000000000000008000012e instr:0x0000f406 iType:St [doCommitNormalInst [0]] 3721 +calling cycle +[RFile] wr_ 0: r 6c <= 0000000000000000000000001fffff44000000 + 37220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h812e } + 37220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: False, capStore: False, potentialCapLoad: True } + 37220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812e } +instret:993 PC:0x1ffff0000000000000000000080000130 instr:0x0000f022 iType:St [doCommitNormalInst [0]] 3722 +instret:994 PC:0x1ffff0000000000000000000080000132 instr:0x00001800 iType:Alu [doCommitNormalInst [1]] 3722 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 37230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 37230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f70, shiftedBE: tagged DataMemAccess , pcHash: 'h8138 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 37230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812e } + 37230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812e } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 37230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:995 PC:0x1ffff0000000000000000000080000134 instr:0xfea44023 iType:St [doCommitNormalInst [0]] 3723 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000005a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8130 } + 37240 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 0000000000000000000000001fffff44000000 + 37240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8130 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 37250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8130 } + 37250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8130 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 37250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8134 } + 37260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } +instret:996 PC:0x1ffff0000000000000000000080000138 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3726 +instret:997 PC:0x1ffff000000000000000000008000013c instr:0xfea005db iType:Cap [doCommitNormalInst [1]] 3726 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 37270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } + 37270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 37270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 37270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 37280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 37280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:998 PC:0x1ffff0000000000000000000080000140 instr:0x00b50463 iType:Br [doCommitNormalInst [0]] 3728 +instret:999 PC:0x1ffff0000000000000000000080000148 instr:0x0040006f iType:J [doCommitNormalInst [1]] 3728 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 37290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 37290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 +instret:1000 PC:0x1ffff000000000000000000008000014c instr:0x05a0006f iType:J [doCommitNormalInst [0]] 3729 +calling cycle + 37300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 37300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h81a6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 37300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + 37300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a6 } +calling cycle +[RFile] wr_ 1: r 0e <= 00000000200003e4000000001fffff44000000 + 37310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 37310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h81a8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 37310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a6 } + 37310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a6 } + 37310 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 37310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 37310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a8 } +calling cycle + 37320 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 00000000200000c6000000001fffff44000000 + 37320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a8 } + 37320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a8 } + 37320 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 37320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 37330 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 00000000200003f4000000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 37340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:1001 PC:0x1ffff00000000000000000000800001a6 instr:0x000070a2 iType:Ld [doCommitNormalInst [0]] 3734 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 37350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 37350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:1002 PC:0x1ffff00000000000000000000800001a8 instr:0x00007402 iType:Ld [doCommitNormalInst [0]] 3735 +instret:1003 PC:0x1ffff00000000000000000000800001aa instr:0x00006145 iType:Alu [doCommitNormalInst [1]] 3735 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 54 <= 0000000000000000000000001fffff44000000 + 37360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: False, potentialCapLoad: True } + 37360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc8 +After delta: vaddr = 0x80000fc8 + 37360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:1004 PC:0x1ffff00000000000000000000800001ac instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 3736 +calling cycle + 37370 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 37370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc8, write: False, capStore: False, potentialCapLoad: False } + 37370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc0 +After delta: vaddr = 0x80000fc0 +instret:1005 PC:0x1ffff0000000000000000000080000318 instr:0xfea0055b iType:Cap [doCommitNormalInst [0]] 3737 +calling cycle +[RFile] wr_ 1: r 0d <= 00000000200003f4000000001fffff44000000 + 37380 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc8, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h000 } + 37380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000fc8, shiftedBE: tagged DataMemAccess , pcHash: 'h8320 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 37380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc0, write: False, capStore: False, potentialCapLoad: False } + 37380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } +instret:1006 PC:0x1ffff000000000000000000008000031c instr:0xfca44823 iType:St [doCommitNormalInst [0]] 3738 +calling cycle + 37390 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc0, check_high: 'h00000000080000fc8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h831c } + 37390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000fc0, shiftedBE: tagged DataMemAccess , pcHash: 'h8322 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 37390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } + 37390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8320 } + 37390 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } + 37390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 37390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8322 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 37400 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6b <= 0000000020000149800000001fffff44000000 + 37400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8322 } + 37400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8322 } + 37400 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } + 37400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 37400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000fc8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 37410 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6f <= 0000000020000400000000001fffff44000000 + 37410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831c } + 37410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h831c } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 37410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 37410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h03, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000fc0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 37420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc4 +After delta: vaddr = 0x80000fc4 + 37420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:1007 PC:0x1ffff0000000000000000000080000320 instr:0x000070e2 iType:Ld [doCommitNormalInst [0]] 3742 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hada, localHist: 'h3fa, globalTaken: True, localTaken: False, pcIndex: 'h169 }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000526; 'h1; InstTag { way: 'h0, ptr: 'h0d, t: 'h1a } + 37430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc4 o: 'h0000000080000fc4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc4, write: False, capStore: False, potentialCapLoad: False } + 37430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc4 +After delta: vaddr = 0x80000fc4 +instret:1008 PC:0x1ffff0000000000000000000080000322 instr:0x00007442 iType:Ld [doCommitNormalInst [0]] 3743 +instret:1009 PC:0x1ffff0000000000000000000080000324 instr:0x00006121 iType:Alu [doCommitNormalInst [1]] 3743 +calling cycle +[ROB incorrectSpec] 'h1 ; InstTag { way: 'h0, ptr: 'h0d, t: 'h1a } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:1010 PC:0x1ffff0000000000000000000080000326 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 3745 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 37490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 37500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd8 +After delta: vaddr = 0x80000fd8 + 37500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 37510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd8, write: False, capStore: False, potentialCapLoad: False } + 37510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff8 +After delta: vaddr = 0x80000ff8 + 37510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 37520 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd8, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 37520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000fd8, shiftedBE: tagged DataMemAccess , pcHash: 'h8526 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 37520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } + 37520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff0 +After delta: vaddr = 0x80000ff0 + 37520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000fd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8526 } +calling cycle + 37530 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } + 37530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h852a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 37530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } + 37530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000fd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8526 } + 37530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000fd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8526 } + 37530 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 37530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 37530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h852a } +calling cycle +[RFile] wr_ 1: r 44 <= 0000000020000400000000001fffff44000000 + 37540 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } + 37540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h852c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 37540 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000000000000001fffff44000000 + 37540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h852a } + 37540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h852a } + 37540 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 37540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 37540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h852c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000fd8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 37550 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 0000000020000006000000001fffff44000000 + 37550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h852c } + 37550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h852c } + 37550 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } + 37550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000ff8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 37560 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 69 <= 0000000000000000000000001fffff44000000 + 37560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:1011 PC:0x1ffff0000000000000000000080000526 instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 3756 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h03, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000ff0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 37570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 33554431 +Before delta: vaddr = 0xffffffffffffffc4 +After delta: vaddr = 0xffffffffffffffc4 + 37570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:1012 PC:0x1ffff000000000000000000008000052a instr:0x000070a2 iType:Ld [doCommitNormalInst [0]] 3757 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h56d, localHist: 'h3fa, globalTaken: True, localTaken: False, pcIndex: 'h169 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000018; 'h0; InstTag { way: 'h1, ptr: 'h0f, t: 'h1f } + 37580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'hffffffffffffffc4 o: 'hffffffffffffffc4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'hffffffffffffffc4, write: False, capStore: False, potentialCapLoad: False } + 37580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 33554431 +Before delta: vaddr = 0xffffffffffffffc4 +After delta: vaddr = 0xffffffffffffffc4 +instret:1013 PC:0x1ffff000000000000000000008000052c instr:0x00007402 iType:Ld [doCommitNormalInst [0]] 3758 +instret:1014 PC:0x1ffff000000000000000000008000052e instr:0x00006145 iType:Alu [doCommitNormalInst [1]] 3758 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h0f, t: 'h1f } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:1015 PC:0x1ffff0000000000000000000080000530 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 3760 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 37660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 63 <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 66 <= 0000000000000000000000001fffff44000000 + 37670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x00000000 +After delta: vaddr = 0x00000000 + 37670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 40 <= 0000000000000000400000001fffff44000000 + 37680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000000000, write: True, capStore: False, potentialCapLoad: False } + 37680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff8 +After delta: vaddr = 0x80000ff8 + 37680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:1016 PC:0x1ffff0000000000000000000080000018 instr:0x0000832a iType:Alu [doCommitNormalInst [0]] 3768 +instret:1017 PC:0x1ffff000000000000000000008000001a instr:0x00004281 iType:Alu [doCommitNormalInst [1]] 3768 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 78 <= 00000000200003e4000000001fffff44000000 + 37690 : [doFinishMem] DTlbResp { resp: <'h0000000000000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000000000, check_high: 'h00000000000000008, check_inclusive: True } }, specBits: 'h000 } + 37690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000018 o: 'h0000000080000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: True, capStore: False, potentialCapLoad: False } + 37690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff0 +After delta: vaddr = 0x80000ff0 + 37690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:1018 PC:0x1ffff000000000000000000008000001c instr:0x00004305 iType:Alu [doCommitNormalInst [0]] 3769 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 67 <= 0000000020000400000000001fffff44000000 + 37700 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } + 37700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: True, capStore: False, potentialCapLoad: False } + 37700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd8 +After delta: vaddr = 0x80000fd8 + 37700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000050e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 37710 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_MMIO_issue] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000000000000, isMMIO: True, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h801e }; MMIOCRq { addr: 'h0000000000000000, func: tagged St , byteEn: , data: TaggedData { tag: False, data: }, loadTags: False } + 37710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd8, write: True, capStore: False, potentialCapLoad: False } + 37710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd8 +After delta: vaddr = 0x80000fd8 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 37720 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd8, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 37720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd8, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 37730 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd8, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 37730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000fd8, shiftedBE: tagged DataMemAccess , pcHash: 'h802e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 37730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00002000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000771 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 41 <= 000000002000040e800000001fffff44000000 + 37740 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 0000000000000000000000001fffff44000000 + 37740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001548 +After delta: vaddr = 0x80001548 + 37740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h2b6, localHist: 'h355, globalTaken: True, localTaken: True, pcIndex: 'h028 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +3775: mmioPlatform.rl_tohost: 0x1 (= 1) +PASS diff --git a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test-error.txt b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test-error.txt new file mode 100644 index 0000000..2f7f821 --- /dev/null +++ b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test-error.txt @@ -0,0 +1,6325 @@ +make -C ../../Tests/elf_to_hex +make[1]: Entering directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/TooobaTest/Toooba/Tests/elf_to_hex' +make[1]: 'elf_to_hex' is up to date. +make[1]: Leaving directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/TooobaTest/Toooba/Tests/elf_to_hex' +../../Tests/elf_to_hex/elf_to_hex ../../Tests/isa/testC Mem.hex +c_mem_load_elf: ../../Tests/isa/testC is a 64-bit ELF file +Section .text : addr 80000000 to addr 80000588; size 0x 588 (= 1416) bytes +Section .data : addr 80001588 to addr 80001598; size 0x 10 (= 16) bytes +Section .sbss : addr 80001598 to addr 800015a0; size 0x 8 (= 8) bytes +Section .bss : addr 800015a0 to addr 80002720; size 0x 1180 (= 4480) bytes +Section .riscv.attributes: Ignored +Section .comment : Ignored +Section .symtab : Searching for addresses of '_start', 'exit' and 'tohost' symbols +Writing symbols to: symbol_table.txt + No 'exit' label found + No 'tohost' symbol found +Section .shstrtab : Ignored +Section .strtab : Ignored +Min addr: 80000000 (hex) +Max addr: 8000271f (hex) +Writing mem hex to file 'Mem.hex' +Subtracting 0x80000000 base from addresses +./exe_HW_sim +v1 +tohost +Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 313 to 33554430. +1: top.soc_top.rl_reset_start_initial ... +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +11: Mem_Controller.set_addr_map: addr_base 0x80000000 addr_lim 0xc0000000 + SoC address map: + Boot ROM: 0x1000 .. 0x2000 + Mem0 Controller: 0x80000000 .. 0xc0000000 + UART0: 0xc0000000 .. 0xc0000080 +11: top.soc_top.rl_reset_complete_initial +calling cycle +================================================================ +Bluespec RISC-V standalone system simulation v1.2 +Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved. +================================================================ +INFO: watch_tohost 1, tohost_addr = 0x0, fromhost_addr = 0x0 +12: top.soc_top.method start (tohost 0, fromhost 0) +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +100: top.soc_top.rl_step_0, n = 0, do_release +100: top.soc_top do_release(restartRunning: True, to_host_addr: 0) +100: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0 +calling cycle +101: top.soc_top.rl_ctrl_req +101: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0 +101: top.soc_top do_release(restartRunning: True, to_host_addr: 0) +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000020 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle +[RFile] wr_ 1: r 40 <= 0000000000000400000000001fffff44000000 +calling cycle +[RFile] wr_ 0: r 41 <= 0000000000000408000000001fffff44000000 +instret:0 PC:0x1ffff0000000000000000000000001000 instr:0x00000297 iType:Auipc [doCommitNormalInst [0]] 167 +calling cycle +instret:1 PC:0x1ffff0000000000000000000000001004 instr:0x02028593 iType:Alu [doCommitNormalInst [0]] 168 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Csr, execFunc: tagged Alu Csrs, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Valid csrAddrMHARTID, scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle +[RFile] wr_ 0: r 42 <= 0000000000000000000000001fffff44000000 +calling cycle +instret:2 PC:0x1ffff0000000000000000000000001008 instr:0xf1402573 iType:Csr [doCommitSystemInst] 224 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling 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+calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 3340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 3350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000018, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x00001018 +After delta: vaddr = 0x00001018 +calling cycle + 3360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000018, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000000001000 o: 'h0000000000001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000001018, write: False, capStore: False, potentialCapLoad: False } +calling cycle + 3370 : [doFinishMem] DTlbResp { resp: <'h0000000000001018,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000001018, check_high: 'h00000000000001020, check_inclusive: True } }, specBits: 'h000 } +calling cycle +calling cycle +[doDeqLdQ_MMIO_issue] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid }; MMIOCRq { addr: 'h0000000000001018, func: tagged Ld , byteEn: , data: TaggedData { tag: , data: }, loadTags: False } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +[RFile] wr_ 3: r 43 <= 0000000020000000000000001fffff44000000 +[doDeqLdQ_MMIO_deq] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid }; TaggedData { tag: False, data: }; TaggedData { tag: False, data: } +calling cycle +instret:3 PC:0x1ffff000000000000000000000000100c instr:0x0182b283 iType:Ld [doCommitNormalInst [0]] 403 +calling cycle +calling cycle +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000000; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:4 PC:0x1ffff0000000000000000000000001010 instr:0x00028067 iType:Jr [doCommitNormalInst [0]] 408 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling 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cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00080000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipcc, execFunc: tagged Alu Add, capFunc: tagged CapModify tagged SpecialRW tagged TCC , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrPCC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h48, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h48, src2: tagged Valid 'h48, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000546 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 46 <= 0000000000020000000000001fffff44000000 +[RFile] wr_ 1: r 45 <= 40000000200000000000ffff1fffff44000000 +calling cycle +[RFile] wr_ 1: r 47 <= 0000000000020000400000001fffff44000000 +instret:5 PC:0x1ffff0000000000000000000080000000 instr:0x020000db iType:Auipcc [doCommitNormalInst [0]] 1155 +instret:6 PC:0x1ffff0000000000000000000080000004 instr:0x000802b7 iType:Alu [doCommitNormalInst [1]] 1155 +calling cycle +[RFile] wr_ 0: r 48 <= 0000000020000400000000001fffff44000000 +instret:7 PC:0x1ffff0000000000000000000080000008 instr:0x00002285 iType:Alu [doCommitNormalInst [0]] 1156 +calling cycle +[RFile] wr_ 0: r 4a <= 0000000020000004000000001fffff44000000 +[RFile] wr_ 1: r 49 <= 0000000020000400000000001fffff44000000 +instret:8 PC:0x1ffff000000000000000000008000000a instr:0x000002b2 iType:Alu [doCommitNormalInst [0]] 1157 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4b <= 0000000020000006000000001fffff44000000 +[ALU redirect - 1] 'h1ffff0000000000000000000080000556; 'h0; InstTag { way: 'h1, ptr: 'h05, t: 'h0b } + 11580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:9 PC:0x1ffff000000000000000000008000000c instr:0x2052815b iType:Cap [doCommitNormalInst [0]] 1158 +instret:10 PC:0x1ffff0000000000000000000080000010 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1158 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h05, t: 'h0b } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:11 PC:0x1ffff0000000000000000000080000014 instr:0x546080e7 iType:Jr [doCommitNormalInst [0]] 1160 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 13430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 13440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff8 +After delta: vaddr = 0x80000ff8 + 13440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000010 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4c <= 00000000200003f4000000001fffff44000000 + 13450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000018 o: 'h0000000080000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: True, capStore: False, potentialCapLoad: False } + 13450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff0 +After delta: vaddr = 0x80000ff0 + 13450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4f <= 0000000020000400000000001fffff44000000 + 13460 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } + 13460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: True, capStore: False, potentialCapLoad: False } + 13460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd8 +After delta: vaddr = 0x80000fd8 + 13460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:12 PC:0x1ffff0000000000000000000080000556 instr:0x00007179 iType:Alu [doCommitNormalInst [0]] 1346 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 50 <= 0000000000000000000000001fffff44000000 + 13470 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } + 13470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd8, write: True, capStore: False, potentialCapLoad: False } + 13470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffec, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fec +After delta: vaddr = 0x80000fec + 13470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:13 PC:0x1ffff0000000000000000000080000558 instr:0x0000f406 iType:St [doCommitNormalInst [0]] 1347 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc38 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 53 <= 0000000000000004000000001fffff44000000 + 13480 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd8, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8558 } + 13480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffec, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fec, write: True, capStore: False, potentialCapLoad: False } + 13480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fe0 +After delta: vaddr = 0x80000fe0 + 13480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 13480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8558 } +instret:14 PC:0x1ffff000000000000000000008000055a instr:0x0000f022 iType:St [doCommitNormalInst [0]] 1348 +instret:15 PC:0x1ffff000000000000000000008000055c instr:0x00001800 iType:Alu [doCommitNormalInst [1]] 1348 +calling cycle + 13490 : [doFinishMem] DTlbResp { resp: <'h0000000080000fec,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fec, check_high: 'h00000000080000ff0, check_inclusive: True } }, specBits: 'h000 } + 13490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000010 o: 'h0000000000000010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe0 o: 'h0000000080000fe0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe0, write: True, capStore: False, potentialCapLoad: False } + 13490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 13490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8558 } + 13490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 13490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fe0 +After delta: vaddr = 0x80000fe0 +instret:16 PC:0x1ffff000000000000000000008000055e instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 1349 +instret:17 PC:0x1ffff0000000000000000000080000560 instr:0xfca43c23 iType:St [doCommitNormalInst [1]] 1349 +calling cycle + 13500 : [doFinishMem] DTlbResp { resp: <'h0000000080000fe0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fe0 o: 'h0000000080000fe0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fe0, check_high: 'h00000000080000fe8, check_inclusive: True } }, specBits: 'h000 } + 13500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe0 o: 'h0000000080000fe0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe0, write: False, capStore: False, potentialCapLoad: False } +instret:18 PC:0x1ffff0000000000000000000080000564 instr:0xfea42623 iType:St [doCommitNormalInst [0]] 1350 +instret:19 PC:0x1ffff0000000000000000000080000568 instr:0x00004541 iType:Alu [doCommitNormalInst [1]] 1350 +calling cycle + 13510 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8558 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000ff8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[RFile] wr_ 1: r 57 <= 000000002000015d000000001fffff44000000 + 13510 : [doFinishMem] DTlbResp { resp: <'h0000000080000fe0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fe0 o: 'h0000000080000fe0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fe0, check_high: 'h00000000080000fe8, check_inclusive: True } }, specBits: 'h000 } + 13510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000fe0, shiftedBE: tagged DataMemAccess , pcHash: 'h856e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, data: TaggedData { tag: False, data: } } +instret:20 PC:0x1ffff000000000000000000008000056a instr:0xfea43023 iType:St [doCommitNormalInst [0]] 1351 +calling cycle +[RFile] wr_ 0: r 58 <= 000000002000015f000000001fffff44000000 +[ALU redirect - 0] 'h1ffff00000000000000000000800001ac; 'h0; InstTag { way: 'h0, ptr: 'h0c, t: 'h18 } + 13520 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 55 <= 0000000000000004000000001fffff44000000 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h0c, t: 'h18 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000fe0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +calling cycle +instret:21 PC:0x1ffff000000000000000000008000056e instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 1355 +calling cycle +[RFile] wr_ 1: r 56 <= 0000000000000008000000001fffff44000000 +calling cycle +instret:22 PC:0x1ffff0000000000000000000080000572 instr:0x00000506 iType:Alu [doCommitNormalInst [0]] 1357 +instret:23 PC:0x1ffff0000000000000000000080000574 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1357 +calling cycle +instret:24 PC:0x1ffff0000000000000000000080000578 instr:0xc38080e7 iType:Jr [doCommitNormalInst [0]] 1358 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 14270 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000ff8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 14280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14280 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 14280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8558 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h855a } + 14290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h855a } +calling cycle + 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h855a } + 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h855a } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fd8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8560 } + 14310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fd8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8560 } +calling cycle + 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fd8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8560 } + 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fd8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8560 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fec, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8564 } + 14330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8564 } +calling cycle + 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8564 } + 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8564 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fe0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h856a } + 14350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fe0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h856a } +calling cycle + 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fe0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h856a } + 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fe0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h856a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 14630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00031000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 14640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc8 +After delta: vaddr = 0x80000fc8 + 14640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffd40 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 59 <= 00000000200003e4000000001fffff44000000 + 14650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000057c o: 'h000000008000057c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc8, write: True, capStore: False, potentialCapLoad: False } + 14650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc0 +After delta: vaddr = 0x80000fc0 + 14650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5c <= 00000000200003f4000000001fffff44000000 + 14660 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc8, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h000 } + 14660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc0, write: True, capStore: False, potentialCapLoad: False } + 14660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 +instret:25 PC:0x1ffff00000000000000000000800001ac instr:0x00007139 iType:Alu [doCommitNormalInst [0]] 1466 +calling cycle +[RFile] wr_ 0: r 5e <= 000000000000c400000000001fffff44000000 + 14670 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc0, check_high: 'h00000000080000fc8, check_inclusive: True } }, specBits: 'h000 } + 14670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: True, capStore: False, potentialCapLoad: False } +instret:26 PC:0x1ffff00000000000000000000800001ae instr:0x0000fc06 iType:St [doCommitNormalInst [0]] 1467 +calling cycle +[RFile] wr_ 0: r 5f <= 000000000000c350000000001fffff44000000 + 14680 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fc8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81ae } + 14680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ae } +instret:27 PC:0x1ffff00000000000000000000800001b0 instr:0x0000f822 iType:St [doCommitNormalInst [0]] 1468 +instret:28 PC:0x1ffff00000000000000000000800001b2 instr:0x00000080 iType:Alu [doCommitNormalInst [1]] 1468 +calling cycle + 14690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ae } + 14690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ae } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:29 PC:0x1ffff00000000000000000000800001b4 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 1469 +instret:30 PC:0x1ffff00000000000000000000800001b8 instr:0x00031537 iType:Alu [doCommitNormalInst [1]] 1469 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fc0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81b0 } + 14700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b0 } +instret:31 PC:0x1ffff00000000000000000000800001bc instr:0xd405051b iType:Alu [doCommitNormalInst [0]] 1470 +calling cycle + 14710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b0 } + 14710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b0 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81b4 } + 14720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b4 } +calling cycle + 14730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b4 } + 14730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +calling cycle +calling cycle + 14750 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b4 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000fb8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000019 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffe5a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000030d40 o: 'h0000000000030d40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: True, capStore: False, potentialCapLoad: False } +calling cycle +[RFile] wr_ 1: r 61 <= 0000000000000006400000001fffff44000000 + 15190 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } +calling cycle +[RFile] wr_ 0: r 63 <= 0000000020000072000000001fffff44000000 +[RFile] wr_ 1: r 62 <= 0000000000001900000000001fffff44000000 +instret:32 PC:0x1ffff00000000000000000000800001c0 instr:0xfea43023 iType:St [doCommitNormalInst [0]] 1520 +instret:33 PC:0x1ffff00000000000000000000800001c4 instr:0x00004565 iType:Alu [doCommitNormalInst [1]] 1520 +calling cycle +[RFile] wr_ 0: r 64 <= 0000000020000074000000001fffff44000000 +[ALU redirect - 0] 'h1ffff0000000000000000000080000022; 'h0; InstTag { way: 'h0, ptr: 'h12, t: 'h24 } +instret:34 PC:0x1ffff00000000000000000000800001c6 instr:0x0000052a iType:Alu [doCommitNormalInst [0]] 1521 +instret:35 PC:0x1ffff00000000000000000000800001c8 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1521 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h12, t: 'h24 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:36 PC:0x1ffff00000000000000000000800001cc instr:0xe5a080e7 iType:Jr [doCommitNormalInst [0]] 1523 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 15430 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000fb8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 15440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15440 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 15440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b4 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81c0 } + 15450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81c0 } +calling cycle + 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81c0 } + 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81c0 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 16120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 65 <= 00000000200003c8000000001fffff44000000 + 16130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000068, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800001d0 o: 'h00000000800001d0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 16130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 16130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 68 <= 00000000200003e4000000001fffff44000000 + 16140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 16140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000060, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 16140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 + 16140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:37 PC:0x1ffff0000000000000000000080000022 instr:0x00007159 iType:Alu [doCommitNormalInst [0]] 1614 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000055e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 16150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000006400 o: 'h0000000000006400 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: True, capStore: False, potentialCapLoad: False } + 16150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 +instret:38 PC:0x1ffff0000000000000000000080000024 instr:0x0000f486 iType:St [doCommitNormalInst [0]] 1615 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 16160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8024 } + 16160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } + 16160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } +instret:39 PC:0x1ffff0000000000000000000080000026 instr:0x0000f0a2 iType:St [doCommitNormalInst [0]] 1616 +instret:40 PC:0x1ffff0000000000000000000080000028 instr:0x00001880 iType:Alu [doCommitNormalInst [1]] 1616 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 16170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h802e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 16170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } + 16170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 16170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:41 PC:0x1ffff000000000000000000008000002a instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1617 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6e <= 000000002000040e800000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8026 } + 16180 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6a <= 0000000000001900000000001fffff44000000 + 16180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001598 +After delta: vaddr = 0x80001598 + 16180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h027 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6f <= 0000000020000566000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 16190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001598, write: False, capStore: False, potentialCapLoad: False } + 16190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } + 16190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 16190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16200 : [doFinishMem] DTlbResp { resp: <'h0000000080001598,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001598, check_high: 'h000000000800015a0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h802a } + 16200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080001598, shiftedBE: tagged DataMemAccess , pcHash: 'h8042 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } + 16200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } +instret:42 PC:0x1ffff000000000000000000008000002e instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 1620 +calling cycle +[RFile] wr_ 0: r 6b <= 0000000000001901c00000001fffff44000000 +[RFile] wr_ 1: r 73 <= 0000000000000400000000001fffff44000000 + 16210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 16210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 16210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } + 16210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 16210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 + 16210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } +calling cycle +[RFile] wr_ 0: r 74 <= 0000000000000400400000001fffff44000000 +[RFile] wr_ 1: r 6c <= 0000000000001900000000001fffff44000000 + 16220 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000000001900000000001fffff44000000 + 16220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000006400 o: 'h0000000000006400 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: True, capStore: False, potentialCapLoad: False } + 16220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } + 16220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:43 PC:0x1ffff0000000000000000000080000032 instr:0x0000051d iType:Alu [doCommitNormalInst [0]] 1622 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16230 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001598, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 16230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } +instret:44 PC:0x1ffff0000000000000000000080000034 instr:0x00009961 iType:Alu [doCommitNormalInst [0]] 1623 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000052a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16240 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f68, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 16240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:45 PC:0x1ffff0000000000000000000080000036 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1624 +instret:46 PC:0x1ffff000000000000000000008000003a instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1624 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 +instret:47 PC:0x1ffff000000000000000000008000003e instr:0x55e50513 iType:Alu [doCommitNormalInst [0]] 1625 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 77 <= 40000000000000000000ffff1fffff44000000 + 16260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: True, potentialCapLoad: True } + 16260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 000000002000041b800000001fffff44000000 + 16270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } + 16270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 16270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7a <= 0000000020000566000000001fffff44000000 + 16280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } + 16280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001598 +After delta: vaddr = 0x80001598 +calling cycle +[RFile] wr_ 1: r 7d <= 000000002000041f000000001fffff44000000 + 16290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h001 } + 16290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001598, write: False, capStore: False, potentialCapLoad: False } +calling cycle + 16300 : [doFinishMem] DTlbResp { resp: <'h0000000080001598,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001598, check_high: 'h000000000800015a0, check_inclusive: True } }, specBits: 'h001 } + 16300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080001598, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } +calling cycle + 16310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 16310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 16710 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001598, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } + 16720 : [Ld resp] 'h03; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } + 16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 +calling cycle + 16730 : [doRespLdMem] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000000000000000000001fffff44000000 + 16730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 16730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 16730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 16730 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } + 16730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080001598, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 16740 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7c <= 0000000000000000000000001fffff44000000 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } +instret:48 PC:0x1ffff0000000000000000000080000042 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 1675 +calling cycle +[RFile] wr_ 1: r 72 <= 0000000000001900000000001fffff44000000 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 17020 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f68, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 17030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17030 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 17030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8036 } + 17040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } +calling cycle + 17050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } + 17050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h027 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 17410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 17420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 73 <= 0000000000000400000000001fffff44000000 + 17430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } + 17430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } + 17430 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } + 17430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000052a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 74 <= 0000000000000400400000001fffff44000000 + 17440 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000000001900000000001fffff44000000 + 17440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f50 +After delta: vaddr = 0x80000f50 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 77 <= 40000000000000000000ffff1fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: True, potentialCapLoad: True } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000524 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 000000002000041b800000001fffff44000000 + 17460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } + 17460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:49 PC:0x1ffff0000000000000000000080000044 instr:0xfd843583 iType:Ld [doCommitNormalInst [0]] 1746 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 72 <= 0000000000001900000000001fffff44000000 + 17470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 17470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7a <= 0000000020000566000000001fffff44000000 +[ALU redirect - 0] 'h1ffff0000000000000000000080000056; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } + 17480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } + 17480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001598 +After delta: vaddr = 0x80001598 + 17480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:50 PC:0x1ffff0000000000000000000080000048 instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 1748 +instret:51 PC:0x1ffff000000000000000000008000004a instr:0x00006585 iType:Alu [doCommitNormalInst [1]] 1748 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:52 PC:0x1ffff000000000000000000008000004c instr:0x00002585 iType:Alu [doCommitNormalInst [0]] 1750 +instret:53 PC:0x1ffff000000000000000000008000004e instr:0x00b57463 iType:Br [doCommitNormalInst [1]] 1750 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000074 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 +calling cycle +[RFile] wr_ 0: r 77 <= 0000000000000000000000001fffff44000000 + 17570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: True, capStore: False, potentialCapLoad: True } +calling cycle + 17580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } +instret:54 PC:0x1ffff0000000000000000000080000056 instr:0x0040006f iType:J [doCommitNormalInst [0]] 1758 +instret:55 PC:0x1ffff000000000000000000008000005a instr:0xfea0055b iType:Cap [doCommitNormalInst [1]] 1758 +calling cycle +instret:56 PC:0x1ffff000000000000000000008000005e instr:0xfea44023 iType:St [doCommitNormalInst [0]] 1759 +instret:57 PC:0x1ffff0000000000000000000080000062 instr:0x0740006f iType:J [doCommitNormalInst [1]] 1759 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h805e } + 17600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +calling cycle + 17610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } + 17610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 + 18100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: False, capStore: False, potentialCapLoad: True } + 18110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 18110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 18120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 18120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f70, shiftedBE: tagged DataMemAccess , pcHash: 'h80d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 18120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 18120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } +calling cycle + 18130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 18130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h80da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + 18130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } + 18130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } + 18130 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 18130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } +calling cycle +[RFile] wr_ 1: r 7d <= 00000000200003e4000000001fffff44000000 + 18140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 18140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h80dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18140 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 0000000000000000000000001fffff44000000 + 18140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + 18140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + 18140 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } + 18140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 18150 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7b <= 0000000020000074000000001fffff44000000 + 18150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 18150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 18150 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } + 18150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 18160 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7c <= 00000000200003f4000000001fffff44000000 + 18160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:58 PC:0x1ffff00000000000000000000800000d6 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1816 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 18170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 18170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:59 PC:0x1ffff00000000000000000000800000da instr:0x000070a6 iType:Ld [doCommitNormalInst [0]] 1817 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: False, potentialCapLoad: True } + 18180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 18180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:60 PC:0x1ffff00000000000000000000800000dc instr:0x00007406 iType:Ld [doCommitNormalInst [0]] 1818 +instret:61 PC:0x1ffff00000000000000000000800000de instr:0x00006165 iType:Alu [doCommitNormalInst [1]] 1818 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h800, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h0f2 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 05 <= 0000000000000000000000001fffff44000000 + 18190 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 18190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: True, capStore: False, potentialCapLoad: False } + 18190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c +instret:62 PC:0x1ffff00000000000000000000800000e0 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 1819 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000dc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 18200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } +instret:63 PC:0x1ffff00000000000000000000800001d0 instr:0xfca44823 iType:St [doCommitNormalInst [0]] 1820 +instret:64 PC:0x1ffff00000000000000000000800001d4 instr:0x00004501 iType:Alu [doCommitNormalInst [1]] 1820 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 44 <= 0000000000000000800000001fffff44000000 + 18210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h81d0 } + 18210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h81de } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 18210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 18210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d0 } +instret:65 PC:0x1ffff00000000000000000000800001d6 instr:0xfca42623 iType:St [doCommitNormalInst [0]] 1821 +instret:66 PC:0x1ffff00000000000000000000800001da instr:0x0040006f iType:J [doCommitNormalInst [1]] 1821 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18220 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000000000000001fffff44000000 + 18220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d0 } + 18220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d0 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 18220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 18220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc4, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h400, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h16b }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 46 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81d6 } + 18230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: True, capStore: False, potentialCapLoad: False } + 18230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f94 +After delta: vaddr = 0x80000f94 + 18230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000038 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h004 } + 18240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc4, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h04, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f94, write: False, capStore: False, potentialCapLoad: False } + 18240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d6 } + 18240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 18240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:67 PC:0x1ffff00000000000000000000800001de instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 1824 +instret:68 PC:0x1ffff00000000000000000000800001e2 instr:0x00004509 iType:Alu [doCommitNormalInst [1]] 1824 +calling cycle +[RFile] wr_ 0: r 4a <= 0000000000000000c00000001fffff44000000 +[ALU redirect - 1] 'h1ffff00000000000000000000800001ec; 'h2; InstTag { way: 'h0, ptr: 'h0a, t: 'h14 } + 18250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f94,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f94 o: 'h0000000080000f94 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f94, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h004 } + 18250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f94, shiftedBE: tagged DataMemAccess , pcHash: 'h82ce } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, data: TaggedData { tag: False, data: } } +calling cycle +[ROB incorrectSpec] 'h2 ; InstTag { way: 'h0, ptr: 'h0a, t: 'h14 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 18270 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +instret:69 PC:0x1ffff00000000000000000000800001e4 instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 1827 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 18810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ge, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hc00, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h100 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 46 <= 0000000000000000000000001fffff44000000 + 18820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 18820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 18830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +instret:70 PC:0x1ffff00000000000000000000800001ec instr:0x0040006f iType:J [doCommitNormalInst [0]] 1883 +instret:71 PC:0x1ffff00000000000000000000800001f0 instr:0x00004501 iType:Alu [doCommitNormalInst [1]] 1883 +calling cycle +[RFile] wr_ 1: r 4a <= 0000000000000000c00000001fffff44000000 + 18840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 18840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81fa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, data: TaggedData { tag: False, data: } } +instret:72 PC:0x1ffff00000000000000000000800001f2 instr:0xfca42423 iType:St [doCommitNormalInst [0]] 1884 +instret:73 PC:0x1ffff00000000000000000000800001f6 instr:0x0040006f iType:J [doCommitNormalInst [1]] 1884 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81f2 } + 18850 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 45 <= 0000000000000000000000001fffff44000000 + 18850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f2 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 18860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f2 } + 18860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f2 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 18860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +instret:74 PC:0x1ffff00000000000000000000800001fa instr:0xfc842583 iType:Ld [doCommitNormalInst [0]] 1887 +instret:75 PC:0x1ffff00000000000000000000800001fe instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 1887 +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000208; 'h2; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } +calling cycle +[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:76 PC:0x1ffff0000000000000000000080000200 instr:0x00b55463 iType:Br [doCommitNormalInst [0]] 1890 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 19390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000374 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 19400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 19410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h001 } + 19410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h820c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h820c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 42 <= 0000000020000485000000001fffff44000000 + 19420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h820c } + 19420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h820c } + 19420 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } + 19420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:77 PC:0x1ffff0000000000000000000080000208 instr:0x0040006f iType:J [doCommitNormalInst [0]] 1942 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00002000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000378 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 51 <= 0000000020000562000000001fffff44000000 + 19430 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4e <= 0000000000000000000000001fffff44000000 + 19430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 19440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 19450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 19450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8220 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8220 } +instret:78 PC:0x1ffff000000000000000000008000020c instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 1945 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 55 <= 000000002000088a000000001fffff44000000 +[RFile] wr_ 1: r 08 <= 0000000000000000000000001fffff44000000 + 19460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8220 } + 19460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8220 } + 19460 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } + 19460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001588 +After delta: vaddr = 0x80001588 + 19460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 52 <= 0000000020000562000000001fffff44000000 + 19470 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 54 <= 0000000000000000000000001fffff44000000 + 19470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080001588 o: 'h0000000080001588 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001588 o: 'h0000000080001588 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001588, write: False, capStore: False, potentialCapLoad: False } + 19470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 19470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:79 PC:0x1ffff0000000000000000000080000210 instr:0x00271513 iType:Alu [doCommitNormalInst [0]] 1947 +instret:80 PC:0x1ffff0000000000000000000080000214 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 1947 +calling cycle +[RFile] wr_ 1: r 4b <= 0000000020000968000000001fffff44000000 + 19480 : [doFinishMem] DTlbResp { resp: <'h0000000080001588,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001588 o: 'h0000000080001588 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001588, check_high: 'h0000000008000158c, check_inclusive: True } }, specBits: 'h000 } + 19480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080001588, shiftedBE: tagged DataMemAccess , pcHash: 'h821e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } + 19480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 19480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080001588, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821e } +instret:81 PC:0x1ffff0000000000000000000080000218 instr:0x37458693 iType:Alu [doCommitNormalInst [0]] 1948 +instret:82 PC:0x1ffff000000000000000000008000021c instr:0x00009536 iType:Alu [doCommitNormalInst [1]] 1948 +calling cycle +[RFile] wr_ 1: r 4c <= 0000000000000000000000001fffff44000000 + 19490 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 19490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8238 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 19490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080001588, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821e } + 19490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080001588, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h821e } + 19490 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } + 19490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } +calling cycle +[RFile] wr_ 0: r 53 <= 0000000000000000000000001fffff44000000 + 19500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 19500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h823c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19500 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 0000000000000006400000001fffff44000000 + 19500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 19500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 19500 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 19500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h823c } +calling cycle +[RFile] wr_ 0: r 57 <= 0000000020000968000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080001588, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 19510 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000000000008000000001fffff44000000 + 19510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h823c } + 19510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h823c } + 19510 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } + 19510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800025b0 +After delta: vaddr = 0x800025b0 +calling cycle +[RFile] wr_ 0: r 5a <= 0000000020000968000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 19520 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5d <= 0000000000000000000000001fffff44000000 + 19520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h00000000800025a0 o: 'h00000000800025a0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000019 o: 'h0000000000000019 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800025b0 o: 'h00000000800025b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800025b0, write: True, capStore: False, potentialCapLoad: False } +instret:83 PC:0x1ffff000000000000000000008000021e instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 1952 +calling cycle + 19530 : [doFinishMem] DTlbResp { resp: <'h00000000800025b0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800025b0 o: 'h00000000800025b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800025b0, check_high: 'h000000000800025b4, check_inclusive: True } }, specBits: 'h000 } +instret:84 PC:0x1ffff0000000000000000000080000220 instr:0xfcc42583 iType:Ld [doCommitNormalInst [0]] 1953 +instret:85 PC:0x1ffff0000000000000000000080000224 instr:0x00759613 iType:Alu [doCommitNormalInst [1]] 1953 +calling cycle +instret:86 PC:0x1ffff0000000000000000000080000228 instr:0x00002597 iType:Auipc [doCommitNormalInst [0]] 1954 +instret:87 PC:0x1ffff000000000000000000008000022c instr:0x37858593 iType:Alu [doCommitNormalInst [1]] 1954 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:88 PC:0x1ffff0000000000000000000080000230 instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 1955 +instret:89 PC:0x1ffff0000000000000000000080000232 instr:0x00000716 iType:Alu [doCommitNormalInst [1]] 1955 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:90 PC:0x1ffff0000000000000000000080000234 instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 1956 +instret:91 PC:0x1ffff0000000000000000000080000236 instr:0x0000ca08 iType:St [doCommitNormalInst [1]] 1956 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800025b0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8236 } + 19570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800025b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8236 } +instret:92 PC:0x1ffff0000000000000000000080000238 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 1957 +instret:93 PC:0x1ffff000000000000000000008000023c instr:0xfcc42603 iType:Ld [doCommitNormalInst [1]] 1957 +calling cycle + 19580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800025b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8236 } + 19580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +calling cycle +calling cycle + 19600 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800025b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8236 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800025b0, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0e, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 19980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 56 <= 0000000000000000000000001fffff44000000 + 19990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 19990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000002 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5e <= 0000000020000968000000001fffff44000000 + 20000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 20000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8244 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 20000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 20000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8244 } +instret:94 PC:0x1ffff0000000000000000000080000240 instr:0x0000061e iType:Alu [doCommitNormalInst [0]] 2000 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 20010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } + 20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8244 } + 20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8244 } + 20010 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } + 20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:95 PC:0x1ffff0000000000000000000080000242 instr:0x0000962e iType:Alu [doCommitNormalInst [0]] 2001 + [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Div, w: False, sign: Unsigned } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20020 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 20020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h824e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20020 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 60 <= 0000000000000000000000001fffff44000000 + 20020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 20020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 20020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0d, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h000 } + 20030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8252 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 20030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824e } + 20030 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } + 20030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 20030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8252 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 20040 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 000000000000c350000000001fffff44000000 + 20040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 20040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8252 } + 20040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8252 } + 20040 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 20040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:96 PC:0x1ffff0000000000000000000080000244 instr:0xfc842703 iType:Ld [doCommitNormalInst [0]] 2004 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5f <= 0000000000000000000000001fffff44000000 + 20050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 20050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8262 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20050 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000000000000001fffff44000000 + 20050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800025a8 +After delta: vaddr = 0x800025a8 + 20050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8262 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'he00, localHist: 'h2aa, globalTaken: True, localTaken: True, pcIndex: 'h13a }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 61 <= 0000000020000968000000001fffff44000000 + 20060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h00000000800025a0 o: 'h00000000800025a0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800025a8 o: 'h00000000800025a8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800025a8, write: True, capStore: False, potentialCapLoad: False } + 20060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8262 } + 20060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8262 } + 20060 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 20060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:97 PC:0x1ffff0000000000000000000080000248 instr:0x00000716 iType:Alu [doCommitNormalInst [0]] 2006 +calling cycle + 20070 : [doFinishMem] DTlbResp { resp: <'h00000000800025a8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800025a8 o: 'h00000000800025a8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800025a8, check_high: 'h000000000800025b0, check_inclusive: True } }, specBits: 'h000 } + 20070 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000000000000001fffff44000000 + 20070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f9c +After delta: vaddr = 0x80000f9c + 20070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:98 PC:0x1ffff000000000000000000008000024a instr:0x0000963a iType:Alu [doCommitNormalInst [0]] 2007 +calling cycle +[RFile] wr_ 0: r 66 <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 6d <= 0000000000000000000000001fffff44000000 + 20080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } + 20080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001588 +After delta: vaddr = 0x80001588 +instret:99 PC:0x1ffff000000000000000000008000024c instr:0x0000e608 iType:St [doCommitNormalInst [0]] 2008 +calling cycle +[RFile] wr_ 0: r 67 <= 0000000020000562000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 20090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h8270 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080001588 o: 'h0000000080001588 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001588 o: 'h0000000080001588 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001588, write: False, capStore: False, potentialCapLoad: False } + 20090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8270 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6a <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20100 : [doFinishMem] DTlbResp { resp: <'h0000000080001588,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001588 o: 'h0000000080001588 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001588, check_high: 'h0000000008000158c, check_inclusive: True } }, specBits: 'h000 } + 20100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080001588, shiftedBE: tagged DataMemAccess , pcHash: 'h825c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8270 } + 20100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f9c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8270 } + 20100 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } + 20100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 20100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080001588, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825c } +instret:100 PC:0x1ffff000000000000000000008000024e instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2010 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00002000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000005 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6b <= 0000000020000968000000001fffff44000000 + 20110 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6f <= 0000000000000000000000001fffff44000000 + 20110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080001588, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825c } + 20110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080001588, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h825c } + 20110 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } + 20110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:101 PC:0x1ffff0000000000000000000080000252 instr:0xfc842603 iType:Ld [doCommitNormalInst [0]] 2011 +instret:102 PC:0x1ffff0000000000000000000080000256 instr:0x00261713 iType:Alu [doCommitNormalInst [1]] 2011 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000031a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6c <= 0000000020000968000000001fffff44000000 + 20120 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5c <= 0000000000000006400000001fffff44000000 + 20120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +instret:103 PC:0x1ffff000000000000000000008000025a instr:0x000096ba iType:Alu [doCommitNormalInst [0]] 2012 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080001588, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000f9c, check_inclusive: True } }, specBits: 'h003 } + 20130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h827e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 20130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000e8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 75 <= 00000000200008a1800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827e } + 20140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h827e } + 20140 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } + 20140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 +instret:104 PC:0x1ffff000000000000000000008000025c instr:0x00004294 iType:Ld [doCommitNormalInst [0]] 2014 +calling cycle +[RFile] wr_ 0: r 76 <= 0000000020000968000000001fffff44000000 + 20150 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000000000000000000001fffff44000000 + 20150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } +calling cycle +[RFile] wr_ 0: r 79 <= 00000000200000a5000000001fffff44000000 + 20160 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 20160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h8290 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8290 } +calling cycle +[RFile] wr_ 0: r 77 <= 00000000200000a7000000001fffff44000000 +[ALU redirect - 0] 'h1ffff000000000000000000008000037c; 'h2; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } + 20170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8290 } + 20170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8290 } + 20170 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 20170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; +calling cycle +[RFile] wr_ 1: r 73 <= 0000000000000000000000001fffff44000000 + 20190 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000000000000000000001fffff44000000 +calling cycle +[RFile] wr_ 1: r 72 <= 0000000020000968000000001fffff44000000 +calling cycle +calling cycle +calling cycle + 20230 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800025b0, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 20240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20240 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 20240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800025b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8236 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800025a8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h824c } + 20250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800025a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824c } +calling cycle + 20260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800025a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824c } + 20260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800025a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824c } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +[RFile] wr_ 2: r 69 <= 00000000000007d0000000001fffff44000000 +calling cycle + 20350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:105 PC:0x1ffff000000000000000000008000025e instr:0x02d55533 iType:Alu [doCommitNormalInst [0]] 2035 +instret:106 PC:0x1ffff0000000000000000000080000262 instr:0xfcc42683 iType:Ld [doCommitNormalInst [1]] 2035 +calling cycle + 20360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800025a0 +After delta: vaddr = 0x800025a0 +instret:107 PC:0x1ffff0000000000000000000080000266 instr:0x0000069e iType:Alu [doCommitNormalInst [0]] 2036 +instret:108 PC:0x1ffff0000000000000000000080000268 instr:0x000095b6 iType:Alu [doCommitNormalInst [1]] 2036 +calling cycle + 20370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h00000000800025a0 o: 'h00000000800025a0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000001f40 o: 'h0000000000001f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800025a0 o: 'h00000000800025a0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800025a0, write: True, capStore: False, potentialCapLoad: False } +instret:109 PC:0x1ffff000000000000000000008000026a instr:0x00000616 iType:Alu [doCommitNormalInst [0]] 2037 +instret:110 PC:0x1ffff000000000000000000008000026c instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 2037 +calling cycle + 20380 : [doFinishMem] DTlbResp { resp: <'h00000000800025a0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800025a0 o: 'h00000000800025a0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800025a0, check_high: 'h000000000800025a8, check_inclusive: True } }, specBits: 'h000 } +calling cycle +instret:111 PC:0x1ffff000000000000000000008000026e instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2039 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800025a0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h826e } + 20400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800025a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826e } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800025a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826e } + 20410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800025a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h826e } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:112 PC:0x1ffff0000000000000000000080000270 instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 2041 +instret:113 PC:0x1ffff0000000000000000000080000274 instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 2041 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } +instret:114 PC:0x1ffff000000000000000000008000027a instr:0x0040006f iType:J [doCommitNormalInst [0]] 2042 +instret:115 PC:0x1ffff000000000000000000008000027e instr:0xfc842503 iType:Ld [doCommitNormalInst [1]] 2042 +calling cycle +instret:116 PC:0x1ffff0000000000000000000080000282 instr:0x00551593 iType:Alu [doCommitNormalInst [0]] 2043 +instret:117 PC:0x1ffff0000000000000000000080000286 instr:0x00002517 iType:Auipc [doCommitNormalInst [1]] 2043 +calling cycle +instret:118 PC:0x1ffff000000000000000000008000028a instr:0x31a50513 iType:Alu [doCommitNormalInst [0]] 2044 +instret:119 PC:0x1ffff000000000000000000008000028e instr:0x0000952e iType:Alu [doCommitNormalInst [1]] 2044 +calling cycle +instret:120 PC:0x1ffff0000000000000000000080000290 instr:0xfd04258f iType:Ld [doCommitNormalInst [0]] 2045 +instret:121 PC:0x1ffff0000000000000000000080000294 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2045 +calling cycle +instret:122 PC:0x1ffff0000000000000000000080000298 instr:0x0e8080e7 iType:Jr [doCommitNormalInst [0]] 2046 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +calling cycle + 20750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 +calling cycle +[RFile] wr_ 1: r 64 <= 00000000200003c8000000001fffff44000000 + 20770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000029c o: 'h000000008000029c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } +calling cycle + 20780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } +instret:123 PC:0x1ffff000000000000000000008000037c instr:0x00007159 iType:Alu [doCommitNormalInst [0]] 2078 +calling cycle +instret:124 PC:0x1ffff000000000000000000008000037e instr:0x0000f486 iType:St [doCommitNormalInst [0]] 2079 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h837e } + 20800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h837e } +calling cycle + 20810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h837e } + 20810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h837e } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 21060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } + 21070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 21070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7e <= 00000000200003e4000000001fffff44000000 + 21080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 21080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800025a0 o: 'h00000000800025a0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 21080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 21080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 21090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 21090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } + 21090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +instret:125 PC:0x1ffff0000000000000000000080000380 instr:0x0000f0a2 iType:St [doCommitNormalInst [0]] 2109 +instret:126 PC:0x1ffff0000000000000000000080000382 instr:0x00001880 iType:Alu [doCommitNormalInst [1]] 2109 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 21100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8380 } + 21100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 21100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8380 } +instret:127 PC:0x1ffff0000000000000000000080000384 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 2110 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 21110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h838c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 21110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8380 } + 21110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8380 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:128 PC:0x1ffff0000000000000000000080000388 instr:0xfcb44823 iType:St [doCommitNormalInst [0]] 2111 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8384 } + 21120 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0b <= 0000000020000968000000001fffff44000000 + 21120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 21120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8384 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 21130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8384 } + 21130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8384 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800025a0 +After delta: vaddr = 0x800025a0 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8388 } + 21140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8396 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h00000000800025a0 o: 'h00000000800025a0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800025a0 o: 'h00000000800025a0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800025a0, write: False, capStore: False, potentialCapLoad: False } + 21140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8396 } +instret:129 PC:0x1ffff000000000000000000008000038c instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2114 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 21150 : [doFinishMem] DTlbResp { resp: <'h00000000800025a0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800025a0 o: 'h00000000800025a0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800025a0, check_high: 'h000000000800025a8, check_inclusive: True } }, specBits: 'h000 } + 21150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h00000000800025a0, shiftedBE: tagged DataMemAccess , pcHash: 'h8390 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8396 } + 21150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8396 } + 21150 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } + 21150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 21150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h00000000800025a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8390 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffac, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 21160 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 05 <= 0000000020000968000000001fffff44000000 + 21160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 21160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h00000000800025a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8390 } + 21160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h00000000800025a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8390 } + 21160 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 21160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8388 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 21170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h83a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21170 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 00000000000007d0000000001fffff44000000 + 21170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8388 } + 21170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8388 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800025a8 +After delta: vaddr = 0x800025a8 + 21170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83a0 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h00000000800025a0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h00000000800025a0 o: 'h00000000800025a0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800025a8 o: 'h00000000800025a8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800025a8, write: False, capStore: False, potentialCapLoad: False } + 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83a0 } + 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83a0 } + 21180 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 21180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf00, localHist: 'h2aa, globalTaken: True, localTaken: True, pcIndex: 'h1de }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 40 <= 0000000000000000000000001fffff44000000 + 21190 : [doFinishMem] DTlbResp { resp: <'h00000000800025a8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800025a8 o: 'h00000000800025a8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800025a8, check_high: 'h000000000800025b0, check_inclusive: True } }, specBits: 'h000 } + 21190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h00000000800025a8, shiftedBE: tagged DataMemAccess , pcHash: 'h839a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21190 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000020000968000000001fffff44000000 + 21190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000001f40 o: 'h0000000000001f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } + 21190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 21190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h00000000800025a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h839a } +instret:130 PC:0x1ffff0000000000000000000080000390 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2119 +calling cycle + 21200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 21200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } + 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h00000000800025a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h839a } + 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h00000000800025a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h839a } + 21200 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800025b0 +After delta: vaddr = 0x800025b0 + 21200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f3c, check_inclusive: True } }, specBits: 'h000 } + 21210 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000000000008000000001fffff44000000 + 21210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h00000000800025a0 o: 'h00000000800025a0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800025b0 o: 'h00000000800025b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800025b0, write: False, capStore: False, potentialCapLoad: False } + 21210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 21210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:131 PC:0x1ffff0000000000000000000080000392 instr:0xfaa43c23 iType:St [doCommitNormalInst [0]] 2121 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21220 : [doFinishMem] DTlbResp { resp: <'h00000000800025b0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800025b0 o: 'h00000000800025b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800025b0, check_high: 'h000000000800025b4, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8392 } + 21220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h00000000800025b0, shiftedBE: tagged DataMemAccess , pcHash: 'h83a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } + 21220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb0, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 21220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h00000000800025b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83a4 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h00000000800025a8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f3c, check_inclusive: True } }, specBits: 'h000 } + 21230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h83b4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 21230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } + 21230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h00000000800025b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83a4 } + 21230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h00000000800025b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83a4 } + 21230 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 21230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 21230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8392 } +instret:132 PC:0x1ffff0000000000000000000080000396 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2123 +calling cycle + 21240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 21240 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 0000000000000006400000001fffff44000000 + 21240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } + 21240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8392 } + 21240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8392 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffac, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:133 PC:0x1ffff000000000000000000008000039a instr:0x00006508 iType:Ld [doCommitNormalInst [0]] 2124 +calling cycle + 21250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 21250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h83b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21250 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 0000000000000000000000001fffff44000000 + 21250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffac, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f3c +After delta: vaddr = 0x80000f3c + 21250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83b8 } +instret:134 PC:0x1ffff000000000000000000008000039c instr:0xfaa43823 iType:St [doCommitNormalInst [0]] 2125 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h839c } + 21260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffac, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000019 o: 'h0000000000000019 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f3c o: 'h0000000080000f3c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f3c, write: True, capStore: False, potentialCapLoad: False } + 21260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83b8 } + 21260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83b8 } + 21260 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } } + 21260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h839c } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h00000000800025b0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f3c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f3c o: 'h0000000080000f3c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f3c, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 21270 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0e <= 00000000000007d0000000001fffff44000000 + 21270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h839c } + 21270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h839c } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:135 PC:0x1ffff00000000000000000000800003a0 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2127 +calling cycle +instret:136 PC:0x1ffff00000000000000000000800003a4 instr:0x00004908 iType:Ld [doCommitNormalInst [0]] 2128 +instret:137 PC:0x1ffff00000000000000000000800003a6 instr:0xfaa42623 iType:St [doCommitNormalInst [1]] 2128 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f3c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h83a6 } + 21290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f3c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83a6 } +instret:138 PC:0x1ffff00000000000000000000800003aa instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 2129 +instret:139 PC:0x1ffff00000000000000000000800003ac instr:0xfaa42423 iType:St [doCommitNormalInst [1]] 2129 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f3c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83a6 } + 21300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:140 PC:0x1ffff00000000000000000000800003b0 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2130 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:141 PC:0x1ffff00000000000000000000800003b4 instr:0xfa842503 iType:Ld [doCommitNormalInst [0]] 2131 +calling cycle + 21320 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f3c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83a6 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f3c, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +instret:142 PC:0x1ffff00000000000000000000800003b8 instr:0xfb843583 iType:Ld [doCommitNormalInst [0]] 2132 +instret:143 PC:0x1ffff00000000000000000000800003bc instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2132 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa4, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa4, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa4, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa4, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f34 +After delta: vaddr = 0x80000f34 + 21680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa4, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Lt, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf80, localHist: 'h2aa, globalTaken: True, localTaken: True, pcIndex: 'h1ed }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffac, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0d <= 0000000000000000000000001fffff44000000 + 21690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa4, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f34 o: 'h0000000080000f34 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f34, write: True, capStore: False, potentialCapLoad: False } + 21690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa4, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f34 +After delta: vaddr = 0x80000f34 + 21690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffac, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f34,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f34 o: 'h0000000080000f34 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f34, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } + 21700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa4, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f34 o: 'h0000000080000f34 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f34, write: False, capStore: False, potentialCapLoad: False } + 21700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffac, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f3c +After delta: vaddr = 0x80000f3c +instret:144 PC:0x1ffff00000000000000000000800003c4 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2170 +instret:145 PC:0x1ffff00000000000000000000800003c8 instr:0x00004501 iType:Alu [doCommitNormalInst [1]] 2170 +calling cycle + 21710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f34,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f34 o: 'h0000000080000f34 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f34, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } + 21710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f34, shiftedBE: tagged DataMemAccess , pcHash: 'h83d2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 21710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffac, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f3c o: 'h0000000080000f3c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f3c, write: False, capStore: False, potentialCapLoad: False } +instret:146 PC:0x1ffff00000000000000000000800003ca instr:0xfaa42223 iType:St [doCommitNormalInst [0]] 2171 +instret:147 PC:0x1ffff00000000000000000000800003ce instr:0x0040006f iType:J [doCommitNormalInst [1]] 2171 +calling cycle + 21720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f3c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f3c o: 'h0000000080000f3c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f3c, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 21720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f3c, shiftedBE: tagged DataMemAccess , pcHash: 'h83d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 21720 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 42 <= 0000000000000000000000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f34, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21730 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000006400000001fffff44000000 + 21730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc38 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f3c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb0, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 +instret:148 PC:0x1ffff00000000000000000000800003d2 instr:0xfa442503 iType:Ld [doCommitNormalInst [0]] 2174 +calling cycle + 21750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } +instret:149 PC:0x1ffff00000000000000000000800003d6 instr:0xfac42583 iType:Ld [doCommitNormalInst [0]] 2175 +calling cycle + 21760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h005 } + 21760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h83e6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83e6 } +calling cycle +[RFile] wr_ 1: r 4e <= 00000000200000fa800000001fffff44000000 + 21770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83e6 } + 21770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83e6 } + 21770 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 21770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:150 PC:0x1ffff00000000000000000000800003da instr:0x00b54463 iType:Br [doCommitNormalInst [0]] 2177 +instret:151 PC:0x1ffff00000000000000000000800003e2 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2177 +calling cycle +[RFile] wr_ 0: r 57 <= 00000000200000fc800000001fffff44000000 +[ALU redirect - 0] 'h1ffff0000000000000000000080000022; 'h1; InstTag { way: 'h1, ptr: 'h14, t: 'h29 } + 21780 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000008000000001fffff44000000 +calling cycle +[ROB incorrectSpec] 'h1 ; InstTag { way: 'h1, ptr: 'h14, t: 'h29 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +calling cycle +instret:152 PC:0x1ffff00000000000000000000800003e6 instr:0xfb043503 iType:Ld [doCommitNormalInst [0]] 2181 +instret:153 PC:0x1ffff00000000000000000000800003ea instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2181 +calling cycle +instret:154 PC:0x1ffff00000000000000000000800003ee instr:0xc38080e7 iType:Jr [doCommitNormalInst [0]] 2182 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 21910 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f3c, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 21920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21920 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 21920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f3c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h83ac } + 21930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83ac } +calling cycle + 21940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83ac } + 21940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83ac } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f34, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h83ca } + 21950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f34, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83ca } +calling cycle + 21960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f34, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83ca } + 21960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f34, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83ca } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f18 +After delta: vaddr = 0x80000f18 + 22310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5b <= 00000000200003ac000000001fffff44000000 + 22320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800003f2 o: 'h00000000800003f2 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: True, capStore: False, potentialCapLoad: False } + 22320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 22320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5d <= 00000000200003c8000000001fffff44000000 + 22330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 22330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: False, potentialCapLoad: False } + 22330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef8 +After delta: vaddr = 0x80000ef8 + 22330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:155 PC:0x1ffff0000000000000000000080000022 instr:0x00007159 iType:Alu [doCommitNormalInst [0]] 2233 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000055e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f18, check_inclusive: True } }, specBits: 'h000 } + 22340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: True, capStore: False, potentialCapLoad: False } + 22340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef8 +After delta: vaddr = 0x80000ef8 +instret:156 PC:0x1ffff0000000000000000000080000024 instr:0x0000f486 iType:St [doCommitNormalInst [0]] 2234 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 22350 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8024 } + 22350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } + 22350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } +instret:157 PC:0x1ffff0000000000000000000080000026 instr:0x0000f0a2 iType:St [doCommitNormalInst [0]] 2235 +instret:158 PC:0x1ffff0000000000000000000080000028 instr:0x00001880 iType:Alu [doCommitNormalInst [1]] 2235 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22360 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 22360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h802e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } + 22360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:159 PC:0x1ffff000000000000000000008000002a instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 2236 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4f <= 000000002000040e800000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8026 } + 22370 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4c <= 0000000000000008000000001fffff44000000 + 22370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001598 +After delta: vaddr = 0x80001598 + 22370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfc0, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h027 }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 61 <= 0000000020000566000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001598, write: False, capStore: False, potentialCapLoad: False } + 22380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } + 22380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef8 +After delta: vaddr = 0x80000ef8 +calling cycle + 22390 : [doFinishMem] DTlbResp { resp: <'h0000000080001598,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001598, check_high: 'h000000000800015a0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h802a } + 22390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080001598, shiftedBE: tagged DataMemAccess , pcHash: 'h8042 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } + 22390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } +instret:160 PC:0x1ffff000000000000000000008000002e instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2239 +calling cycle +[RFile] wr_ 0: r 60 <= 0000000000000009c00000001fffff44000000 +[RFile] wr_ 1: r 63 <= 0000000000000400000000001fffff44000000 + 22400 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 22400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } + 22400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } + 22400 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } + 22400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef8 +After delta: vaddr = 0x80000ef8 + 22400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5c <= 0000000000000400400000001fffff44000000 +[RFile] wr_ 1: r 5e <= 0000000000000008000000001fffff44000000 + 22410 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5f <= 0000000000000000000000001fffff44000000 + 22410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: True, capStore: False, potentialCapLoad: False } + 22410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } + 22410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:161 PC:0x1ffff0000000000000000000080000032 instr:0x0000051d iType:Alu [doCommitNormalInst [0]] 2241 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22420 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 22420 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 0000000000000008000000001fffff44000000 + 22420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:162 PC:0x1ffff0000000000000000000080000034 instr:0x00009961 iType:Alu [doCommitNormalInst [0]] 2242 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000052a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22430 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000ef8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 22430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ee0 +After delta: vaddr = 0x80000ee0 +instret:163 PC:0x1ffff0000000000000000000080000036 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 2243 +instret:164 PC:0x1ffff000000000000000000008000003a instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 2243 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 59 <= 40000000000000000000ffff1fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080001598, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ee0 o: 'h0000000080000ee0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ee0, write: True, capStore: True, potentialCapLoad: True } +instret:165 PC:0x1ffff000000000000000000008000003e instr:0x55e50513 iType:Alu [doCommitNormalInst [0]] 2244 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000524 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 67 <= 0000000000000008000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 22450 : [doFinishMem] DTlbResp { resp: <'h0000000080000ee0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ee0 o: 'h0000000080000ee0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ee0, check_high: 'h00000000080000ef0, check_inclusive: True } }, specBits: 'h003 } +instret:166 PC:0x1ffff0000000000000000000080000042 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2245 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6f <= 000000002000041f000000001fffff44000000 +[RFile] wr_ 1: r 6e <= 000000002000041b800000001fffff44000000 + 22470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000eb8 +After delta: vaddr = 0x80000eb8 + 22470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6c <= 0000000020000568000000001fffff44000000 +[RFile] wr_ 1: r 69 <= 0000000020000566000000001fffff44000000 + 22480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000eb8 o: 'h0000000080000eb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000eb8, write: True, capStore: False, potentialCapLoad: False } + 22480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001598 +After delta: vaddr = 0x80001598 + 22480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22490 : [doFinishMem] DTlbResp { resp: <'h0000000080000eb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000eb8 o: 'h0000000080000eb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000eb8, check_high: 'h00000000080000ec0, check_inclusive: True } }, specBits: 'h000 } + 22490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001598, write: False, capStore: False, potentialCapLoad: False } + 22490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ee0 +After delta: vaddr = 0x80000ee0 + 22490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22500 : [doFinishMem] DTlbResp { resp: <'h0000000080001598,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001598, check_high: 'h000000000800015a0, check_inclusive: True } }, specBits: 'h000 } + 22500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080001598, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ee0 o: 'h0000000080000ee0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ee0, write: False, capStore: False, potentialCapLoad: True } + 22500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ed8 +After delta: vaddr = 0x80000ed8 + 22500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22510 : [doFinishMem] DTlbResp { resp: <'h0000000080000ee0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ee0 o: 'h0000000080000ee0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ee0, check_high: 'h00000000080000ef0, check_inclusive: True } }, specBits: 'h000 } + 22510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000ee0, shiftedBE: tagged DataMemAccess , pcHash: 'h808a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 22510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ed8 o: 'h0000000080000ed8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ed8, write: False, capStore: False, potentialCapLoad: False } + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 22510 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ec0 +After delta: vaddr = 0x80000ec0 + 22510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22520 : [doFinishMem] DTlbResp { resp: <'h0000000080000ed8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ed8 o: 'h0000000080000ed8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ed8, check_high: 'h00000000080000ee0, check_inclusive: True } }, specBits: 'h000 } + 22520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000ed8, shiftedBE: tagged DataMemAccess , pcHash: 'h808e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22520 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000000000000000000001fffff44000000 + 22520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ec0, write: False, capStore: False, potentialCapLoad: True } + 22520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef8 +After delta: vaddr = 0x80000ef8 + 22520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080001598, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22530 : [doFinishMem] DTlbResp { resp: <'h0000000080000ec0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ec0, check_high: 'h00000000080000ed0, check_inclusive: True } }, specBits: 'h000 } + 22530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000ec0, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22530 : [doRespLdForward] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 76 <= 40000000000000000000ffff1fffff44000000 + 22530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } + 22530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } + 22530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 22530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 22540 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 22540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 22540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h4 + 22540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ed8 +After delta: vaddr = 0x80000ed8 + 22540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle + 22560 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef8 +After delta: vaddr = 0x80000ef8 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7e0, localHist: 'h1aa, globalTaken: True, localTaken: False, pcIndex: 'h027 }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 22640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22650 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 22650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, data: TaggedData { tag: False, data: } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 63 <= 0000000000000400000000001fffff44000000 + 22660 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 0000000000000008000000001fffff44000000 + 22660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000052a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5c <= 0000000000000400400000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ee0 +After delta: vaddr = 0x80000ee0 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 59 <= 40000000000000000000ffff1fffff44000000 + 22680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ee0 o: 'h0000000080000ee0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ee0, write: True, capStore: True, potentialCapLoad: True } +instret:167 PC:0x1ffff0000000000000000000080000044 instr:0xfd843583 iType:Ld [doCommitNormalInst [0]] 2268 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000524 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 67 <= 0000000000000008000000001fffff44000000 + 22690 : [doFinishMem] DTlbResp { resp: <'h0000000080000ee0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ee0 o: 'h0000000080000ee0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ee0, check_high: 'h00000000080000ef0, check_inclusive: True } }, specBits: 'h001 } + 22690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6e <= 000000002000041b800000001fffff44000000 + 22700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000eb8 +After delta: vaddr = 0x80000eb8 + 22700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:168 PC:0x1ffff0000000000000000000080000048 instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 2270 +instret:169 PC:0x1ffff000000000000000000008000004a instr:0x00006585 iType:Alu [doCommitNormalInst [1]] 2270 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6f <= 000000002000041f000000001fffff44000000 +[RFile] wr_ 1: r 69 <= 0000000020000566000000001fffff44000000 + 22710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000eb8 o: 'h0000000080000eb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000eb8, write: True, capStore: False, potentialCapLoad: False } + 22710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001598 +After delta: vaddr = 0x80001598 + 22710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:170 PC:0x1ffff000000000000000000008000004c instr:0x00002585 iType:Alu [doCommitNormalInst [0]] 2271 +instret:171 PC:0x1ffff000000000000000000008000004e instr:0x00b57463 iType:Br [doCommitNormalInst [1]] 2271 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6c <= 0000000020000568000000001fffff44000000 + 22720 : [doFinishMem] DTlbResp { resp: <'h0000000080000eb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000eb8 o: 'h0000000080000eb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000eb8, check_high: 'h00000000080000ec0, check_inclusive: True } }, specBits: 'h000 } + 22720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001598, write: False, capStore: False, potentialCapLoad: False } + 22720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ee0 +After delta: vaddr = 0x80000ee0 + 22720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:172 PC:0x1ffff0000000000000000000080000052 instr:0x0140006f iType:J [doCommitNormalInst [0]] 2272 +instret:173 PC:0x1ffff0000000000000000000080000066 instr:0x0210055b iType:Cap [doCommitNormalInst [1]] 2272 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22730 : [doFinishMem] DTlbResp { resp: <'h0000000080001598,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001598, check_high: 'h000000000800015a0, check_inclusive: True } }, specBits: 'h000 } + 22730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ee0 o: 'h0000000080000ee0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ee0, write: False, capStore: False, potentialCapLoad: True } + 22730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ed8 +After delta: vaddr = 0x80000ed8 +instret:174 PC:0x1ffff000000000000000000008000006a instr:0xfca44023 iType:St [doCommitNormalInst [0]] 2273 +instret:175 PC:0x1ffff000000000000000000008000006e instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 2273 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22740 : [doFinishMem] DTlbResp { resp: <'h0000000080000ee0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ee0 o: 'h0000000080000ee0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ee0, check_high: 'h00000000080000ef0, check_inclusive: True } }, specBits: 'h000 } + 22740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ed8 o: 'h0000000080000ed8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ed8, write: False, capStore: False, potentialCapLoad: False } + 22740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:176 PC:0x1ffff0000000000000000000080000072 instr:0x52a50513 iType:Alu [doCommitNormalInst [0]] 2274 +instret:177 PC:0x1ffff0000000000000000000080000076 instr:0xf8a43c23 iType:St [doCommitNormalInst [1]] 2274 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22750 : [doFinishMem] DTlbResp { resp: <'h0000000080000ed8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ed8 o: 'h0000000080000ed8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ed8, check_high: 'h00000000080000ee0, check_inclusive: True } }, specBits: 'h000 } + 22750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000ed8, shiftedBE: tagged DataMemAccess , pcHash: 'h808e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ec0 +After delta: vaddr = 0x80000ec0 + 22750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ec0, write: False, capStore: False, potentialCapLoad: True } + 22760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } + 22760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h6 + 22760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef8 +After delta: vaddr = 0x80000ef8 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22770 : [doFinishMem] DTlbResp { resp: <'h0000000080000ec0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ec0, check_high: 'h00000000080000ed0, check_inclusive: True } }, specBits: 'h000 } + 22770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000ec0, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } + 22770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 22780 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 22780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 22780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h7 + 22780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ec0 +After delta: vaddr = 0x80000ec0 +calling cycle + 22790 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 68 <= 0000000000000008000000001fffff44000000 + 22790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ec0, write: False, capStore: False, potentialCapLoad: True } +calling cycle +[RFile] wr_ 0: r 7a <= 0000000000000001000000001fffff44000000 + 22800 : [doFinishMem] DTlbResp { resp: <'h0000000080000ec0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ec0, check_high: 'h00000000080000ed0, check_inclusive: True } }, specBits: 'h000 } + 22800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000ec0, shiftedBE: tagged DataMemAccess , pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000078, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0d, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 72 <= 000000002000002c000000001fffff44000000 + 22810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + 22810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h0 + 22810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000078, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0d, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0b <= 000000002000002e000000001fffff44000000 +[ALU redirect - 1] 'h1ffff00000000000000000000800000e2; 'h0; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } + 22820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000078, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0d, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x00000078 +After delta: vaddr = 0x00000078 + 22820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22910 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000ef8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 22910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ea8 +After delta: vaddr = 0x80000ea8 + 22910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 74 <= 000000002000039c000000001fffff44000000 + 22920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ea8 o: 'h0000000080000ea8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ea8, write: True, capStore: False, potentialCapLoad: False } + 22920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22920 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 22920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 22920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ea0 +After delta: vaddr = 0x80000ea0 + 22920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 43 <= 00000000200003ac000000001fffff44000000 + 22930 : [doFinishMem] DTlbResp { resp: <'h0000000080000ea8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ea8 o: 'h0000000080000ea8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ea8, check_high: 'h00000000080000eb0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8036 } + 22930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ea0 o: 'h0000000080000ea0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ea0, write: True, capStore: False, potentialCapLoad: False } + 22930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } + 22930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 22930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } + 22930 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } + 22930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 22930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e8c +After delta: vaddr = 0x80000e8c + 22930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22940 : [doFinishMem] DTlbResp { resp: <'h0000000080000ea0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ea0 o: 'h0000000080000ea0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ea0, check_high: 'h00000000080000ea8, check_inclusive: True } }, specBits: 'h000 } + 22940 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 22940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e8c o: 'h0000000080000e8c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e8c, write: True, capStore: False, potentialCapLoad: False } + 22940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 22940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 22940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 22940 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 22940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 22940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e90 +After delta: vaddr = 0x80000e90 + 22940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22950 : [doFinishMem] DTlbResp { resp: <'h0000000080000e8c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e8c o: 'h0000000080000e8c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e8c, check_high: 'h00000000080000e90, check_inclusive: True } }, specBits: 'h000 } + 22950 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080001598, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22950 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 22950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e90 o: 'h0000000080000e90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e90, write: False, capStore: False, potentialCapLoad: True } + 22950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } + 22950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 22950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } + 22950 : [Ld resp] 'h12; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } + 22950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 22950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e8c +After delta: vaddr = 0x80000e8c +calling cycle + 22960 : [doFinishMem] DTlbResp { resp: <'h0000000080000e90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e90 o: 'h0000000080000e90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e90, check_high: 'h00000000080000ea0, check_inclusive: True } }, specBits: 'h000 } + 22960 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000ee0, shiftedBE: tagged DataMemAccess , pcHash: 'h808a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 22960 : [doRespLdMem] 'h12; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000000000000000000000001fffff44000000 + 22960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e8c o: 'h0000000080000e8c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e8c, write: False, capStore: False, potentialCapLoad: False } + 22960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 22960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 22960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 22960 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } + 22960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +calling cycle + 22970 : [doFinishMem] DTlbResp { resp: <'h0000000080000e8c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e8c o: 'h0000000080000e8c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e8c, check_high: 'h00000000080000e90, check_inclusive: True } }, specBits: 'h000 } + 22970 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000e90, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22970 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7d <= 0000000000000000000000001fffff44000000 + 22970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + 22970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 22970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + 22970 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } + 22970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 22980 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000000000000000000001fffff44000000 + 22980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } + 22980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ee0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h806a } + 22990 : [doRespLdForward] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 76 <= 40000000000000000000ffff1fffff44000000 + 22990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 22990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 22990 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } + 22990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } +calling cycle +[RFile] wr_ 1: r 65 <= 0000000000000000000000001ffff800080000 + 23000 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000e8c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23000 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000000000000000000001fffff44000000 + 23000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 23000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 23000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000ee0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806a } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080001598, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23010 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 0000000000000001000000001fffff44000000 + 23010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000ee0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806a } + 23010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000ee0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 23010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ec0 +After delta: vaddr = 0x80000ec0 + 23010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23020 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000e90, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[RFile] wr_ 0: r 7b <= 40000000000000000000ffff1fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000eb8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8076 } + 23020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ec0, write: True, capStore: True, potentialCapLoad: True } + 23020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ed8 +After delta: vaddr = 0x80000ed8 + 23020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000eb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } +instret:178 PC:0x1ffff000000000000000000008000007a instr:0x0000610c iType:Ld [doCommitNormalInst [0]] 2302 +instret:179 PC:0x1ffff000000000000000000008000007c instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 2302 +calling cycle +[RFile] wr_ 1: r 71 <= 0000000020000568000000001fffff44000000 + 23030 : [doFinishMem] DTlbResp { resp: <'h0000000080000ec0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ec0, check_high: 'h00000000080000ed0, check_inclusive: True } }, specBits: 'h000 } + 23030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800015a0 o: 'h00000000800015a0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ed8 o: 'h0000000080000ed8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ed8, write: True, capStore: False, potentialCapLoad: False } + 23030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000eb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } + 23030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 23030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ec0 +After delta: vaddr = 0x80000ec0 + 23030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:180 PC:0x1ffff0000000000000000000080000080 instr:0x52450513 iType:Alu [doCommitNormalInst [0]] 2303 +calling cycle + 23040 : [doFinishMem] DTlbResp { resp: <'h0000000080000ed8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ed8 o: 'h0000000080000ed8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ed8, check_high: 'h00000000080000ee0, check_inclusive: True } }, specBits: 'h000 } + 23040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h00000000000000020 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ec0, write: True, capStore: False, potentialCapLoad: True } + 23040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e90 +After delta: vaddr = 0x80000e90 +instret:181 PC:0x1ffff0000000000000000000080000084 instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 2304 +calling cycle + 23050 : [doFinishMem] DTlbResp { resp: <'h0000000080000ec0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ec0, check_high: 'h00000000080000ed0, check_inclusive: True } }, specBits: 'h000 } + 23050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e90 o: 'h0000000080000e90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e90, write: True, capStore: False, potentialCapLoad: True } +instret:182 PC:0x1ffff0000000000000000000080000086 instr:0xfaa43c23 iType:St [doCommitNormalInst [0]] 2305 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000ee0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 23060 : [doFinishMem] DTlbResp { resp: <'h0000000080000e90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e90 o: 'h0000000080000e90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e90, check_high: 'h00000000080000ea0, check_inclusive: True } }, specBits: 'h000 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000ed8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } +instret:183 PC:0x1ffff000000000000000000008000008a instr:0xfc04250f iType:Ld [doCommitNormalInst [0]] 2307 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 23460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ed8 +After delta: vaddr = 0x80000ed8 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ed8 o: 'h0000000080000ed8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ed8, write: False, capStore: False, potentialCapLoad: False } + 23470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23480 : [doFinishMem] DTlbResp { resp: <'h0000000080000ed8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ed8 o: 'h0000000080000ed8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ed8, check_high: 'h00000000080000ee0, check_inclusive: True } }, specBits: 'h000 } + 23480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000ed8, shiftedBE: tagged DataMemAccess , pcHash: 'h808e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ec0 +After delta: vaddr = 0x80000ec0 + 23480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 23490 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000000020000568000000001fffff44000000 + 23490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ec0, write: False, capStore: False, potentialCapLoad: True } + 23490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef8 +After delta: vaddr = 0x80000ef8 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000ed8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23500 : [doFinishMem] DTlbResp { resp: <'h0000000080000ec0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ec0, check_high: 'h00000000080000ed0, check_inclusive: True } }, specBits: 'h000 } + 23500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000ec0, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } + 23500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23510 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 23510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 23510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 23510 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } + 23510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ec0 +After delta: vaddr = 0x80000ec0 + 23510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } +instret:184 PC:0x1ffff000000000000000000008000008e instr:0xfb843583 iType:Ld [doCommitNormalInst [0]] 2351 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7b <= 40000000200005680000ffff1fffff44000000 + 23520 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7d <= 0000000000000000000000001fffff44000000 + 23520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000000800015a0 o: 'h00000000800015a0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ec0, write: True, capStore: True, potentialCapLoad: True } + 23520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } + 23520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } + 23520 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } + 23520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ec0 +After delta: vaddr = 0x80000ec0 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7a <= 0000000000000001000000001fffff44000000 + 23530 : [doFinishMem] DTlbResp { resp: <'h0000000080000ec0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ec0, check_high: 'h00000000080000ed0, check_inclusive: True } }, specBits: 'h000 } + 23530 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 68 <= 0000000000000008000000001fffff44000000 + 23530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ec0, write: False, capStore: False, potentialCapLoad: True } + 23530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:185 PC:0x1ffff0000000000000000000080000092 instr:0x20b5055b iType:Cap [doCommitNormalInst [0]] 2353 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 72 <= 000000002000002c000000001fffff44000000 + 23540 : [doFinishMem] DTlbResp { resp: <'h0000000080000ec0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ec0, check_high: 'h00000000080000ed0, check_inclusive: True } }, specBits: 'h000 } + 23540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ea8 +After delta: vaddr = 0x80000ea8 + 23540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:186 PC:0x1ffff0000000000000000000080000096 instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 2354 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0b <= 000000002000002e000000001fffff44000000 +[RFile] wr_ 1: r 74 <= 000000002000039c000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000ec0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 23550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ea8 o: 'h0000000080000ea8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ea8, write: True, capStore: False, potentialCapLoad: False } + 23550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ec0 +After delta: vaddr = 0x80000ec0 + 23550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 65 <= 0000000000000000000000001ffff800080000 +[RFile] wr_ 1: r 43 <= 00000000200003ac000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23560 : [doFinishMem] DTlbResp { resp: <'h0000000080000ea8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ea8 o: 'h0000000080000ea8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ea8, check_high: 'h00000000080000eb0, check_inclusive: True } }, specBits: 'h000 } + 23560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h00000000000000020 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ec0, write: True, capStore: False, potentialCapLoad: True } + 23560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ea0 +After delta: vaddr = 0x80000ea0 + 23560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23570 : [doFinishMem] DTlbResp { resp: <'h0000000080000ec0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ec0, check_high: 'h00000000080000ed0, check_inclusive: True } }, specBits: 'h000 } + 23570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ea0 o: 'h0000000080000ea0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ea0, write: True, capStore: False, potentialCapLoad: False } + 23570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e8c +After delta: vaddr = 0x80000e8c + 23570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 23580 : [doFinishMem] DTlbResp { resp: <'h0000000080000ea0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ea0 o: 'h0000000080000ea0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ea0, check_high: 'h00000000080000ea8, check_inclusive: True } }, specBits: 'h000 } + 23580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e8c o: 'h0000000080000e8c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e8c, write: True, capStore: False, potentialCapLoad: False } + 23580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e90 +After delta: vaddr = 0x80000e90 + 23580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23590 : [doFinishMem] DTlbResp { resp: <'h0000000080000e8c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e8c o: 'h0000000080000e8c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e8c, check_high: 'h00000000080000e90, check_inclusive: True } }, specBits: 'h000 } + 23590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e90 o: 'h0000000080000e90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e90, write: False, capStore: False, potentialCapLoad: True } + 23590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e8c +After delta: vaddr = 0x80000e8c + 23590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23600 : [doFinishMem] DTlbResp { resp: <'h0000000080000e90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e90 o: 'h0000000080000e90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e90, check_high: 'h00000000080000ea0, check_inclusive: True } }, specBits: 'h000 } + 23600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000e90, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e8c o: 'h0000000080000e8c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e8c, write: False, capStore: False, potentialCapLoad: False } + 23600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e70 +After delta: vaddr = 0x80000e70 + 23600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23610 : [doFinishMem] DTlbResp { resp: <'h0000000080000e8c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e8c o: 'h0000000080000e8c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e8c, check_high: 'h00000000080000e90, check_inclusive: True } }, specBits: 'h000 } + 23610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000e8c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e70, write: False, capStore: False, potentialCapLoad: True } + 23610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 23610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h6 + 23610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ea8 +After delta: vaddr = 0x80000ea8 + 23610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23620 : [doFinishMem] DTlbResp { resp: <'h0000000080000e70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e70, check_high: 'h00000000080000e80, check_inclusive: True } }, specBits: 'h000 } + 23620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000e70, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23620 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 0000000000000001000000001fffff44000000 + 23620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ea8 o: 'h0000000080000ea8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ea8, write: False, capStore: False, potentialCapLoad: False } + 23620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ea0 +After delta: vaddr = 0x80000ea0 + 23620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } +calling cycle +calling cycle + 23640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 23640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +calling cycle +calling cycle + 23660 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000e70, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23700 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000e90, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 23700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23710 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 23710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 23710 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } + 23710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 23710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ec0 +After delta: vaddr = 0x80000ec0 + 23710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 23720 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: } } + 23720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ec0, write: False, capStore: False, potentialCapLoad: True } + 23720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000eb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } + 23720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 23720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000eb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 23720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 23720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef8 +After delta: vaddr = 0x80000ef8 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23730 : [doFinishMem] DTlbResp { resp: <'h0000000080000ec0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ec0, check_high: 'h00000000080000ed0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ed8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8086 } + 23730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000ec0, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 23730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } + 23730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 23730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 23730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 23730 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } + 23730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000ed8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8086 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23740 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 23740 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 23740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000ed8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8086 } + 23740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000ed8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8086 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 23740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ec0 +After delta: vaddr = 0x80000ec0 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ec0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8096 } + 23750 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23750 : [doRespLdForward] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 7d <= 40000000200005680000ffff1fffff44000000 + 23750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ec0, write: False, capStore: False, potentialCapLoad: True } + 23750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7a <= 0000000000000001000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000ec0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 23760 : [doFinishMem] DTlbResp { resp: <'h0000000080000ec0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ec0, check_high: 'h00000000080000ed0, check_inclusive: True } }, specBits: 'h000 } + 23760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000ec0, shiftedBE: tagged DataMemAccess , pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 23760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } + 23760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } + 23760 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } + 23760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000ec0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8096 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 72 <= 000000002000002c000000001fffff44000000 + 23770 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 68 <= 0000000000000008000000001fffff44000000 + 23770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000ec0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8096 } + 23770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000ec0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8096 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 23770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:187 PC:0x1ffff000000000000000000008000009a instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 2377 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0b <= 000000002000002e000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23780 : [doRespLdForward] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 7f <= 40000000200005680000ffff1fffff44000000 + 23780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ea8 +After delta: vaddr = 0x80000ea8 + 23780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 74 <= 000000002000039c000000001fffff44000000 + 23790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ea8 o: 'h0000000080000ea8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ea8, write: True, capStore: False, potentialCapLoad: False } + 23790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ec0 +After delta: vaddr = 0x80000ec0 + 23790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:188 PC:0x1ffff000000000000000000008000009e instr:0xfd843583 iType:Ld [doCommitNormalInst [0]] 2379 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 43 <= 00000000200003ac000000001fffff44000000 +[RFile] wr_ 1: r 65 <= 400000002000056815a0ffff1ffff8057015a0 + 23800 : [doFinishMem] DTlbResp { resp: <'h0000000080000ea8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ea8 o: 'h0000000080000ea8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ea8, check_high: 'h00000000080000eb0, check_inclusive: True } }, specBits: 'h000 } + 23800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000000800015a0 o: 'h0000000000000000 b: 'h00000000800015a0 t: 'h000000000800015c0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ec0, write: True, capStore: True, potentialCapLoad: True } + 23800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ea0 +After delta: vaddr = 0x80000ea0 + 23800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 23810 : [doFinishMem] DTlbResp { resp: <'h0000000080000ec0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ec0, check_high: 'h00000000080000ed0, check_inclusive: True } }, specBits: 'h000 } + 23810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ea0 o: 'h0000000080000ea0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ea0, write: True, capStore: False, potentialCapLoad: False } + 23810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e90 +After delta: vaddr = 0x80000e90 + 23810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:189 PC:0x1ffff00000000000000000000800000a2 instr:0x10b5055b iType:Cap [doCommitNormalInst [0]] 2381 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23820 : [doFinishMem] DTlbResp { resp: <'h0000000080000ea0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ea0 o: 'h0000000080000ea0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ea0, check_high: 'h00000000080000ea8, check_inclusive: True } }, specBits: 'h000 } + 23820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000000800015a0 o: 'h00000000800015a0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e90 o: 'h0000000080000e90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e90, write: True, capStore: True, potentialCapLoad: True } + 23820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e8c +After delta: vaddr = 0x80000e8c + 23820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:190 PC:0x1ffff00000000000000000000800000a6 instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 2382 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000ec0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 23830 : [doFinishMem] DTlbResp { resp: <'h0000000080000e90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e90 o: 'h0000000080000e90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e90, check_high: 'h00000000080000ea0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ec0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80a6 } + 23830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e8c o: 'h0000000080000e8c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e8c, write: True, capStore: False, potentialCapLoad: False } + 23830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e90 +After delta: vaddr = 0x80000e90 + 23830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ec0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23840 : [doFinishMem] DTlbResp { resp: <'h0000000080000e8c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e8c o: 'h0000000080000e8c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e8c, check_high: 'h00000000080000e90, check_inclusive: True } }, specBits: 'h000 } + 23840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e90 o: 'h0000000080000e90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e90, write: False, capStore: False, potentialCapLoad: True } + 23840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ec0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a6 } + 23840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ec0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 23840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e8c +After delta: vaddr = 0x80000e8c + 23840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23850 : [doFinishMem] DTlbResp { resp: <'h0000000080000e90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e90 o: 'h0000000080000e90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e90, check_high: 'h00000000080000ea0, check_inclusive: True } }, specBits: 'h000 } + 23850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e8c o: 'h0000000080000e8c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e8c, write: False, capStore: False, potentialCapLoad: False } + 23850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e70 +After delta: vaddr = 0x80000e70 + 23850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 23860 : [doFinishMem] DTlbResp { resp: <'h0000000080000e8c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e8c o: 'h0000000080000e8c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e8c, check_high: 'h00000000080000e90, check_inclusive: True } }, specBits: 'h000 } + 23860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000e8c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e70, write: False, capStore: False, potentialCapLoad: True } + 23860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ea8 +After delta: vaddr = 0x80000ea8 + 23860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 45 <= 00000000200003ac000000001fffff44000000 + 23870 : [doFinishMem] DTlbResp { resp: <'h0000000080000e70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e70, check_high: 'h00000000080000e80, check_inclusive: True } }, specBits: 'h000 } + 23870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000e70, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23870 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 0000000000000001000000001fffff44000000 + 23870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ea8 o: 'h0000000080000ea8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ea8, write: False, capStore: False, potentialCapLoad: False } + 23870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ea0 +After delta: vaddr = 0x80000ea0 + 23870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23880 : [doFinishMem] DTlbResp { resp: <'h0000000080000ea8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ea8 o: 'h0000000080000ea8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ea8, check_high: 'h00000000080000eb0, check_inclusive: True } }, specBits: 'h000 } + 23880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000ea8, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ea0 o: 'h0000000080000ea0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ea0, write: False, capStore: False, potentialCapLoad: False } + 23880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 23880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 23890 : [doFinishMem] DTlbResp { resp: <'h0000000080000ea0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ea0 o: 'h0000000080000ea0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ea0, check_high: 'h00000000080000ea8, check_inclusive: True } }, specBits: 'h000 } + 23890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000ea0, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23890 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 000000002000002e000000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23900 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 00000000200003c8000000001fffff44000000 + 23900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 23910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000eb8 +After delta: vaddr = 0x80000eb8 + 23910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000eb8 o: 'h0000000080000eb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000eb8, write: False, capStore: False, potentialCapLoad: False } + 23920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef8 +After delta: vaddr = 0x80000ef8 + 23920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23930 : [doFinishMem] DTlbResp { resp: <'h0000000080000eb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000eb8 o: 'h0000000080000eb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000eb8, check_high: 'h00000000080000ec0, check_inclusive: True } }, specBits: 'h000 } + 23930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000eb8, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } + 23930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ec0 +After delta: vaddr = 0x80000ec0 + 23930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000eb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23940 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 23940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h80c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ec0, write: False, capStore: False, potentialCapLoad: True } + 23940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000eb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 23940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000eb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 23940 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } + 23940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f00 +After delta: vaddr = 0x80000f00 + 23940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23950 : [doFinishMem] DTlbResp { resp: <'h0000000080000ec0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ec0, check_high: 'h00000000080000ed0, check_inclusive: True } }, specBits: 'h000 } + 23950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000ec0, shiftedBE: tagged DataMemAccess , pcHash: 'h80ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23950 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 0000000020000566000000001fffff44000000 + 23950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f00, write: False, capStore: False, potentialCapLoad: True } + 23950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 23950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 23950 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } } + 23950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f18 +After delta: vaddr = 0x80000f18 + 23950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca } +calling cycle +calling cycle + 23970 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 23970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca } + 23970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca } + 23970 : [Ld resp] 'h09; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } + 23970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 23980 : [doRespLdMem] 'h09; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: } } +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ec0 +After delta: vaddr = 0x80000ec0 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 24050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ec0, write: False, capStore: False, potentialCapLoad: True } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7a <= 0000000000000001000000001fffff44000000 + 24060 : [doFinishMem] DTlbResp { resp: <'h0000000080000ec0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ec0, check_high: 'h00000000080000ed0, check_inclusive: True } }, specBits: 'h000 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 72 <= 000000002000002c000000001fffff44000000 + 24070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0b <= 000000002000002e000000001fffff44000000 + 24080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ea8 +After delta: vaddr = 0x80000ea8 + 24080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 74 <= 000000002000039c000000001fffff44000000 + 24090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ea8 o: 'h0000000080000ea8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ea8, write: True, capStore: False, potentialCapLoad: False } + 24090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ea0 +After delta: vaddr = 0x80000ea0 + 24090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 43 <= 00000000200003ac000000001fffff44000000 + 24100 : [doFinishMem] DTlbResp { resp: <'h0000000080000ea8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ea8 o: 'h0000000080000ea8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ea8, check_high: 'h00000000080000eb0, check_inclusive: True } }, specBits: 'h000 } + 24100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ea0 o: 'h0000000080000ea0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ea0, write: True, capStore: False, potentialCapLoad: False } + 24100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e8c +After delta: vaddr = 0x80000e8c + 24100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 24110 : [doFinishMem] DTlbResp { resp: <'h0000000080000ea0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ea0 o: 'h0000000080000ea0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ea0, check_high: 'h00000000080000ea8, check_inclusive: True } }, specBits: 'h000 } + 24110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e8c o: 'h0000000080000e8c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e8c, write: True, capStore: False, potentialCapLoad: False } + 24110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e90 +After delta: vaddr = 0x80000e90 + 24110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24120 : [doFinishMem] DTlbResp { resp: <'h0000000080000e8c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e8c o: 'h0000000080000e8c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e8c, check_high: 'h00000000080000e90, check_inclusive: True } }, specBits: 'h000 } + 24120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e90 o: 'h0000000080000e90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e90, write: False, capStore: False, potentialCapLoad: True } + 24120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e8c +After delta: vaddr = 0x80000e8c + 24120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24130 : [doFinishMem] DTlbResp { resp: <'h0000000080000e90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e90 o: 'h0000000080000e90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e90, check_high: 'h00000000080000ea0, check_inclusive: True } }, specBits: 'h000 } + 24130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000e90, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e8c o: 'h0000000080000e8c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e8c, write: False, capStore: False, potentialCapLoad: False } + 24130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e70 +After delta: vaddr = 0x80000e70 + 24130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24140 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000e70, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 24140 : [doFinishMem] DTlbResp { resp: <'h0000000080000e8c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e8c o: 'h0000000080000e8c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e8c, check_high: 'h00000000080000e90, check_inclusive: True } }, specBits: 'h000 } + 24140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e70, write: False, capStore: False, potentialCapLoad: True } + 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 24140 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } + 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ea8 +After delta: vaddr = 0x80000ea8 + 24140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24150 : [doFinishMem] DTlbResp { resp: <'h0000000080000e70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e70, check_high: 'h00000000080000e80, check_inclusive: True } }, specBits: 'h000 } + 24150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000e70, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24150 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 02 <= 4000000000000000000000001fffff44000000 + 24150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ea8 o: 'h0000000080000ea8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ea8, write: False, capStore: False, potentialCapLoad: False } + 24150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24150 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 24150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 24150 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } + 24150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 24150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ea0 +After delta: vaddr = 0x80000ea0 + 24150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 24160 : [doFinishMem] DTlbResp { resp: <'h0000000080000ea8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ea8 o: 'h0000000080000ea8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ea8, check_high: 'h00000000080000eb0, check_inclusive: True } }, specBits: 'h000 } + 24160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000ea8, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24160 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: } } + 24160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ea0 o: 'h0000000080000ea0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ea0, write: False, capStore: False, potentialCapLoad: False } + 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 24160 : [Ld resp] 'h03; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 45 <= 00000000200003ac000000001fffff44000000 + 24170 : [doFinishMem] DTlbResp { resp: <'h0000000080000ea0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ea0 o: 'h0000000080000ea0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ea0, check_high: 'h00000000080000ea8, check_inclusive: True } }, specBits: 'h000 } + 24170 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000ec0, shiftedBE: tagged DataMemAccess , pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24170 : [doRespLdMem] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 24170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 24170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 24170 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } + 24170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24180 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000e8c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24180 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 40 <= 4000000000000000000000001fffff44000000 + 24180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + 24180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + 24180 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } + 24180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 24190 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 7f <= 400000002000056815a0ffff1ffff8057015a0 + 24190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000ec0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 24200 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 000000002000002e000000001fffff44000000 + 24200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e90 +After delta: vaddr = 0x80000e90 + 24200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 24210 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000ea0, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24210 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 0000000000000001000000001fffff44000000 + 24210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000000800015a0 o: 'h0000000000000000 b: 'h00000000800015a0 t: 'h000000000800015c0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e90 o: 'h0000000080000e90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e90, write: True, capStore: True, potentialCapLoad: True } +instret:191 PC:0x1ffff00000000000000000000800000aa instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 2421 +instret:192 PC:0x1ffff00000000000000000000800000ae instr:0x00004591 iType:Alu [doCommitNormalInst [1]] 2421 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24220 : [doFinishMem] DTlbResp { resp: <'h0000000080000e90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e90 o: 'h0000000080000e90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e90, check_high: 'h00000000080000ea0, check_inclusive: True } }, specBits: 'h000 } + 24220 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 00000000200003c8000000001fffff44000000 +instret:193 PC:0x1ffff00000000000000000000800000b0 instr:0x00000097 iType:Auipc [doCommitNormalInst [0]] 2422 +instret:194 PC:0x1ffff00000000000000000000800000b4 instr:0x032080e7 iType:Jr [doCommitNormalInst [1]] 2422 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e70 +After delta: vaddr = 0x80000e70 + 24230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:195 PC:0x1ffff00000000000000000000800000e2 instr:0x00007139 iType:Alu [doCommitNormalInst [0]] 2423 +instret:196 PC:0x1ffff00000000000000000000800000e4 instr:0x0000fc06 iType:St [doCommitNormalInst [1]] 2423 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 46 <= 4000008000000000000000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ea8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80e4 } + 24240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000020000000000 o: 'h0000020000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e70, write: True, capStore: True, potentialCapLoad: True } + 24240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000eb8 +After delta: vaddr = 0x80000eb8 + 24240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000ea8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 } +instret:197 PC:0x1ffff00000000000000000000800000e6 instr:0x0000f822 iType:St [doCommitNormalInst [0]] 2424 +instret:198 PC:0x1ffff00000000000000000000800000e8 instr:0x00000080 iType:Alu [doCommitNormalInst [1]] 2424 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000e90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 24250 : [doFinishMem] DTlbResp { resp: <'h0000000080000e70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e70, check_high: 'h00000000080000e80, check_inclusive: True } }, specBits: 'h000 } + 24250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000eb8 o: 'h0000000080000eb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000eb8, write: False, capStore: False, potentialCapLoad: False } + 24250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000ea8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 } + 24250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000ea8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ec0 +After delta: vaddr = 0x80000ec0 + 24250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:199 PC:0x1ffff00000000000000000000800000ea instr:0xfea44023 iType:St [doCommitNormalInst [0]] 2425 +instret:200 PC:0x1ffff00000000000000000000800000ee instr:0xfcb42e23 iType:St [doCommitNormalInst [1]] 2425 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000e8c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24260 : [doFinishMem] DTlbResp { resp: <'h0000000080000eb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000eb8 o: 'h0000000080000eb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000eb8, check_high: 'h00000000080000ec0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ea0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80e6 } + 24260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000eb8, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ec0, write: True, capStore: True, potentialCapLoad: True } + 24260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef8 +After delta: vaddr = 0x80000ef8 + 24260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000eb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7e <= 00000000200003c8000000001fffff44000000 + 24270 : [doFinishMem] DTlbResp { resp: <'h0000000080000ec0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ec0, check_high: 'h00000000080000ed0, check_inclusive: True } }, specBits: 'h000 } + 24270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } + 24270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000eb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 24270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000eb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 24270 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } + 24270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ec0 +After delta: vaddr = 0x80000ec0 + 24270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000ea0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000e70, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 24280 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 24280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h80c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24280 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 0000000020000566000000001fffff44000000 + 24280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ec0, write: False, capStore: False, potentialCapLoad: True } + 24280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000ea0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 } + 24280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000ea0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f00 +After delta: vaddr = 0x80000f00 + 24280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000ea8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24290 : [doFinishMem] DTlbResp { resp: <'h0000000080000ec0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ec0, check_high: 'h00000000080000ed0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000e90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80ea } + 24290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000ec0, shiftedBE: tagged DataMemAccess , pcHash: 'h80ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 24290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f00, write: False, capStore: False, potentialCapLoad: True } + 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 24290 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } } + 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001598 +After delta: vaddr = 0x80001598 + 24290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000e90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000ea0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f00,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f00, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 24300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f00, shiftedBE: tagged DataMemAccess , pcHash: 'h80d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24300 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0d <= 0000000000000008000000001fffff44000000 + 24300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001598, write: False, capStore: False, potentialCapLoad: False } + 24300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000e90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea } + 24300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000e90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 24300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f18 +After delta: vaddr = 0x80000f18 + 24300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000eb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24310 : [doFinishMem] DTlbResp { resp: <'h0000000080001598,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001598, check_high: 'h000000000800015a0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000e8c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80ee } + 24310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080001598, shiftedBE: tagged DataMemAccess , pcHash: 'h80c4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24310 : [doRespLdForward] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 42 <= 4000000000000000000000001fffff44000000 + 24310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } + 24310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } + 24310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } + 24310 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } + 24310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 24320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h80da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24320 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 0000000000000000000000001fffff44000000 + 24320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } + 24320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } + 24320 : [Ld resp] 'h09; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } } + 24320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f00 +After delta: vaddr = 0x80000f00 + 24320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24330 : [doRespLdMem] 'h09; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0e <= 0000000000000000000000001fffff44000000 + 24330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f00, write: True, capStore: True, potentialCapLoad: True } + 24330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + 24330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + 24330 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } + 24330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 24330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000e8c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False }, paddr: 'h0000000080001598, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f00,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f00, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 24340 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 00000000200000fc800000001fffff44000000 + 24340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: False } + 24340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000e8c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } + 24340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000e8c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 24340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f18, check_inclusive: True } }, specBits: 'h000 } + 24350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h80dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 24350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001598 +After delta: vaddr = 0x80001598 + 24350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } +calling cycle +calling cycle + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 24370 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 24380 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e90 +After delta: vaddr = 0x80000e90 + 24440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 24450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e90 o: 'h0000000080000e90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e90, write: False, capStore: False, potentialCapLoad: True } + 24450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e8c +After delta: vaddr = 0x80000e8c + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24460 : [doFinishMem] DTlbResp { resp: <'h0000000080000e90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e90 o: 'h0000000080000e90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e90, check_high: 'h00000000080000ea0, check_inclusive: True } }, specBits: 'h000 } + 24460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000e90, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e8c o: 'h0000000080000e8c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e8c, write: False, capStore: False, potentialCapLoad: False } + 24460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24470 : [doFinishMem] DTlbResp { resp: <'h0000000080000e8c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e8c o: 'h0000000080000e8c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e8c, check_high: 'h00000000080000e90, check_inclusive: True } }, specBits: 'h000 } + 24470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000e8c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 24470 : [Ld resp] 'h0a; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } + 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e70 +After delta: vaddr = 0x80000e70 + 24470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000e8c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24480 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 02 <= 400000002000056815a0ffff1ffff8057015a0 + 24480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e70, write: False, capStore: False, potentialCapLoad: True } + 24480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000e8c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f6 } + 24480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000e8c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f6 } + 24480 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 24480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ea8 +After delta: vaddr = 0x80000ea8 + 24480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000e90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 24490 : [doFinishMem] DTlbResp { resp: <'h0000000080000e70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e70, check_high: 'h00000000080000e80, check_inclusive: True } }, specBits: 'h000 } + 24490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000e70, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24490 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 0000000000000001000000001fffff44000000 + 24490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ea8 o: 'h0000000080000ea8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ea8, write: False, capStore: False, potentialCapLoad: False } + 24490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ea0 +After delta: vaddr = 0x80000ea0 + 24490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000e8c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24500 : [doFinishMem] DTlbResp { resp: <'h0000000080000ea8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ea8 o: 'h0000000080000ea8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ea8, check_high: 'h00000000080000eb0, check_inclusive: True } }, specBits: 'h000 } + 24500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000ea8, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ea0 o: 'h0000000080000ea0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ea0, write: False, capStore: False, potentialCapLoad: False } + 24500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 24500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 24500 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } + 24500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000ea8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } +instret:201 PC:0x1ffff00000000000000000000800000f2 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 2450 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 45 <= 00000000200003ac000000001fffff44000000 + 24510 : [doFinishMem] DTlbResp { resp: <'h0000000080000ea0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ea0 o: 'h0000000080000ea0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ea0, check_high: 'h00000000080000ea8, check_inclusive: True } }, specBits: 'h000 } + 24510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000ea0, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24510 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 40 <= 4000000000000000000000001fffff44000000 + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000ea8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000ea8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } + 24510 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e70 +After delta: vaddr = 0x80000e70 + 24510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000ea0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } +instret:202 PC:0x1ffff00000000000000000000800000f6 instr:0xfdc42583 iType:Ld [doCommitNormalInst [0]] 2451 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 46 <= 400000802000056815a0ffff1ffff8057015a0 + 24520 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 000000002000002e000000001fffff44000000 + 24520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800015a0 o: 'h0000000000000000 b: 'h00000200800015a0 t: 'h000000200800015c0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e70, write: True, capStore: True, potentialCapLoad: True } + 24520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000ea0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } + 24520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000ea0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } + 24520 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 24520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h0e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 24530 : [doFinishMem] DTlbResp { resp: <'h0000000080000e70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e70, check_high: 'h00000000080000e80, check_inclusive: True } }, specBits: 'h000 } + 24530 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 00000000200003c8000000001fffff44000000 + 24530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:203 PC:0x1ffff00000000000000000000800000fa instr:0x1ab5055b iType:Cap [doCommitNormalInst [0]] 2453 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff4c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ee8 +After delta: vaddr = 0x80000ee8 +instret:204 PC:0x1ffff00000000000000000000800000fe instr:0xfca44023 iType:St [doCommitNormalInst [0]] 2454 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000e70, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } +[ALU redirect - 0] 'h1ffff00000000000000000000800000b8; 'h0; InstTag { way: 'h0, ptr: 'h04, t: 'h08 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000e70, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80fe } + 24550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ee8 o: 'h0000000080000ee8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ee8, write: False, capStore: False, potentialCapLoad: False } + 24550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000e70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h04, t: 'h08 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000ea8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000e70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } + 24570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000e70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 24570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000e70 +After delta: vaddr = 0x80000e70 + 24660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000e70, write: False, capStore: False, potentialCapLoad: True } + 24670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ea8 +After delta: vaddr = 0x80000ea8 + 24670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24680 : [doFinishMem] DTlbResp { resp: <'h0000000080000e70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000e70, check_high: 'h00000000080000e80, check_inclusive: True } }, specBits: 'h000 } + 24680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000e70, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ea8 o: 'h0000000080000ea8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ea8, write: False, capStore: False, potentialCapLoad: False } + 24680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ea0 +After delta: vaddr = 0x80000ea0 + 24680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } +calling cycle + 24690 : [doFinishMem] DTlbResp { resp: <'h0000000080000ea8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ea8 o: 'h0000000080000ea8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ea8, check_high: 'h00000000080000eb0, check_inclusive: True } }, specBits: 'h000 } + 24690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000ea8, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000e70 o: 'h0000000080000e70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ea0 o: 'h0000000080000ea0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ea0, write: False, capStore: False, potentialCapLoad: False } + 24690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 24690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 24690 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } + 24690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000ea8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } +calling cycle +[RFile] wr_ 1: r 45 <= 00000000200003ac000000001fffff44000000 + 24700 : [doFinishMem] DTlbResp { resp: <'h0000000080000ea0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ea0 o: 'h0000000080000ea0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ea0, check_high: 'h00000000080000ea8, check_inclusive: True } }, specBits: 'h000 } + 24700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000ea0, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24700 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 40 <= 400000802000056815a0ffff1ffff8057015a0 + 24700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000ea8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } + 24700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000ea8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } + 24700 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 24700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000ea0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000e70, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 24710 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 000000002000002e000000001fffff44000000 + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000ea0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000ea0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } + 24710 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000ea8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24720 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 00000000200003c8000000001fffff44000000 + 24720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:205 PC:0x1ffff0000000000000000000080000102 instr:0xfc04250f iType:Ld [doCommitNormalInst [0]] 2472 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000ea0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef8 +After delta: vaddr = 0x80000ef8 + 24730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:206 PC:0x1ffff0000000000000000000080000106 instr:0x000070e2 iType:Ld [doCommitNormalInst [0]] 2473 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[ALU redirect - 1] 'h1ffff00000000000000000000800000b8; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } + 24740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } + 24740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ed8 +After delta: vaddr = 0x80000ed8 + 24740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:207 PC:0x1ffff0000000000000000000080000108 instr:0x00007442 iType:Ld [doCommitNormalInst [0]] 2474 +instret:208 PC:0x1ffff000000000000000000008000010a instr:0x00006121 iType:Alu [doCommitNormalInst [1]] 2474 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:209 PC:0x1ffff000000000000000000008000010c instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2476 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000eb8 +After delta: vaddr = 0x80000eb8 + 24810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000eb8 o: 'h0000000080000eb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000eb8, write: False, capStore: False, potentialCapLoad: False } + 24820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ec0 +After delta: vaddr = 0x80000ec0 + 24820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h0e, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24830 : [doFinishMem] DTlbResp { resp: <'h0000000080000eb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000eb8 o: 'h0000000080000eb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000eb8, check_high: 'h00000000080000ec0, check_inclusive: True } }, specBits: 'h000 } + 24830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000eb8, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800015a0 o: 'h0000000000000000 b: 'h00000200800015a0 t: 'h000000200800015c0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ec0, write: True, capStore: True, potentialCapLoad: True } + 24830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef8 +After delta: vaddr = 0x80000ef8 + 24830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000eb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 24840 : [doFinishMem] DTlbResp { resp: <'h0000000080000ec0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ec0, check_high: 'h00000000080000ed0, check_inclusive: True } }, specBits: 'h000 } + 24840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } + 24840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000eb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 24840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000eb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 24840 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } + 24840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24850 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 24850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h80c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24850 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 0000000020000566000000001fffff44000000 + 24850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000eb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 24860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 24860 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } } + 24860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001598 +After delta: vaddr = 0x80001598 + 24860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24870 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0d <= 0000000000000008000000001fffff44000000 + 24870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001598, write: False, capStore: False, potentialCapLoad: False } + 24870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ec0 +After delta: vaddr = 0x80000ec0 + 24870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:210 PC:0x1ffff00000000000000000000800000b8 instr:0xf9843583 iType:Ld [doCommitNormalInst [0]] 2487 +instret:211 PC:0x1ffff00000000000000000000800000bc instr:0xfaa44023 iType:St [doCommitNormalInst [1]] 2487 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24880 : [doFinishMem] DTlbResp { resp: <'h0000000080001598,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001598, check_high: 'h000000000800015a0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ec0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80bc } + 24880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080001598, shiftedBE: tagged DataMemAccess , pcHash: 'h80c4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ec0, write: False, capStore: False, potentialCapLoad: True } + 24880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f00 +After delta: vaddr = 0x80000f00 + 24880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24890 : [doFinishMem] DTlbResp { resp: <'h0000000080000ec0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ec0 o: 'h0000000080000ec0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ec0, check_high: 'h00000000080000ed0, check_inclusive: True } }, specBits: 'h000 } + 24890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000ec0, shiftedBE: tagged DataMemAccess , pcHash: 'h80ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 24890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f00, write: False, capStore: False, potentialCapLoad: True } + 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } + 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080001598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } + 24890 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False } } + 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f18 +After delta: vaddr = 0x80000f18 + 24890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000ec0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } +instret:212 PC:0x1ffff00000000000000000000800000c0 instr:0xfd843603 iType:Ld [doCommitNormalInst [0]] 2489 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f00,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f00, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 24900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f00, shiftedBE: tagged DataMemAccess , pcHash: 'h80d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24900 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0e <= 0000000000000000000000001fffff44000000 + 24900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } + 24900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000ec0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } + 24900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000ec0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 24900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 24900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0e, isFpuReg: False }, paddr: 'h0000000080001598, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 24910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h80da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24910 : [doRespLdForward] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 42 <= 400000802000056815a0ffff1ffff8057015a0 + 24910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: False } + 24910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } + 24910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } + 24910 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } + 24910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } +calling cycle +[RFile] wr_ 0: r 7e <= 00000000200003c8000000001fffff44000000 + 24920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f18, check_inclusive: True } }, specBits: 'h000 } + 24920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h80dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24920 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 0000000000000000000000001fffff44000000 + 24920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + 24920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + 24920 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } + 24920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f00 +After delta: vaddr = 0x80000f00 + 24920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } +instret:213 PC:0x1ffff00000000000000000000800000c4 instr:0x00006188 iType:Ld [doCommitNormalInst [0]] 2492 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 54 <= 0000000000000008000000001fffff44000000 + 24930 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 00000000200000fc800000001fffff44000000 + 24930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800015a0 o: 'h0000000000000000 b: 'h00000200800015a0 t: 'h000000200800015c0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f00, write: True, capStore: True, potentialCapLoad: True } + 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 24930 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } + 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001598 +After delta: vaddr = 0x80001598 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 24940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f00,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f00, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 24940 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5a <= 00000000200003e4000000001fffff44000000 + 24940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001598, write: True, capStore: False, potentialCapLoad: False } +instret:214 PC:0x1ffff00000000000000000000800000c6 instr:0x00009532 iType:Alu [doCommitNormalInst [0]] 2494 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24950 : [doFinishMem] DTlbResp { resp: <'h0000000080001598,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001598 o: 'h0000000080001598 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001598, check_high: 'h000000000800015a0, check_inclusive: True } }, specBits: 'h000 } + 24950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 53 <= 0000000000000000000000001fffff44000000 +[ALU redirect - 0] 'h1ffff00000000000000000000800003f2; 'h1; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } + 24960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x00000000 +After delta: vaddr = 0x00000000 + 24960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:215 PC:0x1ffff00000000000000000000800000c8 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2496 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001598, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80c8 } + 24970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001598, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c8 } +[ROB incorrectSpec] 'h1 ; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000ec0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 24980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001598, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c8 } + 24980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001598, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c8 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +instret:216 PC:0x1ffff00000000000000000000800000ca instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 2499 +instret:217 PC:0x1ffff00000000000000000000800000ce instr:0xfea44023 iType:St [doCommitNormalInst [1]] 2499 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f00, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f00, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80ce } + 25000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ce } +instret:218 PC:0x1ffff00000000000000000000800000d2 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2500 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ce } + 25010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ce } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 25010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f00 +After delta: vaddr = 0x80000f00 + 25100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f00, write: False, capStore: False, potentialCapLoad: True } + 25110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f18 +After delta: vaddr = 0x80000f18 + 25110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f00,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f00, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 25120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f00, shiftedBE: tagged DataMemAccess , pcHash: 'h80d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } + 25120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 25120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } +calling cycle + 25130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 25130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h80da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000eb0 o: 'h0000000080000eb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: False } + 25130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } + 25130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } + 25130 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } + 25130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } +calling cycle +[RFile] wr_ 1: r 7e <= 00000000200003c8000000001fffff44000000 + 25140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f18, check_inclusive: True } }, specBits: 'h000 } + 25140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h80dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25140 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 64 <= 400000802000056815a0ffff1ffff8057015a0 + 25140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + 25140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + 25140 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } + 25140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f00, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 25150 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 00000000200000fc800000001fffff44000000 + 25150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 25150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 25150 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } + 25150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25160 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5a <= 00000000200003e4000000001fffff44000000 +instret:219 PC:0x1ffff00000000000000000000800000d6 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 2516 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:220 PC:0x1ffff00000000000000000000800000da instr:0x000070a6 iType:Ld [doCommitNormalInst [0]] 2517 +calling cycle +[ALU redirect - 1] 'h1ffff00000000000000000000800003f2; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } +instret:221 PC:0x1ffff00000000000000000000800000dc instr:0x00007406 iType:Ld [doCommitNormalInst [0]] 2518 +instret:222 PC:0x1ffff00000000000000000000800000de instr:0x00006165 iType:Alu [doCommitNormalInst [1]] 2518 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:223 PC:0x1ffff00000000000000000000800000e0 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2520 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa4, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 25270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa4, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } + 25280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa4, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f34 +After delta: vaddr = 0x80000f34 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 25290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h83f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa4, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f34 o: 'h0000000080000f34 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f34, write: False, capStore: False, potentialCapLoad: False } + 25290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83f2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f34,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f34 o: 'h0000000080000f34 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f34, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } + 25300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f34, shiftedBE: tagged DataMemAccess , pcHash: 'h83f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83f2 } + 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83f2 } + 25300 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f34, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h3f0, localHist: 'h2aa, globalTaken: True, localTaken: True, pcIndex: 'h20b }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25310 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000000000000001fffff44000000 + 25310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f34, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83f6 } + 25310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f34, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83f6 } + 25310 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } + 25310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 25310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4f <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 25320 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4c <= 0000000000000000000000001fffff44000000 + 25320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: False, potentialCapLoad: False } + 25320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 25320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f34, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f34, check_inclusive: True } }, specBits: 'h000 } + 25330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } + 25330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb0, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 +instret:224 PC:0x1ffff00000000000000000000800003f2 instr:0xfd04258f iType:Ld [doCommitNormalInst [0]] 2533 +calling cycle + 25340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f34, check_inclusive: True } }, specBits: 'h000 } + 25340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h840e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } + 25340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:225 PC:0x1ffff00000000000000000000800003f6 instr:0xfa442603 iType:Ld [doCommitNormalInst [0]] 2534 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 60 <= 0000000000000000000000001fffff44000000 + 25350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 25350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8412 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25350 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5f <= 0000000000000000000000001fffff44000000 + 25350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x00000000 +After delta: vaddr = 0x00000000 + 25350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8412 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 58 <= 0000000000000000000000001fffff44000000 + 25360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h4, rVal1: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800015a0 o: 'h0000000000000000 b: 'h00000200800015a0 t: 'h000000200800015c0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000000000, write: True, capStore: True, potentialCapLoad: False } + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8412 } + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8412 } + 25360 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 25360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:226 PC:0x1ffff00000000000000000000800003fa instr:0x00000612 iType:Alu [doCommitNormalInst [0]] 2536 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa4, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25370 : [doFinishMem] DTlbResp { resp: <'h0000000000000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: False, capException: tagged Valid CSR_XCapCause { cheri_exc_reg: 'h0b, cheri_exc_code: cheriExcTagViolation }, check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h0b, check_low: 'h0000000000000000, check_high: 'h00000000000000010, check_inclusive: True } }, specBits: 'h000 } + 25370 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 0000000000000008000000001fffff44000000 + 25370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } + 25370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 25370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa4, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:227 PC:0x1ffff00000000000000000000800003fc instr:0x22c585db iType:Cap [doCommitNormalInst [0]] 2537 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f34, check_inclusive: True } }, specBits: 'h003 } + 25380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h8422 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } + 25380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa4, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f34 +After delta: vaddr = 0x80000f34 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_MMIO_issue] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000000000000, isMMIO: True, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8400 }; MMIOCRq { addr: 'h0000000000000000, func: tagged St , byteEn: , data: TaggedData { tag: True, data: }, loadTags: False } + 25390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h8426 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25390 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4b <= 0000000000000000000000001fffff44000000 + 25390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa4, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f34 o: 'h0000000080000f34 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f34, write: False, capStore: False, potentialCapLoad: False } + 25390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8426 } +calling cycle + 25400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f34,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f34 o: 'h0000000080000f34 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f34, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h002 } + 25400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f34, shiftedBE: tagged DataMemAccess , pcHash: 'h842a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8426 } + 25400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8426 } + 25400 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } + 25400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f34, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h842a } +calling cycle + 25410 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 67 <= 0000000000000000000000001fffff44000000 + 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f34, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h842a } + 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f34, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h842a } + 25410 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } + 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 25420 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6b <= 0000000000000000000000001fffff44000000 +2543: mmioPlatform.rl_tohost: 0x200800015a0 (= 2201170744736) +FAIL 1100585372368 diff --git a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.tst b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.tst new file mode 100644 index 0000000..247acdb --- /dev/null +++ b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.tst @@ -0,0 +1,4632 @@ +make -C ../../Tests/elf_to_hex +make[1]: Entering directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/TooobaTest/Toooba/Tests/elf_to_hex' +make[1]: 'elf_to_hex' is up to date. +make[1]: Leaving directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/TooobaTest/Toooba/Tests/elf_to_hex' +../../Tests/elf_to_hex/elf_to_hex ../../Tests/isa/testC Mem.hex +c_mem_load_elf: ../../Tests/isa/testC is a 64-bit ELF file +Section .text : addr 80000000 to addr 8000048c; size 0x 48c (= 1164) bytes +Section .sbss : addr 80001490 to addr 80001498; size 0x 8 (= 8) bytes +Section .bss : addr 80001498 to addr 80011498; size 0x 10000 (= 65536) bytes +Section .riscv.attributes: Ignored +Section .comment : Ignored +Section .symtab : Searching for addresses of '_start', 'exit' and 'tohost' symbols +Writing symbols to: symbol_table.txt + No 'exit' label found + No 'tohost' symbol found +Section .shstrtab : Ignored +Section .strtab : Ignored +Min addr: 80000000 (hex) +Max addr: 80011497 (hex) +Writing mem hex to file 'Mem.hex' +Subtracting 0x80000000 base from addresses +./exe_HW_sim +v1 +tohost +Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 2213 to 33554430. +1: top.soc_top.rl_reset_start_initial ... +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +11: Mem_Controller.set_addr_map: addr_base 0x80000000 addr_lim 0xc0000000 + SoC address map: + Boot ROM: 0x1000 .. 0x2000 + Mem0 Controller: 0x80000000 .. 0xc0000000 + UART0: 0xc0000000 .. 0xc0000080 +11: top.soc_top.rl_reset_complete_initial +calling cycle +================================================================ +Bluespec RISC-V standalone system simulation v1.2 +Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved. +================================================================ +INFO: watch_tohost 1, tohost_addr = 0x0, fromhost_addr = 0x0 +12: top.soc_top.method start (tohost 0, fromhost 0) +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +100: top.soc_top.rl_step_0, n = 0, do_release +100: top.soc_top do_release(restartRunning: True, to_host_addr: 0) +100: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0 +calling cycle +101: top.soc_top.rl_ctrl_req +101: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0 +101: top.soc_top do_release(restartRunning: True, to_host_addr: 0) +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000020 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle +[RFile] wr_ 1: r 40 <= 0000000000000400000000001fffff44000000 +calling cycle +[RFile] wr_ 0: r 41 <= 0000000000000408000000001fffff44000000 +instret:0 PC:0x1ffff0000000000000000000000001000 instr:0x00000297 iType:Auipc [doCommitNormalInst [0]] 167 +calling cycle +instret:1 PC:0x1ffff0000000000000000000000001004 instr:0x02028593 iType:Alu [doCommitNormalInst [0]] 168 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Csr, execFunc: tagged Alu Csrs, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Valid csrAddrMHARTID, scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle +[RFile] wr_ 0: r 42 <= 0000000000000000000000001fffff44000000 +calling cycle +instret:2 PC:0x1ffff0000000000000000000000001008 instr:0xf1402573 iType:Csr [doCommitSystemInst] 224 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling 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+calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 3340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 3350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000018, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x00001018 +After delta: vaddr = 0x00001018 +calling cycle + 3360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000018, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000000001000 o: 'h0000000000001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000001018, write: False, capStore: False, potentialCapLoad: False } +calling cycle + 3370 : [doFinishMem] DTlbResp { resp: <'h0000000000001018,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000001018, check_high: 'h00000000000001020, check_inclusive: True } }, specBits: 'h000 } +calling cycle +calling cycle +[doDeqLdQ_MMIO_issue] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid }; MMIOCRq { addr: 'h0000000000001018, func: tagged Ld , byteEn: , data: TaggedData { tag: , data: }, loadTags: False } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +[RFile] wr_ 3: r 43 <= 0000000020000000000000001fffff44000000 +[doDeqLdQ_MMIO_deq] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid }; TaggedData { tag: False, data: }; TaggedData { tag: False, data: } +calling cycle +instret:3 PC:0x1ffff000000000000000000000000100c instr:0x0182b283 iType:Ld [doCommitNormalInst [0]] 403 +calling cycle +calling cycle +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000000; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:4 PC:0x1ffff0000000000000000000000001010 instr:0x00028067 iType:Jr [doCommitNormalInst [0]] 408 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling 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cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00080000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipcc, execFunc: tagged Alu Add, capFunc: tagged CapModify tagged SpecialRW tagged TCC , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrPCC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h48, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h48, src2: tagged Valid 'h48, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000316 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 46 <= 0000000000020000000000001fffff44000000 +[RFile] wr_ 1: r 45 <= 40000000200000000000ffff1fffff44000000 +calling cycle +[RFile] wr_ 1: r 47 <= 0000000000020000400000001fffff44000000 +instret:5 PC:0x1ffff0000000000000000000080000000 instr:0x020000db iType:Auipcc [doCommitNormalInst [0]] 1155 +instret:6 PC:0x1ffff0000000000000000000080000004 instr:0x000802b7 iType:Alu [doCommitNormalInst [1]] 1155 +calling cycle +[RFile] wr_ 0: r 48 <= 0000000020000400000000001fffff44000000 +instret:7 PC:0x1ffff0000000000000000000080000008 instr:0x00002285 iType:Alu [doCommitNormalInst [0]] 1156 +calling cycle +[RFile] wr_ 0: r 4a <= 0000000020000004000000001fffff44000000 +[RFile] wr_ 1: r 49 <= 0000000020000400000000001fffff44000000 +instret:8 PC:0x1ffff000000000000000000008000000a instr:0x000002b2 iType:Alu [doCommitNormalInst [0]] 1157 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4b <= 0000000020000006000000001fffff44000000 +[ALU redirect - 1] 'h1ffff0000000000000000000080000326; 'h0; InstTag { way: 'h1, ptr: 'h05, t: 'h0b } + 11580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:9 PC:0x1ffff000000000000000000008000000c instr:0x2052815b iType:Cap [doCommitNormalInst [0]] 1158 +instret:10 PC:0x1ffff0000000000000000000080000010 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1158 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h05, t: 'h0b } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:11 PC:0x1ffff0000000000000000000080000014 instr:0x316080e7 iType:Jr [doCommitNormalInst [0]] 1160 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 12640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 12650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff8 +After delta: vaddr = 0x80000ff8 + 12650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffcee }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4c <= 00000000200003e8000000001fffff44000000 + 12660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000018 o: 'h0000000080000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: True, capStore: False, potentialCapLoad: False } + 12660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff0 +After delta: vaddr = 0x80000ff0 + 12660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4f <= 0000000020000400000000001fffff44000000 + 12670 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } + 12670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: True, capStore: False, potentialCapLoad: False } + 12670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffec, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fec +After delta: vaddr = 0x80000fec +instret:12 PC:0x1ffff0000000000000000000080000326 instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 1267 +calling cycle +[RFile] wr_ 0: r 50 <= 0000000000000000000000001fffff44000000 + 12680 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } + 12680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffec, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fec, write: True, capStore: False, potentialCapLoad: False } +instret:13 PC:0x1ffff0000000000000000000080000328 instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 1268 +calling cycle +[RFile] wr_ 0: r 52 <= 00000000200000cd000000001fffff44000000 + 12690 : [doFinishMem] DTlbResp { resp: <'h0000000080000fec,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fec, check_high: 'h00000000080000ff0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8328 } + 12690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } +instret:14 PC:0x1ffff000000000000000000008000032a instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 1269 +instret:15 PC:0x1ffff000000000000000000008000032c instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 1269 +calling cycle +[RFile] wr_ 1: r 53 <= 00000000200000cf000000001fffff44000000 +[ALU redirect - 1] 'h1ffff0000000000000000000080000022; 'h0; InstTag { way: 'h1, ptr: 'h09, t: 'h13 } + 12700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 12700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } + 12700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:16 PC:0x1ffff000000000000000000008000032e instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 1270 +instret:17 PC:0x1ffff0000000000000000000080000330 instr:0xfea42623 iType:St [doCommitNormalInst [1]] 1270 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h09, t: 'h13 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 12720 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000ff8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +instret:18 PC:0x1ffff0000000000000000000080000334 instr:0x00000097 iType:Auipc [doCommitNormalInst [0]] 1272 +instret:19 PC:0x1ffff0000000000000000000080000338 instr:0xcee080e7 iType:Jr [doCommitNormalInst [1]] 1272 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 13210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 13220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 13220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 54 <= 00000000200003cc000000001fffff44000000 + 13230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000033c o: 'h000000008000033c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 13230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 13230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 57 <= 00000000200003e8000000001fffff44000000 + 13240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 13240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } + 13240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 13240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:20 PC:0x1ffff0000000000000000000080000022 instr:0x00007159 iType:Alu [doCommitNormalInst [0]] 1324 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000456 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 13250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 13250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 13250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +instret:21 PC:0x1ffff0000000000000000000080000024 instr:0x0000f486 iType:St [doCommitNormalInst [0]] 1325 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 13260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 13260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +instret:22 PC:0x1ffff0000000000000000000080000026 instr:0x0000f0a2 iType:St [doCommitNormalInst [0]] 1326 +instret:23 PC:0x1ffff0000000000000000000080000028 instr:0x00001880 iType:Alu [doCommitNormalInst [1]] 1326 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 13270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 13270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h802e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 13270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:24 PC:0x1ffff000000000000000000008000002a instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1327 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00010000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5d <= 000000002000040e800000001fffff44000000 + 13280 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000000000000001fffff44000000 + 13280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001490 +After delta: vaddr = 0x80001490 + 13280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h027 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5e <= 0000000020000524000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 13290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: False, capStore: False, potentialCapLoad: False } + 13290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 13300 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h000 } + 13300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080001490, shiftedBE: tagged DataMemAccess , pcHash: 'h8042 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 13300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 13300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 13300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } +instret:25 PC:0x1ffff000000000000000000008000002e instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 1330 +calling cycle +[RFile] wr_ 0: r 5a <= 0000000000000001c00000001fffff44000000 +[RFile] wr_ 1: r 62 <= 0000000000004000000000001fffff44000000 + 13310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 13310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 13310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 13310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } + 13310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 13310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +calling cycle +[RFile] wr_ 0: r 63 <= 0000000000004000400000001fffff44000000 +[RFile] wr_ 1: r 5b <= 0000000000000000000000001fffff44000000 + 13320 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 60 <= 0000000000000000000000001fffff44000000 + 13320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +instret:26 PC:0x1ffff0000000000000000000080000032 instr:0x0000051d iType:Alu [doCommitNormalInst [0]] 1332 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 13330 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001490, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 13330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } +instret:27 PC:0x1ffff0000000000000000000080000034 instr:0x00009961 iType:Alu [doCommitNormalInst [0]] 1333 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000422 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 13340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:28 PC:0x1ffff0000000000000000000080000036 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1334 +instret:29 PC:0x1ffff000000000000000000008000003a instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1334 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 13350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 +instret:30 PC:0x1ffff000000000000000000008000003e instr:0x45650513 iType:Alu [doCommitNormalInst [0]] 1335 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 66 <= 40000000000000000000ffff1fffff44000000 + 13360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } + 13360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 68 <= 000000002000041b800000001fffff44000000 + 13370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h001 } + 13370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 13370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 69 <= 0000000020000524000000001fffff44000000 + 13380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } + 13380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001490 +After delta: vaddr = 0x80001490 +calling cycle +[RFile] wr_ 1: r 6c <= 000000002000041f000000001fffff44000000 + 13390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } + 13390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: False, capStore: False, potentialCapLoad: False } +calling cycle + 13400 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h001 } + 13400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080001490, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 13400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } +calling cycle + 13410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 13410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 13410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 14240 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000ff8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 14250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14250 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 14250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h832a } + 14260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +calling cycle + 14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } + 14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fec, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8330 } + 14280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } +calling cycle + 14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8024 } + 14300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } +calling cycle + 14310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } + 14310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +calling cycle +calling cycle + 14330 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f98, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 14760 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001490, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 14770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14770 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 14770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } + 14770 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } + 14770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 +calling cycle + 14780 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5f <= 0000000000000000000000001fffff44000000 + 14780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 14780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 14780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 14780 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } + 14780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080001490, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 14790 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6b <= 0000000000000000000000001fffff44000000 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } +instret:31 PC:0x1ffff0000000000000000000080000042 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 1480 +calling cycle +[RFile] wr_ 1: r 61 <= 0000000000000000000000001fffff44000000 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00010000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h027 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 15150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 15160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, data: TaggedData { tag: False, data: } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 62 <= 0000000000004000000000001fffff44000000 + 15170 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 60 <= 0000000000000000000000001fffff44000000 + 15170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000422 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 63 <= 0000000000004000400000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 15180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 66 <= 40000000000000000000ffff1fffff44000000 + 15190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } +instret:32 PC:0x1ffff0000000000000000000080000044 instr:0xfd843583 iType:Ld [doCommitNormalInst [0]] 1519 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000041c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 61 <= 0000000000000000000000001fffff44000000 + 15200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h001 } + 15200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 68 <= 000000002000041b800000001fffff44000000 + 15210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 15210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:33 PC:0x1ffff0000000000000000000080000048 instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 1521 +instret:34 PC:0x1ffff000000000000000000008000004a instr:0x000065c1 iType:Alu [doCommitNormalInst [1]] 1521 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6c <= 000000002000041f000000001fffff44000000 +[RFile] wr_ 1: r 69 <= 0000000020000524000000001fffff44000000 + 15220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } + 15220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001490 +After delta: vaddr = 0x80001490 + 15220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:35 PC:0x1ffff000000000000000000008000004c instr:0x00002585 iType:Alu [doCommitNormalInst [0]] 1522 +instret:36 PC:0x1ffff000000000000000000008000004e instr:0x00b57463 iType:Br [doCommitNormalInst [1]] 1522 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6d <= 0000000020000526000000001fffff44000000 + 15230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 15230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: False, capStore: False, potentialCapLoad: False } + 15230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 15230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:37 PC:0x1ffff0000000000000000000080000052 instr:0x0140006f iType:J [doCommitNormalInst [0]] 1523 +instret:38 PC:0x1ffff0000000000000000000080000066 instr:0x0210055b iType:Cap [doCommitNormalInst [1]] 1523 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 15240 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h000 } + 15240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080001490, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 15240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } + 15240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 15240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } +instret:39 PC:0x1ffff000000000000000000008000006a instr:0xfca44023 iType:St [doCommitNormalInst [0]] 1524 +instret:40 PC:0x1ffff000000000000000000008000006e instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1524 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 15250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h808a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 15250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 15250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 15250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 15250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 15250 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } + 15250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 15250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:41 PC:0x1ffff0000000000000000000080000072 instr:0x42250513 iType:Alu [doCommitNormalInst [0]] 1525 +instret:42 PC:0x1ffff0000000000000000000080000076 instr:0xf8a43c23 iType:St [doCommitNormalInst [1]] 1525 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 15260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h808e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 15260 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6b <= 0000000000000000000000001fffff44000000 + 15260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 15260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 15260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080001490, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 15270 : [doRespLdForward] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 70 <= 40000000000000000000ffff1fffff44000000 + 15270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + 15270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } + 15270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 15270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 15270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 15280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 15280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 15280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 15280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 15280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } +instret:43 PC:0x1ffff000000000000000000008000007a instr:0x0000610c iType:Ld [doCommitNormalInst [0]] 1528 +instret:44 PC:0x1ffff000000000000000000008000007c instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1528 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15290 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f58, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[RFile] wr_ 1: r 6e <= 0000000020000526000000001fffff44000000 + 15290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 15290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 15290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001498 o: 'h0000000080001498 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 15290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 15290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 15290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 +instret:45 PC:0x1ffff0000000000000000000080000080 instr:0x41c50513 iType:Alu [doCommitNormalInst [0]] 1529 +calling cycle + 15300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 15300 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 + 15300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } +instret:46 PC:0x1ffff0000000000000000000080000084 instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 1530 +calling cycle +[RFile] wr_ 0: r 79 <= 0000000000000002800000001fffff44000000 + 15310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 15310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 15310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } +instret:47 PC:0x1ffff0000000000000000000080000086 instr:0xfaa43c23 iType:St [doCommitNormalInst [0]] 1531 +calling cycle +[RFile] wr_ 1: r 7a <= 000000002000002c000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 15320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + 15320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h0 +calling cycle +[RFile] wr_ 0: r 7b <= 000000002000002e000000001fffff44000000 +[ALU redirect - 0] 'h1ffff00000000000000000000800000e2; 'h0; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } +instret:48 PC:0x1ffff000000000000000000008000008a instr:0xfc04250f iType:Ld [doCommitNormalInst [0]] 1533 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +calling cycle +calling cycle +calling cycle + 15380 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f98, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 15390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15390 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 15390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8026 } + 15400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } +calling cycle + 15410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } + 15410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 15410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h802a } + 15420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } +calling cycle + 15430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } + 15430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h3 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 15830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 15830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7c <= 00000000200003bc000000001fffff44000000 + 15840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } + 15840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 15840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7f <= 00000000200003cc000000001fffff44000000 + 15850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 15850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } + 15850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + 15850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 15860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: True, capStore: False, potentialCapLoad: False } + 15860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 15860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 15870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } + 15870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c +calling cycle + 15880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 15880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 15880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False } + 15880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } +calling cycle + 15890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 15890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +calling cycle + 15900 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000 +calling cycle + 15910 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f10, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 16060 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f58, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 16070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16070 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 16070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } + 16070 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } + 16070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 +calling cycle + 16080 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000000000000000000001fffff44000000 + 16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 16080 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 16090 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000000000000000000001fffff44000000 + 16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + 16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + 16090 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 16090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16100 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000000000000000000001fffff44000000 + 16100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } + 16100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 16100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 16100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 16100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8036 } + 16110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } +calling cycle + 16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } + 16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h806a } + 16130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806a } +calling cycle + 16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806a } + 16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8076 } + 16150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } +calling cycle + 16160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } + 16160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 16450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 16460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h808e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 16460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 16460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16470 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000020000526000000001fffff44000000 + 16470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + 16470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 16480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 16480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 16480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 16490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 16490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 16490 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 16490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 16490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } +instret:49 PC:0x1ffff000000000000000000008000008e instr:0xfb843583 iType:Ld [doCommitNormalInst [0]] 1649 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 72 <= 40000000200005260000ffff1fffff44000000 + 16500 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000000000000000000001fffff44000000 + 16500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001498 o: 'h0000000080001498 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } + 16500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } + 16500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } + 16500 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } + 16500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 0000000000000002800000001fffff44000000 + 16510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 16510 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 + 16510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + 16510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:50 PC:0x1ffff0000000000000000000080000092 instr:0x20b5055b iType:Cap [doCommitNormalInst [0]] 1651 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7a <= 000000002000002c000000001fffff44000000 + 16520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 16520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 16520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:51 PC:0x1ffff0000000000000000000080000096 instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 1652 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7b <= 000000002000002e000000001fffff44000000 +[RFile] wr_ 1: r 7c <= 00000000200003bc000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 16530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } + 16530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 16530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 76 <= 0000000000000000000000001ffff800000000 +[RFile] wr_ 1: r 7f <= 00000000200003cc000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 16540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 16540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h00000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: True } + 16540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 16540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 16550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } + 16550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + 16550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 16560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: True, capStore: False, potentialCapLoad: False } + 16560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 16560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 16570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } + 16570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + 16570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 16580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False } + 16580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef0 +After delta: vaddr = 0x80000ef0 + 16580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 16590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 16590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True } + 16590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 16590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h4 + 16590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 16590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 16600 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 16600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16600 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000 + 16600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } + 16600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 16600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } +calling cycle +calling cycle + 16620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 16620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +calling cycle +calling cycle + 16640 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000ef0, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16680 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f10, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 16680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16690 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 16690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 16690 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 16690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 16690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 16690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16700 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: } } + 16700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + 16700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } + 16700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 16700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 16700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 16700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8086 } + 16710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 16710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 16710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 16710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 16710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 16710 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } + 16710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8086 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 16720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 16720 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8086 } + 16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8086 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8096 } + 16730 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16730 : [doRespLdForward] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 74 <= 40000000200005260000ffff1fffff44000000 + 16730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + 16730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 79 <= 0000000000000002800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 16740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 16740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 16740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } + 16740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } + 16740 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } + 16740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8096 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7a <= 000000002000002c000000001fffff44000000 + 16750 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8096 } + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8096 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:52 PC:0x1ffff000000000000000000008000009a instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 1675 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7b <= 000000002000002e000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 16760 : [doRespLdForward] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 78 <= 40000000200005260000ffff1fffff44000000 + 16760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 16760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7c <= 00000000200003bc000000001fffff44000000 + 16770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } + 16770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 16770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:53 PC:0x1ffff000000000000000000008000009e instr:0xfd843583 iType:Ld [doCommitNormalInst [0]] 1677 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7f <= 00000000200003cc000000001fffff44000000 +[RFile] wr_ 1: r 76 <= 40000000200005261498ffff1ffff805261498 + 16780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 16780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001498 o: 'h0000000000000000 b: 'h0000000080001498 t: 'h00000000080001498 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } + 16780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 16780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 16790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } + 16790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 16790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:54 PC:0x1ffff00000000000000000000800000a2 instr:0x10b5055b iType:Cap [doCommitNormalInst [0]] 1679 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 16800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001498 o: 'h0000000080001498 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: True, potentialCapLoad: True } + 16800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + 16800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:55 PC:0x1ffff00000000000000000000800000a6 instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 1680 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 16810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80a6 } + 16810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: True, capStore: False, potentialCapLoad: False } + 16810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 16810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 16820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } + 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a6 } + 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + 16820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 16830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 16830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False } + 16830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef0 +After delta: vaddr = 0x80000ef0 + 16830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 16840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 16840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 16840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True } + 16840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 16840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 02 <= 00000000200003cc000000001fffff44000000 + 16850 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 16850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16850 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000 + 16850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } + 16850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 16850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 16860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 16860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 16860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } + 16860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 16860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 16870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 16870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 16870 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 000000002000002e000000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16880 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 00000000200003e8000000001fffff44000000 + 16880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 16890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } + 16900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 16900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 16910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 16910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 16910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 16920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h80c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + 16920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 16920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 16920 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 16920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 16920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 16930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 16930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16930 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 0000000020000524000000001fffff44000000 + 16930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } + 16930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 16930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 16930 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 16930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 16930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca } +calling cycle +calling cycle + 16950 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 16950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca } + 16950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca } + 16950 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 16950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 16960 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: } } +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 17030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 0000000000000002800000001fffff44000000 + 17040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7a <= 000000002000002c000000001fffff44000000 + 17050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7b <= 000000002000002e000000001fffff44000000 + 17060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 17060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7c <= 00000000200003bc000000001fffff44000000 + 17070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } + 17070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 17070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7f <= 00000000200003cc000000001fffff44000000 + 17080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 17080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } + 17080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + 17080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 17090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 17090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: True, capStore: False, potentialCapLoad: False } + 17090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 17090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 17100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } + 17100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + 17100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 17110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False } + 17110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef0 +After delta: vaddr = 0x80000ef0 + 17110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17120 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000ef0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 17120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 17120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True } + 17120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 17120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 17120 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 17120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 17120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17130 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 17130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17130 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 0a <= 4000000000000000000000001fffff44000000 + 17130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } + 17130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17130 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 17130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17130 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 17130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 17130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 17130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 17140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 17140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 17140 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: } } + 17140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } + 17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17140 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } + 17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 02 <= 00000000200003cc000000001fffff44000000 + 17150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 17150 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17150 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17150 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } + 17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17160 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 17160 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 43 <= 4000000000000000000000001fffff44000000 + 17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + 17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + 17160 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 17170 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 78 <= 40000000200005261498ffff1ffff805261498 + 17170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 17180 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 000000002000002e000000001fffff44000000 + 17180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 17180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 17190 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 17190 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000 + 17190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001498 o: 'h0000000000000000 b: 'h0000000080001498 t: 'h00000000080001498 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: True, potentialCapLoad: True } +instret:56 PC:0x1ffff00000000000000000000800000aa instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 1719 +instret:57 PC:0x1ffff00000000000000000000800000ae instr:0x000045a9 iType:Alu [doCommitNormalInst [1]] 1719 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 17200 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 00000000200003e8000000001fffff44000000 +instret:58 PC:0x1ffff00000000000000000000800000b0 instr:0x00000097 iType:Auipc [doCommitNormalInst [0]] 1720 +instret:59 PC:0x1ffff00000000000000000000800000b4 instr:0x032080e7 iType:Jr [doCommitNormalInst [1]] 1720 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef0 +After delta: vaddr = 0x80000ef0 + 17210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:60 PC:0x1ffff00000000000000000000800000e2 instr:0x00007139 iType:Alu [doCommitNormalInst [0]] 1721 +instret:61 PC:0x1ffff00000000000000000000800000e4 instr:0x0000fc06 iType:St [doCommitNormalInst [1]] 1721 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 44 <= 4000014000000000000000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80e4 } + 17220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050000000000 o: 'h0000050000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: True, capStore: True, potentialCapLoad: True } + 17220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 17220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 } +instret:62 PC:0x1ffff00000000000000000000800000e6 instr:0x0000f822 iType:St [doCommitNormalInst [0]] 1722 +instret:63 PC:0x1ffff00000000000000000000800000e8 instr:0x00000080 iType:Alu [doCommitNormalInst [1]] 1722 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 17230 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 17230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } + 17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 } + 17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 17230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:64 PC:0x1ffff00000000000000000000800000ea instr:0xfea44023 iType:St [doCommitNormalInst [0]] 1723 +instret:65 PC:0x1ffff00000000000000000000800000ee instr:0xfcb42e23 iType:St [doCommitNormalInst [1]] 1723 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f0c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80e6 } + 17240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } + 17240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 17240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } +calling cycle + 17250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 } +calling cycle + 17260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 17260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 17260 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 17260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 17270 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 17270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 } + 17270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80ea } + 17280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea } +calling cycle + 17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea } + 17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f0c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80ee } + 17300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f0c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } +calling cycle + 17310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f0c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } + 17310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f0c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 17330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 17340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } + 17340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 17350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False } + 17350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 17360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 17360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 17360 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 17360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef0 +After delta: vaddr = 0x80000ef0 + 17360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f0c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17370 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 0a <= 40000000200005261498ffff1ffff805261498 + 17370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True } + 17370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f0c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f6 } + 17370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f0c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f6 } + 17370 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } + 17370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 17370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 17380 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 17380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17380 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000 + 17380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } + 17380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 17380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f0c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 17390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } + 17390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17390 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } + 17390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } +instret:66 PC:0x1ffff00000000000000000000800000f2 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1739 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 02 <= 00000000200003cc000000001fffff44000000 + 17400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 17400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17400 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 43 <= 4000000000000000000000001fffff44000000 + 17400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } + 17400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } + 17400 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 17400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef0 +After delta: vaddr = 0x80000ef0 + 17400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } +instret:67 PC:0x1ffff00000000000000000000800000f6 instr:0xfdc42583 iType:Ld [doCommitNormalInst [0]] 1740 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 44 <= 40000140200005261498ffff1ffff805261498 + 17410 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 000000002000002e000000001fffff44000000 + 17410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050080001498 o: 'h0000000000000000 b: 'h0000050080001498 t: 'h00000050080001498 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: True, capStore: True, potentialCapLoad: True } + 17410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } + 17410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } + 17410 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 17410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17420 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 17420 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 00000000200003e8000000001fffff44000000 + 17420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:68 PC:0x1ffff00000000000000000000800000fa instr:0x1ab5055b iType:Cap [doCommitNormalInst [0]] 1742 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 49 <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 4a <= 0000000000000000000000001fffff44000000 + 17430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x00000000 +After delta: vaddr = 0x00000000 + 17430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:69 PC:0x1ffff00000000000000000000800000fe instr:0xfca44023 iType:St [doCommitNormalInst [0]] 1743 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4d <= 0000000000000000400000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000ef0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } +[ALU redirect - 0] 'h1ffff00000000000000000000800000b8; 'h0; InstTag { way: 'h0, ptr: 'h04, t: 'h08 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ef0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80fe } + 17440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000000000, write: True, capStore: False, potentialCapLoad: False } + 17440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 17440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000ef0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h04, t: 'h08 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000ef0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000ef0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef0 +After delta: vaddr = 0x80000ef0 + 17550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True } + 17560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 17560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17570 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 17570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } + 17570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 17570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } +calling cycle + 17580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 17580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } + 17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17580 : [Ld resp] 'h15; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } + 17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } +calling cycle +[RFile] wr_ 1: r 02 <= 00000000200003cc000000001fffff44000000 + 17590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 17590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17590 : [doRespLdMem] 'h15; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 43 <= 40000140200005261498ffff1ffff805261498 + 17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } + 17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } + 17590 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000ef0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 17600 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 000000002000002e000000001fffff44000000 + 17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } + 17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } + 17600 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17610 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 00000000200003e8000000001fffff44000000 +instret:70 PC:0x1ffff0000000000000000000080000102 instr:0xfc04250f iType:Ld [doCommitNormalInst [0]] 1761 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:71 PC:0x1ffff0000000000000000000080000106 instr:0x000070e2 iType:Ld [doCommitNormalInst [0]] 1762 +calling cycle +[ALU redirect - 1] 'h1ffff00000000000000000000800000b8; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } +instret:72 PC:0x1ffff0000000000000000000080000108 instr:0x00007442 iType:Ld [doCommitNormalInst [0]] 1763 +instret:73 PC:0x1ffff000000000000000000008000010a instr:0x00006121 iType:Alu [doCommitNormalInst [1]] 1763 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:74 PC:0x1ffff000000000000000000008000010c instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 1765 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 17720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } + 17730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 17730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 17740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050080001498 o: 'h0000000000000000 b: 'h0000050080001498 t: 'h00000050080001498 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } + 17740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 17740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 17750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 17750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 17750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 17750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 17750 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 17750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 17760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h80c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17760 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 0000000020000524000000001fffff44000000 + 17760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 17770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 17770 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 17770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001490 +After delta: vaddr = 0x80001490 + 17770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17780 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 0000000000000000000000001fffff44000000 + 17780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: False, capStore: False, potentialCapLoad: False } + 17780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 17780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:75 PC:0x1ffff00000000000000000000800000b8 instr:0xf9843583 iType:Ld [doCommitNormalInst [0]] 1778 +instret:76 PC:0x1ffff00000000000000000000800000bc instr:0xfaa44023 iType:St [doCommitNormalInst [1]] 1778 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17790 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80bc } + 17790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080001490, shiftedBE: tagged DataMemAccess , pcHash: 'h80c4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + 17790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 17790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 17800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 17800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } + 17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } + 17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } + 17800 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } + 17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 17800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } +instret:77 PC:0x1ffff00000000000000000000800000c0 instr:0xfd843603 iType:Ld [doCommitNormalInst [0]] 1780 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 17810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h80d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17810 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4e <= 0000000000000000000000001fffff44000000 + 17810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } + 17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 17810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080001490, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 17820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h80da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17820 : [doRespLdForward] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 51 <= 40000140200005261498ffff1ffff805261498 + 17820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } + 17820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } + 17820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } + 17820 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } + 17820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } +calling cycle +[RFile] wr_ 0: r 4f <= 00000000200003e8000000001fffff44000000 + 17830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 17830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h80dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17830 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4c <= 0000000000000000000000001fffff44000000 + 17830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + 17830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + 17830 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } + 17830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 17830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } +instret:78 PC:0x1ffff00000000000000000000800000c4 instr:0x00006188 iType:Ld [doCommitNormalInst [0]] 1783 +calling cycle +[RFile] wr_ 1: r 08 <= 0000000000000000000000001fffff44000000 + 17840 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 55 <= 00000000200000cf000000001fffff44000000 + 17840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050080001498 o: 'h0000000000000000 b: 'h0000050080001498 t: 'h00000050080001498 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: True, potentialCapLoad: True } + 17840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 17840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 17840 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } + 17840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001490 +After delta: vaddr = 0x80001490 +calling cycle + 17850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 17850 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 56 <= 0000000020000400000000001fffff44000000 + 17850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: True, capStore: False, potentialCapLoad: False } +instret:79 PC:0x1ffff00000000000000000000800000c6 instr:0x00009532 iType:Alu [doCommitNormalInst [0]] 1785 +calling cycle + 17860 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h000 } +calling cycle +[ALU redirect - 0] 'h1ffff000000000000000000008000033c; 'h1; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } +instret:80 PC:0x1ffff00000000000000000000800000c8 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 1787 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001490, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80c8 } + 17880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001490, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c8 } +[ROB incorrectSpec] 'h1 ; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001490, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c8 } + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001490, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c8 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +instret:81 PC:0x1ffff00000000000000000000800000ca instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 1790 +instret:82 PC:0x1ffff00000000000000000000800000ce instr:0xfea44023 iType:St [doCommitNormalInst [1]] 1790 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80ce } + 17910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ce } +instret:83 PC:0x1ffff00000000000000000000800000d2 instr:0x0040006f iType:J [doCommitNormalInst [0]] 1791 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ce } + 17920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ce } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 17920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 18010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } + 18020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 18020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 18030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 18030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h80d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 18030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 18030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } +calling cycle + 18040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 18040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h80da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } + 18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } + 18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } + 18040 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } + 18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } +calling cycle +[RFile] wr_ 1: r 4f <= 00000000200003e8000000001fffff44000000 + 18050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 18050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h80dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18050 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 4c <= 40000140200005261498ffff1ffff805261498 + 18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + 18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + 18050 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } + 18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 18060 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 55 <= 00000000200000cf000000001fffff44000000 + 18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 18060 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } + 18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 18070 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 56 <= 0000000020000400000000001fffff44000000 +instret:84 PC:0x1ffff00000000000000000000800000d6 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1807 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:85 PC:0x1ffff00000000000000000000800000da instr:0x000070a6 iType:Ld [doCommitNormalInst [0]] 1808 +calling cycle +[ALU redirect - 1] 'h1ffff000000000000000000008000033c; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } +instret:86 PC:0x1ffff00000000000000000000800000dc instr:0x00007406 iType:Ld [doCommitNormalInst [0]] 1809 +instret:87 PC:0x1ffff00000000000000000000800000de instr:0x00006165 iType:Alu [doCommitNormalInst [1]] 1809 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:88 PC:0x1ffff00000000000000000000800000e0 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 1811 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000050 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd0 +After delta: vaddr = 0x80000fd0 + 18180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000045 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050080001498 o: 'h0000000000000000 b: 'h0000050080001498 t: 'h00000050080001498 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: True, capStore: True, potentialCapLoad: True } + 18190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc8 +After delta: vaddr = 0x80000fc8 + 18190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h1aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 59 <= 0000000000000014000000001fffff44000000 + 18200 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 18200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000050 o: 'h0000000000000050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc8, write: True, capStore: False, potentialCapLoad: False } + 18200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc8 +After delta: vaddr = 0x80000fc8 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h16, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000116 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18210 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc8, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h000 } + 18210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc8, write: False, capStore: False, potentialCapLoad: False } +instret:89 PC:0x1ffff000000000000000000008000033c instr:0xfca44823 iType:St [doCommitNormalInst [0]] 1821 +instret:90 PC:0x1ffff0000000000000000000080000340 instr:0x05000513 iType:Alu [doCommitNormalInst [1]] 1821 +calling cycle +[RFile] wr_ 0: r 5d <= 0000000000000011400000001fffff44000000 + 18220 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc8, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h833c } + 18220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000fc8, shiftedBE: tagged DataMemAccess , pcHash: 'h834c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 18220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +instret:91 PC:0x1ffff0000000000000000000080000344 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 1822 +instret:92 PC:0x1ffff0000000000000000000080000348 instr:0x0040006f iType:J [doCommitNormalInst [1]] 1822 +calling cycle + 18230 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000000000014000000001fffff44000000 + 18230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 18230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 18230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000fc8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fc8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8344 } + 18240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } +calling cycle + 18250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + 18250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 18250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:93 PC:0x1ffff000000000000000000008000034c instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 1825 +instret:94 PC:0x1ffff0000000000000000000080000350 instr:0x04500513 iType:Alu [doCommitNormalInst [1]] 1825 +calling cycle +calling cycle +instret:95 PC:0x1ffff0000000000000000000080000354 instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 1827 +instret:96 PC:0x1ffff0000000000000000000080000358 instr:0x1160006f iType:J [doCommitNormalInst [1]] 1827 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffcb8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd0 +After delta: vaddr = 0x80000fd0 +calling cycle + 18760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: False, capStore: False, potentialCapLoad: True } +calling cycle +[RFile] wr_ 1: r 60 <= 000000002000011c800000001fffff44000000 + 18770 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 18770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000fd0, shiftedBE: tagged DataMemAccess , pcHash: 'h846e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h846e } +calling cycle +[RFile] wr_ 1: r 62 <= 000000002000011e800000001fffff44000000 +[ALU redirect - 1] 'h1ffff000000000000000000008000012a; 'h0; InstTag { way: 'h1, ptr: 'h07, t: 'h0f } + 18780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h846e } + 18780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h846e } + 18780 : [Ld resp] 'h0a; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } + 18780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h07, t: 'h0f } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 18800 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 5f <= 40000140200005261498ffff1ffff805261498 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } +calling cycle +instret:97 PC:0x1ffff000000000000000000008000046e instr:0xfd04250f iType:Ld [doCommitNormalInst [0]] 1882 +instret:98 PC:0x1ffff0000000000000000000080000472 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1882 +calling cycle +instret:99 PC:0x1ffff0000000000000000000080000476 instr:0xcb8080e7 iType:Jr [doCommitNormalInst [0]] 1883 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 19320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 64 <= 00000000200003dc000000001fffff44000000 + 19330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000047a o: 'h000000008000047a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 19330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 19330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 67 <= 00000000200003e8000000001fffff44000000 + 19340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 19340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } + 19340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 19340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:100 PC:0x1ffff000000000000000000008000012a instr:0x00007179 iType:Alu [doCommitNormalInst [0]] 1934 +calling cycle + 19350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 19350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050080001498 o: 'h0000000000000000 b: 'h0000050080001498 t: 'h00000050080001498 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: True, potentialCapLoad: True } + 19350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 +instret:101 PC:0x1ffff000000000000000000008000012c instr:0x0000f406 iType:St [doCommitNormalInst [0]] 1935 +calling cycle +[RFile] wr_ 0: r 6a <= 0000000000000000000000001fffff44000000 + 19360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h812c } + 19360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } + 19360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812c } +instret:102 PC:0x1ffff000000000000000000008000012e instr:0x0000f022 iType:St [doCommitNormalInst [0]] 1936 +instret:103 PC:0x1ffff0000000000000000000080000130 instr:0x00001800 iType:Alu [doCommitNormalInst [1]] 1936 +calling cycle + 19370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 19370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h8136 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 19370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812c } + 19370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812c } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 19370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:104 PC:0x1ffff0000000000000000000080000132 instr:0xfea44023 iType:St [doCommitNormalInst [0]] 1937 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h812e } + 19380 : [doRespLdForward] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 68 <= 40000140200005261498ffff1ffff805261498 + 19380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812e } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 19390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812e } + 19390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812e } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 19390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8132 } + 19400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8132 } +instret:105 PC:0x1ffff0000000000000000000080000136 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1940 +instret:106 PC:0x1ffff000000000000000000008000013a instr:0xfea005db iType:Cap [doCommitNormalInst [1]] 1940 +calling cycle + 19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8132 } + 19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8132 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h09f }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:107 PC:0x1ffff000000000000000000008000013e instr:0x00b50463 iType:Br [doCommitNormalInst [0]] 1988 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 19890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 +instret:108 PC:0x1ffff0000000000000000000080000142 instr:0x00c0006f iType:J [doCommitNormalInst [0]] 1989 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapInspect GetLen, capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } + 19900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 19910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 19910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h814e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 19910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h814e } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } + 19920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h814e } + 19920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h814e } + 19920 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } + 19920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 19930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h8158 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19930 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 6c <= 40000140200005261498ffff1ffff805261498 + 19930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 19930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8158 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000322 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 19940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 19940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8158 } + 19940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8158 } + 19940 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 19940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 + 19940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 19950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 19950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8164 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19950 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 6e <= 40000140200005261498ffff1ffff805261498 + 19950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: False, capStore: False, potentialCapLoad: False } + 19950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 19950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } +instret:109 PC:0x1ffff000000000000000000008000014e instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1995 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000320 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6d <= 0000014020000526000000001fffff44000000 + 19960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f78, check_inclusive: True } }, specBits: 'h000 } + 19960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f70, shiftedBE: tagged DataMemAccess , pcHash: 'h8168 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000050080001498 o: 'h0000050080001498 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } + 19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } + 19960 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } + 19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 } +calling cycle +[RFile] wr_ 1: r 74 <= 000000002000045b800000001fffff44000000 + 19970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 19970 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000000000000000000000001fffff44000000 + 19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 } + 19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 } + 19970 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } + 19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 + 19970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:110 PC:0x1ffff0000000000000000000080000152 instr:0x0000852a iType:Alu [doCommitNormalInst [0]] 1997 +calling cycle +[RFile] wr_ 0: r 6b <= 0000000000000000000000001fffff44000000 + 19980 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 72 <= 0000000000000000000000001fffff44000000 + 19980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: True, capStore: False, potentialCapLoad: False } + 19980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001490 +After delta: vaddr = 0x80001490 +instret:111 PC:0x1ffff0000000000000000000080000154 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1998 +calling cycle +[RFile] wr_ 0: r 77 <= 0000000020000524000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 19990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f78, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8154 } + 19990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: False, capStore: False, potentialCapLoad: False } + 19990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8154 } +calling cycle +[RFile] wr_ 0: r 75 <= 000000002000045e000000001fffff44000000 + 20000 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h000 } + 20000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080001490, shiftedBE: tagged DataMemAccess , pcHash: 'h8176 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8154 } + 20000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8154 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 } +instret:112 PC:0x1ffff0000000000000000000080000158 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 2000 +instret:113 PC:0x1ffff000000000000000000008000015c instr:0xfe35055b iType:Cap [doCommitNormalInst [1]] 2000 +calling cycle +[RFile] wr_ 1: r 71 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 } + 20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 } + 20010 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:114 PC:0x1ffff0000000000000000000080000160 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2001 +calling cycle +[RFile] wr_ 1: r 53 <= 0000000020000526000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8160 } + 20020 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000000000000001fffff44000000 + 20020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8160 } +calling cycle +calling cycle + 20040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8160 } + 20040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8160 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 20490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000322 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 20500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 20510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 20510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8164 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: False, capStore: False, potentialCapLoad: False } + 20510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000320 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 20520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f78, check_inclusive: True } }, specBits: 'h000 } + 20520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f70, shiftedBE: tagged DataMemAccess , pcHash: 'h8168 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } + 20520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } + 20520 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } + 20520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 20520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h0c2 }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 74 <= 000000002000045b800000001fffff44000000 + 20530 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000014020000526000000001fffff44000000 + 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 } + 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 } + 20530 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } + 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001490 +After delta: vaddr = 0x80001490 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000001e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 77 <= 0000000020000524000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20540 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 72 <= 0000000000000000000000001fffff44000000 + 20540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[RFile] wr_ 0: r 75 <= 000000002000045e000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20550 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h000 } + 20550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080001490, shiftedBE: tagged DataMemAccess , pcHash: 'h8176 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 } +instret:115 PC:0x1ffff0000000000000000000080000164 instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2055 +calling cycle +[RFile] wr_ 0: r 53 <= 0000000020000526000000001fffff44000000 + 20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 } + 20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 } + 20560 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:116 PC:0x1ffff0000000000000000000080000168 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 2056 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 71 <= 0000014020000526000000001fffff44000000 + 20570 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000000000000001fffff44000000 + 20570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080001490, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 20580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:117 PC:0x1ffff000000000000000000008000016c instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 2058 +instret:118 PC:0x1ffff000000000000000000008000016e instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2058 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 20590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 20590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 +instret:119 PC:0x1ffff0000000000000000000080000172 instr:0x32258593 iType:Alu [doCommitNormalInst [0]] 2059 +instret:120 PC:0x1ffff0000000000000000000080000176 instr:0x00006190 iType:Ld [doCommitNormalInst [1]] 2059 +calling cycle +[RFile] wr_ 1: r 7a <= 0000000020000526000000001fffff44000000 + 20600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h001 } + 20600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } + 20600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a4 } +instret:121 PC:0x1ffff0000000000000000000080000178 instr:0x00001597 iType:Auipc [doCommitNormalInst [0]] 2060 +instret:122 PC:0x1ffff000000000000000000008000017c instr:0x32058593 iType:Alu [doCommitNormalInst [1]] 2060 +calling cycle +[RFile] wr_ 0: r 05 <= 00000000200003e8000000001fffff44000000 + 20610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h001 } + 20610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h81a6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a4 } + 20610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a4 } + 20610 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } + 20610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a6 } +instret:123 PC:0x1ffff0000000000000000000080000180 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 2061 +calling cycle + 20620 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7e <= 000000002000011e800000001fffff44000000 + 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a6 } + 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a6 } + 20620 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } + 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:124 PC:0x1ffff0000000000000000000080000182 instr:0x00b50463 iType:Br [doCommitNormalInst [0]] 2062 +instret:125 PC:0x1ffff0000000000000000000080000186 instr:0x01e0006f iType:J [doCommitNormalInst [1]] 2062 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20630 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 57 <= 0000000020000400000000001fffff44000000 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:126 PC:0x1ffff00000000000000000000800001a4 instr:0x000070a2 iType:Ld [doCommitNormalInst [0]] 2064 +calling cycle +instret:127 PC:0x1ffff00000000000000000000800001a6 instr:0x00007402 iType:Ld [doCommitNormalInst [0]] 2065 +instret:128 PC:0x1ffff00000000000000000000800001a8 instr:0x00006145 iType:Alu [doCommitNormalInst [1]] 2065 +calling cycle +instret:129 PC:0x1ffff00000000000000000000800001aa instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2066 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd0 +After delta: vaddr = 0x80000fd0 + 21140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 78 <= 0000000000000000000000001fffff44000000 + 21150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: True, capStore: False, potentialCapLoad: True } + 21150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff8 +After delta: vaddr = 0x80000ff8 + 21150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0a <= 0000000000000000000000001fffff44000000 + 21160 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 21160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } + 21160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff0 +After delta: vaddr = 0x80000ff0 +instret:130 PC:0x1ffff000000000000000000008000047a instr:0xfea0055b iType:Cap [doCommitNormalInst [0]] 2116 +calling cycle + 21170 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } + 21170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h8484 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } + 21170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8484 } +instret:131 PC:0x1ffff000000000000000000008000047e instr:0xfca44823 iType:St [doCommitNormalInst [0]] 2117 +instret:132 PC:0x1ffff0000000000000000000080000482 instr:0x00004501 iType:Alu [doCommitNormalInst [1]] 2117 +calling cycle +[RFile] wr_ 0: r 7b <= 0000000020000400000000001fffff44000000 + 21180 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h847e } + 21180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h8486 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8484 } + 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8484 } + 21180 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8486 } +calling cycle + 21190 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000020000006000000001fffff44000000 + 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8486 } + 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8486 } + 21190 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h847e } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000ff8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21200 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000000000000000000001fffff44000000 + 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h847e } + 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h847e } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000ff0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:133 PC:0x1ffff0000000000000000000080000484 instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2121 +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000018; 'h0; InstTag { way: 'h1, ptr: 'h0a, t: 'h15 } +instret:134 PC:0x1ffff0000000000000000000080000486 instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2122 +instret:135 PC:0x1ffff0000000000000000000080000488 instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2122 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h0a, t: 'h15 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:136 PC:0x1ffff000000000000000000008000048a instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2124 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 21320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 45 <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 7c <= 0000000000000000000000001fffff44000000 + 21330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x00000000 +After delta: vaddr = 0x00000000 + 21330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 40 <= 0000000000000000400000001fffff44000000 + 21340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000000000, write: True, capStore: False, potentialCapLoad: False } + 21340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff8 +After delta: vaddr = 0x80000ff8 + 21340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:137 PC:0x1ffff0000000000000000000080000018 instr:0x0000832a iType:Alu [doCommitNormalInst [0]] 2134 +instret:138 PC:0x1ffff000000000000000000008000001a instr:0x00004281 iType:Alu [doCommitNormalInst [1]] 2134 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0c <= 00000000200003e4000000001fffff44000000 + 21350 : [doFinishMem] DTlbResp { resp: <'h0000000000000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000000000, check_high: 'h00000000000000008, check_inclusive: True } }, specBits: 'h000 } + 21350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000018 o: 'h0000000080000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: True, capStore: False, potentialCapLoad: False } + 21350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff0 +After delta: vaddr = 0x80000ff0 + 21350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:139 PC:0x1ffff000000000000000000008000001c instr:0x00004305 iType:Alu [doCommitNormalInst [0]] 2135 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 42 <= 0000000020000400000000001fffff44000000 + 21360 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } + 21360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: True, capStore: False, potentialCapLoad: False } + 21360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd8 +After delta: vaddr = 0x80000fd8 + 21360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000456 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 21370 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_MMIO_issue] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000000000000, isMMIO: True, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h801e }; MMIOCRq { addr: 'h0000000000000000, func: tagged St , byteEn: , data: TaggedData { tag: False, data: }, loadTags: False } + 21370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd8, write: True, capStore: False, potentialCapLoad: False } + 21370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd8 +After delta: vaddr = 0x80000fd8 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 21380 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd8, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 21380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd8, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21390 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd8, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 21390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000fd8, shiftedBE: tagged DataMemAccess , pcHash: 'h802e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 21390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00010000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 47 <= 000000002000040e800000001fffff44000000 + 21400 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4b <= 0000000000000000000000001fffff44000000 + 21400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001490 +After delta: vaddr = 0x80001490 + 21400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: False, localTaken: False, pcIndex: 'h027 }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +2141: mmioPlatform.rl_tohost: 0x1 (= 1) +PASS diff --git a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt index 7782ca9..247acdb 100644 --- a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt +++ b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt @@ -4,9 +4,9 @@ make[1]: 'elf_to_hex' is up to date. make[1]: Leaving directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/TooobaTest/Toooba/Tests/elf_to_hex' ../../Tests/elf_to_hex/elf_to_hex ../../Tests/isa/testC Mem.hex c_mem_load_elf: ../../Tests/isa/testC is a 64-bit ELF file -Section .text : addr 80000000 to addr 800001b8; size 0x 1b8 (= 440) bytes -Section .sbss : addr 800011b8 to addr 800011c0; size 0x 8 (= 8) bytes -Section .bss : addr 800011c0 to addr 800021c0; size 0x 1000 (= 4096) bytes +Section .text : addr 80000000 to addr 8000048c; size 0x 48c (= 1164) bytes +Section .sbss : addr 80001490 to addr 80001498; size 0x 8 (= 8) bytes +Section .bss : addr 80001498 to addr 80011498; size 0x 10000 (= 65536) bytes Section .riscv.attributes: Ignored Section .comment : Ignored Section .symtab : Searching for addresses of '_start', 'exit' and 'tohost' symbols @@ -16,11 +16,11 @@ Writing symbols to: symbol_table.txt Section .shstrtab : Ignored Section .strtab : Ignored Min addr: 80000000 (hex) -Max addr: 800021bf (hex) +Max addr: 80011497 (hex) Writing mem hex to file 'Mem.hex' Subtracting 0x80000000 base from addresses ./exe_HW_sim +v1 +tohost -Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 270 to 33554430. +Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 2213 to 33554430. 1: top.soc_top.rl_reset_start_initial ... calling cycle calling cycle @@ -1224,7 +1224,7 @@ calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h48, src2: tagged Valid 'h48, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h1a, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000011a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000316 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle [RFile] wr_ 0: r 46 <= 0000000000020000000000001fffff44000000 [RFile] wr_ 1: r 45 <= 40000000200000000000ffff1fffff44000000 @@ -1243,14 +1243,14 @@ instret:8 PC:0x1ffff000000000000000000008000000a instr:0x000002b2 iType:Alu [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle [RFile] wr_ 1: r 4b <= 0000000020000006000000001fffff44000000 -[ALU redirect - 1] 'h1ffff000000000000000000008000012a; 'h0; InstTag { way: 'h1, ptr: 'h05, t: 'h0b } +[ALU redirect - 1] 'h1ffff0000000000000000000080000326; 'h0; InstTag { way: 'h1, ptr: 'h05, t: 'h0b } 11580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } instret:9 PC:0x1ffff000000000000000000008000000c instr:0x2052815b iType:Cap [doCommitNormalInst [0]] 1158 instret:10 PC:0x1ffff0000000000000000000080000010 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1158 calling cycle [ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h05, t: 'h0b } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:11 PC:0x1ffff0000000000000000000080000014 instr:0x11a080e7 iType:Jr [doCommitNormalInst [0]] 1160 +instret:11 PC:0x1ffff0000000000000000000080000014 instr:0x316080e7 iType:Jr [doCommitNormalInst [0]] 1160 calling cycle calling cycle calling cycle @@ -1353,28 +1353,28 @@ calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 12640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 12640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 12650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 12650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000ff8 After delta: vaddr = 0x80000ff8 - 12650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000001e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 12650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffcee }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 4c <= 00000000200003f0000000001fffff44000000 - 12660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000018 o: 'h0000000080000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +[RFile] wr_ 1: r 4c <= 00000000200003e8000000001fffff44000000 + 12660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000018 o: 'h0000000080000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: True, capStore: False, potentialCapLoad: False } - 12660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 12660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000ff0 After delta: vaddr = 0x80000ff0 @@ -1382,38 +1382,40 @@ After delta: vaddr = 0x80000ff0 calling cycle [RFile] wr_ 1: r 4f <= 0000000020000400000000001fffff44000000 12670 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } - 12670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } + 12670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: True, capStore: False, potentialCapLoad: False } 12670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffec, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000fec After delta: vaddr = 0x80000fec -instret:12 PC:0x1ffff000000000000000000008000012a instr:0x00007139 iType:Alu [doCommitNormalInst [0]] 1267 +instret:12 PC:0x1ffff0000000000000000000080000326 instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 1267 calling cycle [RFile] wr_ 0: r 50 <= 0000000000000000000000001fffff44000000 12680 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } 12680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffec, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fec, write: True, capStore: False, potentialCapLoad: False } -instret:13 PC:0x1ffff000000000000000000008000012c instr:0x0000fc06 iType:St [doCommitNormalInst [0]] 1268 +instret:13 PC:0x1ffff0000000000000000000080000328 instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 1268 calling cycle -[RFile] wr_ 0: r 52 <= 0000000000000007800000001fffff44000000 -[RFile] wr_ 1: r 53 <= 000000002000004e800000001fffff44000000 +[RFile] wr_ 0: r 52 <= 00000000200000cd000000001fffff44000000 12690 : [doFinishMem] DTlbResp { resp: <'h0000000080000fec,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fec, check_high: 'h00000000080000ff0, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h812c } - 12690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812c } -instret:14 PC:0x1ffff000000000000000000008000012e instr:0x0000f822 iType:St [doCommitNormalInst [0]] 1269 -instret:15 PC:0x1ffff0000000000000000000080000130 instr:0x00000080 iType:Alu [doCommitNormalInst [1]] 1269 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8328 } + 12690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } +instret:14 PC:0x1ffff000000000000000000008000032a instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 1269 +instret:15 PC:0x1ffff000000000000000000008000032c instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 1269 calling cycle +[RFile] wr_ 1: r 53 <= 00000000200000cf000000001fffff44000000 +[ALU redirect - 1] 'h1ffff0000000000000000000080000022; 'h0; InstTag { way: 'h1, ptr: 'h09, t: 'h13 } 12700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 12700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812c } + 12700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } 12700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace -instret:16 PC:0x1ffff0000000000000000000080000132 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 1270 -instret:17 PC:0x1ffff0000000000000000000080000134 instr:0xfea42623 iType:St [doCommitNormalInst [1]] 1270 +instret:16 PC:0x1ffff000000000000000000008000032e instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 1270 +instret:17 PC:0x1ffff0000000000000000000080000330 instr:0xfea42623 iType:St [doCommitNormalInst [1]] 1270 calling cycle -instret:18 PC:0x1ffff0000000000000000000080000138 instr:0x00004579 iType:Alu [doCommitNormalInst [0]] 1271 -instret:19 PC:0x1ffff000000000000000000008000013a instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1271 +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h09, t: 'h13 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; calling cycle - 12720 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812c } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000ff8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 12720 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000ff8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +instret:18 PC:0x1ffff0000000000000000000080000334 instr:0x00000097 iType:Auipc [doCommitNormalInst [0]] 1272 +instret:19 PC:0x1ffff0000000000000000000080000338 instr:0xcee080e7 iType:Jr [doCommitNormalInst [1]] 1272 calling cycle calling cycle calling cycle @@ -1458,657 +1460,623 @@ calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffee8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle calling cycle calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 54 <= 0000000020000050800000001fffff44000000 -[ALU redirect - 1] 'h1ffff0000000000000000000080000022; 'h0; InstTag { way: 'h0, ptr: 'h0a, t: 'h14 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h0a, t: 'h14 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; + 13210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -instret:20 PC:0x1ffff000000000000000000008000013e instr:0xee8080e7 iType:Jr [doCommitNormalInst [0]] 1322 -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 13280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 13290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb8 -After delta: vaddr = 0x80000fb8 - 13290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 55 <= 00000000200003d4000000001fffff44000000 - 13300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000068, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000142 o: 'h0000000080000142 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: True, capStore: False, potentialCapLoad: False } - 13300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb0 -After delta: vaddr = 0x80000fb0 - 13300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 58 <= 00000000200003f0000000001fffff44000000 - 13310 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } - 13310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000060, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: True, capStore: False, potentialCapLoad: False } - 13310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 13220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000f98 After delta: vaddr = 0x80000f98 - 13310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:21 PC:0x1ffff0000000000000000000080000022 instr:0x00007159 iType:Alu [doCommitNormalInst [0]] 1331 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h1e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000017e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 13220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 13320 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } - 13320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000001e o: 'h000000000000001e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +[RFile] wr_ 1: r 54 <= 00000000200003cc000000001fffff44000000 + 13230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000033c o: 'h000000008000033c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } - 13320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 13230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 -instret:22 PC:0x1ffff0000000000000000000080000024 instr:0x0000f486 iType:St [doCommitNormalInst [0]] 1332 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 13330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 13330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } -instret:23 PC:0x1ffff0000000000000000000080000026 instr:0x0000f0a2 iType:St [doCommitNormalInst [0]] 1333 -instret:24 PC:0x1ffff0000000000000000000080000028 instr:0x00001880 iType:Alu [doCommitNormalInst [1]] 1333 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 13340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 13340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h802e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 13340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:25 PC:0x1ffff000000000000000000008000002a instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1334 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 000000002000040e800000001fffff44000000 - 13350 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000007800000001fffff44000000 - 13350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011b8 -After delta: vaddr = 0x800011b8 - 13350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h027 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5f <= 000000002000046e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 13360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011b8, write: False, capStore: False, potentialCapLoad: False } - 13360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 13370 : [doFinishMem] DTlbResp { resp: <'h00000000800011b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800011b8, check_high: 'h000000000800011c0, check_inclusive: True } }, specBits: 'h000 } - 13370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h00000000800011b8, shiftedBE: tagged DataMemAccess , pcHash: 'h8042 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 13370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - 13370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 13370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } -instret:26 PC:0x1ffff000000000000000000008000002e instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 1337 -calling cycle -[RFile] wr_ 0: r 5b <= 0000000000000009400000001fffff44000000 -[RFile] wr_ 1: r 63 <= 0000000000000400000000001fffff44000000 - 13380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 13380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 13380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 13380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } - 13380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 13380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 -calling cycle -[RFile] wr_ 0: r 64 <= 0000000000000400400000001fffff44000000 -[RFile] wr_ 1: r 5c <= 0000000000000008000000001fffff44000000 - 13390 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000007800000001fffff44000000 - 13390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } -instret:27 PC:0x1ffff0000000000000000000080000032 instr:0x0000051d iType:Alu [doCommitNormalInst [0]] 1339 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 13400 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h02, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800011b8, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 13400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } -instret:28 PC:0x1ffff0000000000000000000080000034 instr:0x00009961 iType:Alu [doCommitNormalInst [0]] 1340 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000014a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 13410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:29 PC:0x1ffff0000000000000000000080000036 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1341 -instret:30 PC:0x1ffff000000000000000000008000003a instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1341 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 13420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 -instret:31 PC:0x1ffff000000000000000000008000003e instr:0x17e50513 iType:Alu [doCommitNormalInst [0]] 1342 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 67 <= 40000000000000000000ffff1fffff44000000 - 13430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: True, potentialCapLoad: True } - 13430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 000000002000041b800000001fffff44000000 - 13440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h001 } - 13440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 13440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6a <= 000000002000046e000000001fffff44000000 - 13450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } - 13450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011b8 -After delta: vaddr = 0x800011b8 -calling cycle -[RFile] wr_ 1: r 6d <= 000000002000041f000000001fffff44000000 - 13460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 13460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011b8, write: False, capStore: False, potentialCapLoad: False } -calling cycle - 13470 : [doFinishMem] DTlbResp { resp: <'h00000000800011b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800011b8, check_high: 'h000000000800011c0, check_inclusive: True } }, specBits: 'h001 } - 13470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h00000000800011b8, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 13470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -calling cycle - 13480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 13480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 13480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - 14230 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000ff8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -calling cycle - 14240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 14240 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 14240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812c } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 14240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h812e } - 14250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812e } -calling cycle - 14260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 14260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812e } - 14260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 14260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812e } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 14260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fec, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8134 } - 14270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } -calling cycle - 14280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 14280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } - 14280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 14280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 14280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8024 } - 14290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } -calling cycle - 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } - 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace -calling cycle -calling cycle - 14320 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000fb8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - 14750 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800011b8, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -calling cycle - 14760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 14760 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 14760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } - 14760 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 14760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 -calling cycle - 14770 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000000000000001fffff44000000 - 14770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 14770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 14770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit - 14770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 14770 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 14770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h00000000800011b8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 14780 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000000000000001fffff44000000 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } -instret:32 PC:0x1ffff0000000000000000000080000042 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 1479 -calling cycle -[RFile] wr_ 1: r 62 <= 0000000000000007800000001fffff44000000 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 15120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 15130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h027 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 15140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 15150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 15150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, data: TaggedData { tag: False, data: } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 63 <= 0000000000000400000000001fffff44000000 - 15160 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000008000000001fffff44000000 - 15160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000014a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 64 <= 0000000000000400400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 15170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 67 <= 40000000000000000000ffff1fffff44000000 - 15180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: True, potentialCapLoad: True } -instret:33 PC:0x1ffff0000000000000000000080000044 instr:0xfd843583 iType:Ld [doCommitNormalInst [0]] 1518 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000144 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 62 <= 0000000000000008000000001fffff44000000 - 15190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h001 } - 15190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 000000002000041b800000001fffff44000000 - 15200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 15200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:34 PC:0x1ffff0000000000000000000080000048 instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 1520 -instret:35 PC:0x1ffff000000000000000000008000004a instr:0x00006585 iType:Alu [doCommitNormalInst [1]] 1520 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6d <= 000000002000041f000000001fffff44000000 -[RFile] wr_ 1: r 6a <= 000000002000046e000000001fffff44000000 - 15210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } - 15210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011b8 -After delta: vaddr = 0x800011b8 - 15210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:36 PC:0x1ffff000000000000000000008000004c instr:0x00002585 iType:Alu [doCommitNormalInst [0]] 1521 -instret:37 PC:0x1ffff000000000000000000008000004e instr:0x00b57463 iType:Br [doCommitNormalInst [1]] 1521 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6e <= 0000000020000470000000001fffff44000000 - 15220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 15220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011b8, write: False, capStore: False, potentialCapLoad: False } - 15220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 15220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:38 PC:0x1ffff0000000000000000000080000052 instr:0x0140006f iType:J [doCommitNormalInst [0]] 1522 -instret:39 PC:0x1ffff0000000000000000000080000066 instr:0x0210055b iType:Cap [doCommitNormalInst [1]] 1522 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 15230 : [doFinishMem] DTlbResp { resp: <'h00000000800011b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800011b8, check_high: 'h000000000800011c0, check_inclusive: True } }, specBits: 'h000 } - 15230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h00000000800011b8, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 15230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } - 15230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 13230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 57 <= 00000000200003e8000000001fffff44000000 + 13240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 13240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } + 13240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000f78 After delta: vaddr = 0x80000f78 - 15230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:40 PC:0x1ffff000000000000000000008000006a instr:0xfca44023 iType:St [doCommitNormalInst [0]] 1523 -instret:41 PC:0x1ffff000000000000000000008000006e instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1523 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 13240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:20 PC:0x1ffff0000000000000000000080000022 instr:0x00007159 iType:Alu [doCommitNormalInst [0]] 1324 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000456 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 15240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 15240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h808a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 15240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } - 15240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 15240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 15240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 15240 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 15240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 15240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:42 PC:0x1ffff0000000000000000000080000072 instr:0x14a50513 iType:Alu [doCommitNormalInst [0]] 1524 -instret:43 PC:0x1ffff0000000000000000000080000076 instr:0xf8a43c23 iType:St [doCommitNormalInst [1]] 1524 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 15250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 15250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h808e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 15250 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000000000000001fffff44000000 - 15250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 15250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 15250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h00000000800011b8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 15260 : [doRespLdForward] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 71 <= 40000000000000000000ffff1fffff44000000 - 15260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - 15260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } - 15260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 15260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 15260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 15270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 15270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 15270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - 15270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 15270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 15270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } -instret:44 PC:0x1ffff000000000000000000008000007a instr:0x0000610c iType:Ld [doCommitNormalInst [0]] 1527 -instret:45 PC:0x1ffff000000000000000000008000007c instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1527 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 15280 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f78, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 1: r 6f <= 0000000020000470000000001fffff44000000 - 15280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 15280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 15280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800011c0 o: 'h00000000800011c0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } + 13250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 13250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } - 15280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 15280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 - 15280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 13250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +instret:21 PC:0x1ffff0000000000000000000080000024 instr:0x0000f486 iType:St [doCommitNormalInst [0]] 1325 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 13260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 13260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +instret:22 PC:0x1ffff0000000000000000000080000026 instr:0x0000f0a2 iType:St [doCommitNormalInst [0]] 1326 +instret:23 PC:0x1ffff0000000000000000000080000028 instr:0x00001880 iType:Alu [doCommitNormalInst [1]] 1326 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 13270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 13270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h802e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 13270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:24 PC:0x1ffff000000000000000000008000002a instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1327 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00010000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5d <= 000000002000040e800000001fffff44000000 + 13280 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000000000000001fffff44000000 + 13280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001490 +After delta: vaddr = 0x80001490 + 13280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h027 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5e <= 0000000020000524000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 13290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: False, capStore: False, potentialCapLoad: False } + 13290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 13300 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h000 } + 13300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080001490, shiftedBE: tagged DataMemAccess , pcHash: 'h8042 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 13300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 13300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 13300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } +instret:25 PC:0x1ffff000000000000000000008000002e instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 1330 +calling cycle +[RFile] wr_ 0: r 5a <= 0000000000000001c00000001fffff44000000 +[RFile] wr_ 1: r 62 <= 0000000000004000000000001fffff44000000 + 13310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 13310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 13310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 13310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } + 13310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 13310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +calling cycle +[RFile] wr_ 0: r 63 <= 0000000000004000400000001fffff44000000 +[RFile] wr_ 1: r 5b <= 0000000000000000000000001fffff44000000 + 13320 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 60 <= 0000000000000000000000001fffff44000000 + 13320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +instret:26 PC:0x1ffff0000000000000000000080000032 instr:0x0000051d iType:Alu [doCommitNormalInst [0]] 1332 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 13330 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001490, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 13330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } +instret:27 PC:0x1ffff0000000000000000000080000034 instr:0x00009961 iType:Alu [doCommitNormalInst [0]] 1333 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000422 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 13340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:28 PC:0x1ffff0000000000000000000080000036 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1334 +instret:29 PC:0x1ffff000000000000000000008000003a instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1334 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 13350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } Decoded delta from register = 0 Before delta: vaddr = 0x80000f60 After delta: vaddr = 0x80000f60 -instret:46 PC:0x1ffff0000000000000000000080000080 instr:0x14450513 iType:Alu [doCommitNormalInst [0]] 1528 +instret:30 PC:0x1ffff000000000000000000008000003e instr:0x45650513 iType:Alu [doCommitNormalInst [0]] 1335 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 15290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 15290 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000008000000001fffff44000000 - 15290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +[RFile] wr_ 1: r 66 <= 40000000000000000000ffff1fffff44000000 + 13360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } + 13360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 68 <= 000000002000041b800000001fffff44000000 + 13370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h001 } + 13370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 13370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 69 <= 0000000020000524000000001fffff44000000 + 13380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } + 13380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001490 +After delta: vaddr = 0x80001490 +calling cycle +[RFile] wr_ 1: r 6c <= 000000002000041f000000001fffff44000000 + 13390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } + 13390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: False, capStore: False, potentialCapLoad: False } +calling cycle + 13400 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h001 } + 13400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080001490, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 13400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } +calling cycle + 13410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 13410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 13410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 14240 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000ff8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 14250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14250 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 14250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h832a } + 14260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +calling cycle + 14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } + 14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fec, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8330 } + 14280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } +calling cycle + 14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8024 } + 14300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } +calling cycle + 14310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } + 14310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +calling cycle +calling cycle + 14330 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f98, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 14760 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001490, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 14770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14770 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 14770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } + 14770 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } + 14770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 +calling cycle + 14780 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5f <= 0000000000000000000000001fffff44000000 + 14780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 14780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 14780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 14780 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } + 14780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080001490, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 14790 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6b <= 0000000000000000000000001fffff44000000 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } +instret:31 PC:0x1ffff0000000000000000000080000042 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 1480 +calling cycle +[RFile] wr_ 1: r 61 <= 0000000000000000000000001fffff44000000 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00010000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h027 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 15150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 15160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, data: TaggedData { tag: False, data: } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 62 <= 0000000000004000000000001fffff44000000 + 15170 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 60 <= 0000000000000000000000001fffff44000000 + 15170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000422 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 63 <= 0000000000004000400000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 15180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 66 <= 40000000000000000000ffff1fffff44000000 + 15190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } +instret:32 PC:0x1ffff0000000000000000000080000044 instr:0xfd843583 iType:Ld [doCommitNormalInst [0]] 1519 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000041c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 61 <= 0000000000000000000000001fffff44000000 + 15200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h001 } + 15200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 68 <= 000000002000041b800000001fffff44000000 + 15210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 15210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:33 PC:0x1ffff0000000000000000000080000048 instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 1521 +instret:34 PC:0x1ffff000000000000000000008000004a instr:0x000065c1 iType:Alu [doCommitNormalInst [1]] 1521 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6c <= 000000002000041f000000001fffff44000000 +[RFile] wr_ 1: r 69 <= 0000000020000524000000001fffff44000000 + 15220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } + 15220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001490 +After delta: vaddr = 0x80001490 + 15220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:35 PC:0x1ffff000000000000000000008000004c instr:0x00002585 iType:Alu [doCommitNormalInst [0]] 1522 +instret:36 PC:0x1ffff000000000000000000008000004e instr:0x00b57463 iType:Br [doCommitNormalInst [1]] 1522 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6d <= 0000000020000526000000001fffff44000000 + 15230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 15230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: False, capStore: False, potentialCapLoad: False } + 15230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 15230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:37 PC:0x1ffff0000000000000000000080000052 instr:0x0140006f iType:J [doCommitNormalInst [0]] 1523 +instret:38 PC:0x1ffff0000000000000000000080000066 instr:0x0210055b iType:Cap [doCommitNormalInst [1]] 1523 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 15240 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h000 } + 15240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080001490, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 15240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } -instret:47 PC:0x1ffff0000000000000000000080000084 instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 1529 + 15240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 15240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } +instret:39 PC:0x1ffff000000000000000000008000006a instr:0xfca44023 iType:St [doCommitNormalInst [0]] 1524 +instret:40 PC:0x1ffff000000000000000000008000006e instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1524 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 7a <= 0000000000000001000000001fffff44000000 - 15300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 15300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 15300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } -instret:48 PC:0x1ffff0000000000000000000080000086 instr:0xfaa43c23 iType:St [doCommitNormalInst [0]] 1530 + 15250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 15250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h808a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 15250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 15250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 15250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 15250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 15250 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } + 15250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 15250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:41 PC:0x1ffff0000000000000000000080000072 instr:0x42250513 iType:Alu [doCommitNormalInst [0]] 1525 +instret:42 PC:0x1ffff0000000000000000000080000076 instr:0xf8a43c23 iType:St [doCommitNormalInst [1]] 1525 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 7b <= 000000002000002c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 15310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } - 15310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h0 + 15260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 15260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h808e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 15260 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6b <= 0000000000000000000000001fffff44000000 + 15260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 15260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 15260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 7c <= 000000002000002e000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080001490, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 15270 : [doRespLdForward] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 70 <= 40000000000000000000ffff1fffff44000000 + 15270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + 15270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } + 15270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 15270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 15270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 15280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 15280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 15280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 15280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 15280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } +instret:43 PC:0x1ffff000000000000000000008000007a instr:0x0000610c iType:Ld [doCommitNormalInst [0]] 1528 +instret:44 PC:0x1ffff000000000000000000008000007c instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1528 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15290 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f58, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[RFile] wr_ 1: r 6e <= 0000000020000526000000001fffff44000000 + 15290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 15290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 15290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001498 o: 'h0000000080001498 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 15290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 15290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 15290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 +instret:45 PC:0x1ffff0000000000000000000080000080 instr:0x41c50513 iType:Alu [doCommitNormalInst [0]] 1529 +calling cycle + 15300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 15300 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 + 15300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } +instret:46 PC:0x1ffff0000000000000000000080000084 instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 1530 +calling cycle +[RFile] wr_ 0: r 79 <= 0000000000000002800000001fffff44000000 + 15310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 15310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 15310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } +instret:47 PC:0x1ffff0000000000000000000080000086 instr:0xfaa43c23 iType:St [doCommitNormalInst [0]] 1531 +calling cycle +[RFile] wr_ 1: r 7a <= 000000002000002c000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 15320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + 15320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h0 +calling cycle +[RFile] wr_ 0: r 7b <= 000000002000002e000000001fffff44000000 [ALU redirect - 0] 'h1ffff00000000000000000000800000e2; 'h0; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } -instret:49 PC:0x1ffff000000000000000000008000008a instr:0xfc04250f iType:Ld [doCommitNormalInst [0]] 1532 +instret:48 PC:0x1ffff000000000000000000008000008a instr:0xfc04250f iType:Ld [doCommitNormalInst [0]] 1533 calling cycle [ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle calling cycle calling cycle calling cycle - 15370 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000fb8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 15380 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f98, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } calling cycle - 15380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15380 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 15380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 15380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 15390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15390 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 15390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8026 } - 15390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8026 } + 15400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } calling cycle - 15400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } - 15400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 15400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 15400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 15410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } + 15410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 15410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h802a } - 15410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h802a } + 15420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } calling cycle - 15420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } - 15420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 15420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 15420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8036 } - 15430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } -calling cycle - 15440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } - 15440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 15440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 15440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h806a } - 15450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806a } -calling cycle - 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806a } - 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806a } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8076 } - 15470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -calling cycle - 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h3 + 15430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } + 15430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h3 calling cycle calling cycle calling cycle @@ -2140,377 +2108,166 @@ calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 15810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 15820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 15830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 15820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 15830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 7d <= 00000000200003c4000000001fffff44000000 - 15830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } - 15830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +[RFile] wr_ 1: r 7c <= 00000000200003bc000000001fffff44000000 + 15840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } + 15840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 15830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 15840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 05 <= 00000000200003d4000000001fffff44000000 - 15840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 15840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } - 15840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +[RFile] wr_ 1: r 7f <= 00000000200003cc000000001fffff44000000 + 15850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 15850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } + 15850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f2c -After delta: vaddr = 0x80000f2c - 15840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + 15850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 15850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 15850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: True, capStore: False, potentialCapLoad: False } - 15850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 15850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 15860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 15860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: True } - 15860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f2c -After delta: vaddr = 0x80000f2c - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 15870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 15870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 15870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: False, capStore: False, potentialCapLoad: False } - 15870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 15870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 15880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 15880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f2c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 15880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } - 15880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 15880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 15860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 15860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: True, capStore: False, potentialCapLoad: False } + 15860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000f10 After delta: vaddr = 0x80000f10 - 15880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 15860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 15890 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000001000000001fffff44000000 - 15890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } + 15870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 15870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } - 15890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 15870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 15890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c calling cycle - 15900 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f30, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 15900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 15900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 15900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } - 15900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 15900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 15880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 15880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 15880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False } + 15880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } calling cycle - 15910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 15910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 15910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } - 15910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - 15910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 15890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 15890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace calling cycle -[RFile] wr_ 0: r 45 <= 00000000200003d4000000001fffff44000000 - 15920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 15920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 15920 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 000000002000002e000000001fffff44000000 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 15900 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000 calling cycle - 15930 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 00000000200003f0000000001fffff44000000 - 15930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + 15910 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f10, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } calling cycle - 15940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 15950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } - 15950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - 15960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 15960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 15960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 15970 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 000000002000046e000000001fffff44000000 - 15970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - 15970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 15980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 15980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h80c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 15980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011b8 -After delta: vaddr = 0x800011b8 - 15980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 15980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 15990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011b8, write: False, capStore: False, potentialCapLoad: False } - 15990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - 15990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 15990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - 15990 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 15990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 15990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 16000 : [doFinishMem] DTlbResp { resp: <'h00000000800011b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800011b8, check_high: 'h000000000800011c0, check_inclusive: True } }, specBits: 'h000 } - 16000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h00000000800011b8, shiftedBE: tagged DataMemAccess , pcHash: 'h80c4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 16000 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000008000000001fffff44000000 - 16000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - 16000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 16000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 16010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 16010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 16010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } - 16010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 16010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } - 16010 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 16010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 16010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 16010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 16010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 16020 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000000000000001fffff44000000 - 16020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } - 16020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca } - 16020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h5 - 16020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb8 -After delta: vaddr = 0x80000fb8 - 16020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - 16030 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 16030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h80d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 16030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } - 16030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb0 -After delta: vaddr = 0x80000fb0 - 16030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 16030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } calling cycle - 16040 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } - 16040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h80da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 16040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } - 16040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } - 16040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 16040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } - 16040 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 16040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 16040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011b8 -After delta: vaddr = 0x800011b8 calling cycle - 16050 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f78, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -[RFile] wr_ 0: r 42 <= 0000000000000008000000001fffff44000000 -[RFile] wr_ 1: r 4f <= 00000000200003f0000000001fffff44000000 - 16050 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } - 16050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h80dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 16050 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000000000000001fffff44000000 - 16050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011b8, write: True, capStore: False, potentialCapLoad: False } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000010 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - 16060 : [doFinishMem] DTlbResp { resp: <'h00000000800011b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800011b8, check_high: 'h000000000800011c0, check_inclusive: True } }, specBits: 'h000 } - 16060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16060 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 16060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } - 16060 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 16060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 - 16060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffeda }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - 16070 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000000000000001fffff44000000 - 16070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 16070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit - 16070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 16070 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 16070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 16080 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 - 16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + 16060 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f58, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 16070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16070 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 16070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } + 16070 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } + 16070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 +calling cycle + 16080 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000000000000000000001fffff44000000 + 16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } 16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit - 16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } - 16080 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 - 16080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 16080 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 calling cycle -[RFile] wr_ 0: r 5a <= 0000000000000004000000001fffff44000000 - 16090 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000000000000001fffff44000000 - 16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 16090 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000000000000000000001fffff44000000 + 16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } 16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit - 16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 - 16090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + 16090 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 16090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16100 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000000000000000000001fffff44000000 + 16100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } + 16100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 16100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 16100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 16090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 16100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8086 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8036 } + 16110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } calling cycle - 16110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca } - 16110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit - 16110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca } - 16110 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 16110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 16120 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + 16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } 16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } - 16120 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 16120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 16130 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 16130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } - 16130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 16130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } - 16130 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 16130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 16130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8086 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h806a } + 16130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806a } calling cycle - 16140 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8086 } + 16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806a } 16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8086 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8076 } + 16150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - 16380 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f30, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -calling cycle - 16390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16390 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 16390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } - 16390 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 16390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 -calling cycle - 16400 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: } } - 16400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - 16400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit - 16400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - 16400 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 16400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 16410 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: } } + 16160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } + 16160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 calling cycle calling cycle calling cycle @@ -2537,4464 +2294,2339 @@ calling cycle calling cycle calling cycle calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle + 16430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle + 16440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle + 16450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 16450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle + 16460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 16460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h808e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 16460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 16460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 16750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 16760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 16470 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000020000526000000001fffff44000000 + 16470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + 16470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000f78 After delta: vaddr = 0x80000f78 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 16770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 16480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 16480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } - 16770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 16780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 16780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h808e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 16780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 16490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 16490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 16490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 16490 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 16490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 16780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 16780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 16490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } +instret:49 PC:0x1ffff000000000000000000008000008e instr:0xfb843583 iType:Ld [doCommitNormalInst [0]] 1649 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } calling cycle - 16790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - 16790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } - 16790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 16790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } - 16790 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 16790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 16790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +[RFile] wr_ 1: r 72 <= 40000000200005260000ffff1fffff44000000 + 16500 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000000000000000000001fffff44000000 + 16500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001498 o: 'h0000000080001498 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } + 16500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } + 16500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } + 16500 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } + 16500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 16800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 16800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 16800 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000020000470000000001fffff44000000 - 16800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - 16800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 16800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 16810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 16810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 16810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 16810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 16810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 16810 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 16810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 16810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 16810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 16810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 16820 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 1: r 79 <= 0000000000000002800000001fffff44000000 + 16510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 16510 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } [RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 - 16820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } + 16510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + 16510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:50 PC:0x1ffff0000000000000000000080000092 instr:0x20b5055b iType:Cap [doCommitNormalInst [0]] 1651 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7a <= 000000002000002c000000001fffff44000000 + 16520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 16520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 16520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:51 PC:0x1ffff0000000000000000000080000096 instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 1652 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7b <= 000000002000002e000000001fffff44000000 +[RFile] wr_ 1: r 7c <= 00000000200003bc000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 16530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } + 16530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 16530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 76 <= 0000000000000000000000001ffff800000000 +[RFile] wr_ 1: r 7f <= 00000000200003cc000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 16540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 16540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h00000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: True } + 16540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 16540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 16550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } + 16550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + 16550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 16560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: True, capStore: False, potentialCapLoad: False } + 16560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 16560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 16570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } + 16570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + 16570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 16580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False } + 16580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef0 +After delta: vaddr = 0x80000ef0 + 16580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 16590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 16590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True } + 16590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 16590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h4 + 16590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 16590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 16600 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 16600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16600 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000 + 16600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } + 16600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 16600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } +calling cycle +calling cycle + 16620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 16620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +calling cycle +calling cycle + 16640 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000ef0, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16680 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f10, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 16680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16690 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 16690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 16690 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 16690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 16690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 16690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16700 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: } } + 16700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + 16700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } + 16700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 16700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 16700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 16700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8086 } + 16710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 16710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 16710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 16710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 16710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 16710 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } + 16710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8086 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 16720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 16720 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8086 } + 16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8086 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8096 } + 16730 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16730 : [doRespLdForward] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 74 <= 40000000200005260000ffff1fffff44000000 + 16730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + 16730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 79 <= 0000000000000002800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 16740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 16740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 16740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } + 16740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } + 16740 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } + 16740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8096 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7a <= 000000002000002c000000001fffff44000000 + 16750 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8096 } + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8096 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:52 PC:0x1ffff000000000000000000008000009a instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 1675 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7b <= 000000002000002e000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 16760 : [doRespLdForward] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 78 <= 40000000200005260000ffff1fffff44000000 + 16760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 16760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7c <= 00000000200003bc000000001fffff44000000 + 16770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } + 16770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 16770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:53 PC:0x1ffff000000000000000000008000009e instr:0xfd843583 iType:Ld [doCommitNormalInst [0]] 1677 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7f <= 00000000200003cc000000001fffff44000000 +[RFile] wr_ 1: r 76 <= 40000000200005261498ffff1ffff805261498 + 16780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 16780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001498 o: 'h0000000000000000 b: 'h0000000080001498 t: 'h00000000080001498 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } + 16780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 16780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 16790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } + 16790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 16790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:54 PC:0x1ffff00000000000000000000800000a2 instr:0x10b5055b iType:Cap [doCommitNormalInst [0]] 1679 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 16800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001498 o: 'h0000000080001498 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: True, potentialCapLoad: True } + 16800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + 16800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:55 PC:0x1ffff00000000000000000000800000a6 instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 1680 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 16810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80a6 } + 16810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: True, capStore: False, potentialCapLoad: False } + 16810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 16810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 16820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } + 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a6 } 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } - 16820 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 16820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 -instret:50 PC:0x1ffff000000000000000000008000008e instr:0xfb843583 iType:Ld [doCommitNormalInst [0]] 1682 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + 16820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 73 <= 40000000200004700000ffff1fffff44000000 - 16830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 16830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 16830 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000008000000001fffff44000000 - 16830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000000800011c0 o: 'h00000000800011c0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } - 16830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 16830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + 16830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 16830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False } + 16830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef0 +After delta: vaddr = 0x80000ef0 + 16830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 7a <= 0000000000000001000000001fffff44000000 - 16840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 16840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } - 16840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 16840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } - 16840 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 16840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 16840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } + 16840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 16840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 16840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True } + 16840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 16840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 02 <= 00000000200003cc000000001fffff44000000 + 16850 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 16850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16850 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000 + 16850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } + 16850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 16850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 16860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 16860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 16860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } + 16860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 16860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 16870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 16870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 16870 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 000000002000002e000000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16880 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 00000000200003e8000000001fffff44000000 + 16880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 16890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } + 16900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 16900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 16910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 16910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000f40 After delta: vaddr = 0x80000f40 - 16840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:51 PC:0x1ffff0000000000000000000080000092 instr:0x20b5055b iType:Cap [doCommitNormalInst [0]] 1684 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 7d <= 00000000200003c4000000001fffff44000000 -[RFile] wr_ 1: r 7b <= 000000002000002c000000001fffff44000000 - 16850 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000000000000001fffff44000000 - 16850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } - 16850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 16920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 16920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h80c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + 16920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 16920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 16920 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 16920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 16850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:52 PC:0x1ffff0000000000000000000080000096 instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 1685 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 16920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 77 <= 0000000000000000000000001ffff800080000 -[RFile] wr_ 1: r 05 <= 00000000200003d4000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } - 16860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h001 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8096 } - 16860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h00000000000000020 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } - 16860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } + 16930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 16930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16930 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 0000000020000524000000001fffff44000000 + 16930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } + 16930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 16930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 16930 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 16930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 16860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 16860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8096 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 16930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca } calling cycle -[RFile] wr_ 0: r 7c <= 000000002000002e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 16870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 16870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } - 16870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8096 } - 16870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 16870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8096 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 16870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 16870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +calling cycle + 16950 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 16950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca } + 16950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca } + 16950 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 16950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 16960 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: } } +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 16870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } calling cycle - 16880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 16880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: False, potentialCapLoad: True } - 16880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 17030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 0000000000000002800000001fffff44000000 + 17040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7a <= 000000002000002c000000001fffff44000000 + 17050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7b <= 000000002000002e000000001fffff44000000 + 17060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f2c -After delta: vaddr = 0x80000f2c - 16880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 17060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } - 16890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 16890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: True, capStore: False, potentialCapLoad: False } - 16890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +[RFile] wr_ 0: r 7c <= 00000000200003bc000000001fffff44000000 + 17070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } + 17070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 16890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 17070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 16900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 16900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: True } - 16900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +[RFile] wr_ 1: r 7f <= 00000000200003cc000000001fffff44000000 + 17080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 17080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } + 17080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f2c -After delta: vaddr = 0x80000f2c - 16900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + 17080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 16910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 16910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 16910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: False, capStore: False, potentialCapLoad: False } - 16910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 17090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 17090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: True, capStore: False, potentialCapLoad: False } + 17090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000f10 After delta: vaddr = 0x80000f10 - 16910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + 17090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 16920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 16920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f2c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 16920 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000000000000001fffff44000000 - 16920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } + 17100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 17100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } - 16920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 17100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 16920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + 17100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 16930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 16930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 16930 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000001000000001fffff44000000 - 16930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } - 16930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 17110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 17110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False } + 17110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 16930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000ef0 +After delta: vaddr = 0x80000ef0 + 17110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 45 <= 00000000200003d4000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 16940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 16940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 16940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } - 16940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - 16940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 16940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - 16940 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 16940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 16940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f2c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 16950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 16950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 16950 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 46 <= 4000000000000000000000001fffff44000000 - 16950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 17120 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000ef0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 17120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 17120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True } + 17120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 17120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 17120 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 17120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 17120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 01 <= 0000008000000000000000001fffff44000000 - 16960 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 000000002000002e000000001fffff44000000 - 16960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000020000000000 o: 'h0000020000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: False, potentialCapLoad: True } - 16960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 16970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 16970 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 00000000200003f0000000001fffff44000000 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 16980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } + 17130 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 17130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17130 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 0a <= 4000000000000000000000001fffff44000000 + 17130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } + 17130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17130 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 17130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17130 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 17130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 17130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 16980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 17130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } - 16990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } - 16990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 16990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 17140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 17140 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: } } + 17140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } + 17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17140 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } + 17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 17000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 17000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 17000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } - 17000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 17000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 17000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 17010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 17010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - 17010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - 17010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - 17010 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 17010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 17010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 17020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 17020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h80c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 17020 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 000000002000046e000000001fffff44000000 - 17020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - 17020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 17020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 17020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } -calling cycle -calling cycle - 17040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - 17040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - 17040 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 17040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 17050 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 17100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 17110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 17110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 17120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - 17120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 17130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 17130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 17130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - 17130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 17130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 17140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 17140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 17140 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 17140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 17150 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 75 <= 40000000200004700000ffff1fffff44000000 - 17150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - 17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } +[RFile] wr_ 0: r 02 <= 00000000200003cc000000001fffff44000000 + 17150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 17150 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17150 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } 17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } - 17150 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + 17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17150 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } + 17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 7a <= 0000000000000001000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 17160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 17160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 17160 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000008000000001fffff44000000 - 17160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + 17160 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 17160 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 43 <= 4000000000000000000000001fffff44000000 + 17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + 17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + 17160 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 7b <= 000000002000002c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 17170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } - 17170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } - 17170 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 17170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:53 PC:0x1ffff000000000000000000008000009a instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 1717 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + 17170 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 78 <= 40000000200005261498ffff1ffff805261498 + 17170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 7c <= 000000002000002e000000001fffff44000000 - 17180 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 79 <= 40000000200004700000ffff1fffff44000000 - 17180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 17180 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 000000002000002e000000001fffff44000000 + 17180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 17180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:54 PC:0x1ffff000000000000000000008000009e instr:0xfd843583 iType:Ld [doCommitNormalInst [0]] 1718 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 17180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 77 <= 400000002000047011c0ffff1ffff8047811c0 - 17190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000000800011c0 o: 'h0000000000000000 b: 'h00000000800011c0 t: 'h000000000800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } - 17190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 17190 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 17190 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000 + 17190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001498 o: 'h0000000000000000 b: 'h0000000080001498 t: 'h00000000080001498 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: True, potentialCapLoad: True } +instret:56 PC:0x1ffff00000000000000000000800000aa instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 1719 +instret:57 PC:0x1ffff00000000000000000000800000ae instr:0x000045a9 iType:Alu [doCommitNormalInst [1]] 1719 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 17200 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 00000000200003e8000000001fffff44000000 +instret:58 PC:0x1ffff00000000000000000000800000b0 instr:0x00000097 iType:Auipc [doCommitNormalInst [0]] 1720 +instret:59 PC:0x1ffff00000000000000000000800000b4 instr:0x032080e7 iType:Jr [doCommitNormalInst [1]] 1720 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 17190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000ef0 +After delta: vaddr = 0x80000ef0 + 17210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:60 PC:0x1ffff00000000000000000000800000e2 instr:0x00007139 iType:Alu [doCommitNormalInst [0]] 1721 +instret:61 PC:0x1ffff00000000000000000000800000e4 instr:0x0000fc06 iType:St [doCommitNormalInst [1]] 1721 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 7d <= 00000000200003c4000000001fffff44000000 - 17200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 17200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } - 17200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +[RFile] wr_ 1: r 44 <= 4000014000000000000000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80e4 } + 17220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050000000000 o: 'h0000050000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: True, capStore: True, potentialCapLoad: True } + 17220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 17200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:55 PC:0x1ffff00000000000000000000800000a2 instr:0x10b5055b iType:Cap [doCommitNormalInst [0]] 1720 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 17220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 } +instret:62 PC:0x1ffff00000000000000000000800000e6 instr:0x0000f822 iType:St [doCommitNormalInst [0]] 1722 +instret:63 PC:0x1ffff00000000000000000000800000e8 instr:0x00000080 iType:Alu [doCommitNormalInst [1]] 1722 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 05 <= 00000000200003d4000000001fffff44000000 - 17210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 17210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } - 17210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 17210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:56 PC:0x1ffff00000000000000000000800000a6 instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 1721 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } - 17220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80a6 } - 17220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000000800011c0 o: 'h00000000800011c0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: True, potentialCapLoad: True } - 17220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f2c -After delta: vaddr = 0x80000f2c - 17220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 17220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a6 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 17230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 17230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: True, capStore: False, potentialCapLoad: False } - 17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a6 } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 17230 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 17230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } + 17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 } 17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a6 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 17230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 17240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 17240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: True } - 17240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f2c -After delta: vaddr = 0x80000f2c - 17240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 17250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 17250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 17250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: False, capStore: False, potentialCapLoad: False } - 17250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 17250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 17260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 17260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f2c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 17260 : [doRespLdForward] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 40 <= 40000000200004700000ffff1fffff44000000 - 17260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } - 17260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 17260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 45 <= 00000000200003d4000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 17270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 17270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 17270 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000001000000001fffff44000000 - 17270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } - 17270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000f40 After delta: vaddr = 0x80000f40 - 17270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f2c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 17280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 17280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 17280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } - 17280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - 17280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - 17280 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 17280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 17290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 17290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 17290 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 46 <= 4000000000000000000000001fffff44000000 - 17290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 01 <= 40000080200004700000ffff1fffff44000000 - 17300 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 000000002000002e000000001fffff44000000 - 17300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800011c0 o: 'h00000200800011c0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: True, potentialCapLoad: True } - 17300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 17310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 17310 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 00000000200003f0000000001fffff44000000 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 17320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 17320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } - 17330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } - 17330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 17330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 17340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 17340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 17340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } - 17340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 17340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 17340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 17350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 17350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - 17350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - 17350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - 17350 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 17350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 17350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -calling cycle - 17370 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 17440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 17450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 17460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7a <= 0000000000000001000000001fffff44000000 - 17470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 17470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 17470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7b <= 000000002000002c000000001fffff44000000 - 17480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } - 17480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } - 17480 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 17480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7c <= 000000002000002e000000001fffff44000000 - 17490 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 79 <= 400000002000047011c0ffff1ffff8047811c0 - 17490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 17490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7d <= 00000000200003c4000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 17500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } - 17500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 17500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 00000000200003d4000000001fffff44000000 - 17510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 17510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } - 17510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 17510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:57 PC:0x1ffff00000000000000000000800000aa instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 1751 -instret:58 PC:0x1ffff00000000000000000000800000ae instr:0x00004591 iType:Alu [doCommitNormalInst [1]] 1751 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 17520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 17520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000000800011c0 o: 'h0000000000000000 b: 'h00000000800011c0 t: 'h000000000800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: True, potentialCapLoad: True } - 17520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f2c -After delta: vaddr = 0x80000f2c - 17520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:59 PC:0x1ffff00000000000000000000800000b0 instr:0x00000097 iType:Auipc [doCommitNormalInst [0]] 1752 -instret:60 PC:0x1ffff00000000000000000000800000b4 instr:0x032080e7 iType:Jr [doCommitNormalInst [1]] 1752 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 17530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 17530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: True, capStore: False, potentialCapLoad: False } - 17530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 17530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:61 PC:0x1ffff00000000000000000000800000e2 instr:0x00007139 iType:Alu [doCommitNormalInst [0]] 1753 -instret:62 PC:0x1ffff00000000000000000000800000e4 instr:0x0000fc06 iType:St [doCommitNormalInst [1]] 1753 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 17540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80e4 } - 17540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: True } - 17540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f2c -After delta: vaddr = 0x80000f2c - 17540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 17540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 } -instret:63 PC:0x1ffff00000000000000000000800000e6 instr:0x0000f822 iType:St [doCommitNormalInst [0]] 1754 -instret:64 PC:0x1ffff00000000000000000000800000e8 instr:0x00000080 iType:Alu [doCommitNormalInst [1]] 1754 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 17550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 17550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 17550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: False, capStore: False, potentialCapLoad: False } - 17550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 } - 17550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 17550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 17550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:65 PC:0x1ffff00000000000000000000800000ea instr:0xfea44023 iType:St [doCommitNormalInst [0]] 1755 -instret:66 PC:0x1ffff00000000000000000000800000ee instr:0xfcb42e23 iType:St [doCommitNormalInst [1]] 1755 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 17560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80e6 } - 17560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f2c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 17560 : [doRespLdForward] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 40 <= 400000002000047011c0ffff1ffff8047811c0 - 17560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } - 17560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 17560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 17560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 17570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 17570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 17570 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000001000000001fffff44000000 - 17570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } - 17570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 } - 17570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 17570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 17570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 45 <= 00000000200003d4000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f2c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 17580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80ea } - 17580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 17580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } - 17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - 17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - 17580 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 17580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } -instret:67 PC:0x1ffff00000000000000000000800000f2 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1758 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 17590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 17590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 17590 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 46 <= 4000000000000000000000001fffff44000000 - 17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } - 17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } - 17590 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 17590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } -instret:68 PC:0x1ffff00000000000000000000800000f6 instr:0xfdc42583 iType:Ld [doCommitNormalInst [0]] 1759 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 01 <= 400000802000047011c0ffff1ffff8047811c0 - 17600 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 000000002000002e000000001fffff44000000 - 17600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800011c0 o: 'h0000000000000000 b: 'h00000200800011c0 t: 'h000000200800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: True, potentialCapLoad: True } - 17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } - 17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } - 17600 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 17610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 17610 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 00000000200003f0000000001fffff44000000 - 17610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea } - 17610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 17610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:69 PC:0x1ffff00000000000000000000800000fa instr:0x1ab5055b iType:Cap [doCommitNormalInst [0]] 1761 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f2c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80ee } - 17620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 17620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 17620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f2c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } -instret:70 PC:0x1ffff00000000000000000000800000fe instr:0xfca44023 iType:St [doCommitNormalInst [0]] 1762 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } - 17630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } - 17630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f2c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } - 17630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f2c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 17630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 17630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 17640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80fe } - 17640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 17640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } - 17640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 17640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 17640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 17650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 17650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - 17650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - 17650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - 17650 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 17650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 17650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 17650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 17660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 17660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h80c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 17660 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 000000002000046e000000001fffff44000000 - 17660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - 17660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } - 17660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 17660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 17660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 17660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } -calling cycle -calling cycle - 17680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - 17680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - 17680 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 17680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 17690 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 17750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 17760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 17760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 17770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } - 17770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 17770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 17780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 17780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 17780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } - 17780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 17780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } -calling cycle - 17790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 17790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 17790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } - 17790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - 17790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - 17790 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 17790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } -calling cycle -[RFile] wr_ 1: r 45 <= 00000000200003d4000000001fffff44000000 - 17800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 17800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 17800 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 46 <= 400000802000047011c0ffff1ffff8047811c0 - 17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } - 17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } - 17800 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 17810 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 000000002000002e000000001fffff44000000 - 17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } - 17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } - 17810 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 17820 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 00000000200003f0000000001fffff44000000 -instret:71 PC:0x1ffff0000000000000000000080000102 instr:0xfc04250f iType:Ld [doCommitNormalInst [0]] 1782 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:72 PC:0x1ffff0000000000000000000080000106 instr:0x000070e2 iType:Ld [doCommitNormalInst [0]] 1783 -calling cycle -[ALU redirect - 1] 'h1ffff00000000000000000000800000b8; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } -instret:73 PC:0x1ffff0000000000000000000080000108 instr:0x00007442 iType:Ld [doCommitNormalInst [0]] 1784 -instret:74 PC:0x1ffff000000000000000000008000010a instr:0x00006121 iType:Alu [doCommitNormalInst [1]] 1784 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle -instret:75 PC:0x1ffff000000000000000000008000010c instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 1786 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 17920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 17930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 17930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 17940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } - 17940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 17940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 17950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 17950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 17950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800011c0 o: 'h0000000000000000 b: 'h00000200800011c0 t: 'h000000200800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } - 17950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 17950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 17960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 17960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - 17960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - 17960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - 17960 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 17960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 17970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 17970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h80c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 17970 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 000000002000046e000000001fffff44000000 - 17970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 17970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 17980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - 17980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - 17980 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 17980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011b8 -After delta: vaddr = 0x800011b8 - 17980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 17990 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000008000000001fffff44000000 - 17990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011b8, write: False, capStore: False, potentialCapLoad: False } - 17990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 17990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:76 PC:0x1ffff00000000000000000000800000b8 instr:0xf9843583 iType:Ld [doCommitNormalInst [0]] 1799 -instret:77 PC:0x1ffff00000000000000000000800000bc instr:0xfaa44023 iType:St [doCommitNormalInst [1]] 1799 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 18000 : [doFinishMem] DTlbResp { resp: <'h00000000800011b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800011b8, check_high: 'h000000000800011c0, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80bc } - 18000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h00000000800011b8, shiftedBE: tagged DataMemAccess , pcHash: 'h80c4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - 18000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 18000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 18000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 18010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 18010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 18010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } - 18010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } - 18010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } - 18010 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 18010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb8 -After delta: vaddr = 0x80000fb8 - 18010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 18010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -instret:78 PC:0x1ffff00000000000000000000800000c0 instr:0xfd843603 iType:Ld [doCommitNormalInst [0]] 1801 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 18020 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 18020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h80d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18020 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000000000000001fffff44000000 - 18020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } - 18020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 18020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 18020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb0 -After delta: vaddr = 0x80000fb0 - 18020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 18020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h00000000800011b8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 18030 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } - 18030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h80da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18030 : [doRespLdForward] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 50 <= 400000802000047011c0ffff1ffff8047811c0 - 18030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } - 18030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } - 18030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } - 18030 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 18030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } -calling cycle -[RFile] wr_ 0: r 4f <= 00000000200003f0000000001fffff44000000 - 18040 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } - 18040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h80dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18040 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000000000000001fffff44000000 - 18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } - 18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } - 18040 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 18040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 18040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } -instret:79 PC:0x1ffff00000000000000000000800000c4 instr:0x00006188 iType:Ld [doCommitNormalInst [0]] 1804 -calling cycle -[RFile] wr_ 1: r 42 <= 0000000000000008000000001fffff44000000 - 18050 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000020000050800000001fffff44000000 - 18050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800011c0 o: 'h0000000000000000 b: 'h00000200800011c0 t: 'h000000200800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: True, potentialCapLoad: True } - 18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } - 18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } - 18050 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011b8 -After delta: vaddr = 0x800011b8 -calling cycle - 18060 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 18060 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000020000400000000001fffff44000000 - 18060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011b8, write: True, capStore: False, potentialCapLoad: False } -instret:80 PC:0x1ffff00000000000000000000800000c6 instr:0x00009532 iType:Alu [doCommitNormalInst [0]] 1806 -calling cycle - 18070 : [doFinishMem] DTlbResp { resp: <'h00000000800011b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800011b8, check_high: 'h000000000800011c0, check_inclusive: True } }, specBits: 'h000 } -calling cycle -[ALU redirect - 0] 'h1ffff0000000000000000000080000142; 'h1; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } -instret:81 PC:0x1ffff00000000000000000000800000c8 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 1808 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800011b8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80c8 } - 18090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800011b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c8 } -[ROB incorrectSpec] 'h1 ; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 18100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800011b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c8 } - 18100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800011b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c8 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 18100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -instret:82 PC:0x1ffff00000000000000000000800000ca instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 1811 -instret:83 PC:0x1ffff00000000000000000000800000ce instr:0xfea44023 iType:St [doCommitNormalInst [1]] 1811 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80ce } - 18120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ce } -instret:84 PC:0x1ffff00000000000000000000800000d2 instr:0x0040006f iType:J [doCommitNormalInst [0]] 1812 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 18130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ce } - 18130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ce } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 18130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 18220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 18230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 18230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 18240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } - 18240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb8 -After delta: vaddr = 0x80000fb8 - 18240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 18250 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 18250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h80d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } - 18250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb0 -After delta: vaddr = 0x80000fb0 - 18250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } -calling cycle - 18260 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } - 18260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h80da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } - 18260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } - 18260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } - 18260 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 18260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } -calling cycle -[RFile] wr_ 1: r 4f <= 00000000200003f0000000001fffff44000000 - 18270 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } - 18270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h80dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18270 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4c <= 400000802000047011c0ffff1ffff8047811c0 - 18270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } - 18270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } - 18270 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 18270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 18280 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000020000050800000001fffff44000000 - 18280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } - 18280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } - 18280 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 18280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 18290 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000020000400000000001fffff44000000 -instret:85 PC:0x1ffff00000000000000000000800000d6 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1829 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:86 PC:0x1ffff00000000000000000000800000da instr:0x000070a6 iType:Ld [doCommitNormalInst [0]] 1830 -calling cycle -[ALU redirect - 1] 'h1ffff0000000000000000000080000142; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } -instret:87 PC:0x1ffff00000000000000000000800000dc instr:0x00007406 iType:Ld [doCommitNormalInst [0]] 1831 -instret:88 PC:0x1ffff00000000000000000000800000de instr:0x00006165 iType:Alu [doCommitNormalInst [1]] 1831 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle -instret:89 PC:0x1ffff00000000000000000000800000e0 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 1833 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000010 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 18390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffeda }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 18400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fd0 -After delta: vaddr = 0x80000fd0 -calling cycle - 18410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800011c0 o: 'h0000000000000000 b: 'h00000200800011c0 t: 'h000000200800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: True, capStore: True, potentialCapLoad: True } -calling cycle -[RFile] wr_ 1: r 5a <= 0000000000000004000000001fffff44000000 - 18420 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } -calling cycle -[RFile] wr_ 1: r 5b <= 0000000020000052000000001fffff44000000 -instret:90 PC:0x1ffff0000000000000000000080000142 instr:0xfca44823 iType:St [doCommitNormalInst [0]] 1843 -instret:91 PC:0x1ffff0000000000000000000080000146 instr:0x00004541 iType:Alu [doCommitNormalInst [1]] 1843 -calling cycle -[RFile] wr_ 0: r 5d <= 0000000020000054000000001fffff44000000 -[ALU redirect - 0] 'h1ffff0000000000000000000080000022; 'h0; InstTag { way: 'h0, ptr: 'h04, t: 'h08 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8142 } - 18440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8142 } -instret:92 PC:0x1ffff0000000000000000000080000148 instr:0x00000097 iType:Auipc [doCommitNormalInst [0]] 1844 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h04, t: 'h08 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle - 18460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8142 } - 18460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8142 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 18460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:93 PC:0x1ffff000000000000000000008000014c instr:0xeda080e7 iType:Jr [doCommitNormalInst [0]] 1846 -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 18510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 18520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb8 -After delta: vaddr = 0x80000fb8 - 18520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5c <= 00000000200003d4000000001fffff44000000 - 18530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000068, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000150 o: 'h0000000080000150 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: True, capStore: False, potentialCapLoad: False } - 18530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb0 -After delta: vaddr = 0x80000fb0 - 18530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 41 <= 00000000200003f0000000001fffff44000000 - 18540 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } - 18540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000060, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: True, capStore: False, potentialCapLoad: False } - 18540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 18540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:94 PC:0x1ffff0000000000000000000080000022 instr:0x00007159 iType:Alu [doCommitNormalInst [0]] 1854 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h1e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000017e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 18550 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } - 18550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000010 o: 'h0000000000000010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } - 18550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 -instret:95 PC:0x1ffff0000000000000000000080000024 instr:0x0000f486 iType:St [doCommitNormalInst [0]] 1855 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 18560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8024 } - 18560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - 18560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } -instret:96 PC:0x1ffff0000000000000000000080000026 instr:0x0000f0a2 iType:St [doCommitNormalInst [0]] 1856 -instret:97 PC:0x1ffff0000000000000000000080000028 instr:0x00001880 iType:Alu [doCommitNormalInst [1]] 1856 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 18570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 18570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h802e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 18570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } - 18570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 18570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:98 PC:0x1ffff000000000000000000008000002a instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1857 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 62 <= 000000002000040e800000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8026 } - 18580 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000004000000001fffff44000000 - 18580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011b8 -After delta: vaddr = 0x800011b8 - 18580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 18580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: True, localTaken: False, pcIndex: 'h027 }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 68 <= 000000002000046e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 18590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011b8, write: False, capStore: False, potentialCapLoad: False } - 18590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } - 18590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 18590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 18600 : [doFinishMem] DTlbResp { resp: <'h00000000800011b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800011b8, check_high: 'h000000000800011c0, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h802a } - 18600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h00000000800011b8, shiftedBE: tagged DataMemAccess , pcHash: 'h8042 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - 18600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 18600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } -instret:99 PC:0x1ffff000000000000000000008000002e instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 1860 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 63 <= 0000000000000005c00000001fffff44000000 -[RFile] wr_ 1: r 64 <= 0000000000000400000000001fffff44000000 - 18610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 18610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 18610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } - 18610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } - 18610 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 18610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 18610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 18610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000014a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6a <= 0000000000000400400000001fffff44000000 -[RFile] wr_ 1: r 65 <= 0000000000000004000000001fffff44000000 - 18620 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000008000000001fffff44000000 - 18620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000010 o: 'h0000000000000010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } - 18620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } - 18620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 18620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 -instret:100 PC:0x1ffff0000000000000000000080000032 instr:0x0000051d iType:Alu [doCommitNormalInst [0]] 1862 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 70 <= 40000000000000000000ffff1fffff44000000 - 18630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 18630 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000004000000001fffff44000000 - 18630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: True, potentialCapLoad: True } -instret:101 PC:0x1ffff0000000000000000000080000034 instr:0x00009961 iType:Alu [doCommitNormalInst [0]] 1863 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000144 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6c <= 000000002000041b800000001fffff44000000 - 18640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h001 } -instret:102 PC:0x1ffff0000000000000000000080000036 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1864 -instret:103 PC:0x1ffff000000000000000000008000003a instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1864 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h00000000800011b8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8036 } - 18650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 18650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } -instret:104 PC:0x1ffff000000000000000000008000003e instr:0x17e50513 iType:Alu [doCommitNormalInst [0]] 1865 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6b <= 000000000000000c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 18660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } - 18660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 18660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 18660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:105 PC:0x1ffff0000000000000000000080000042 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 1866 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 000000002000046e000000001fffff44000000 - 18670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } - 18670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011b8 -After delta: vaddr = 0x800011b8 - 18670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 000000002000041f000000001fffff44000000 - 18680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 18680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011b8, write: False, capStore: False, potentialCapLoad: False } - 18680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 18680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 0000000020000470000000001fffff44000000 - 18690 : [doFinishMem] DTlbResp { resp: <'h00000000800011b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800011b8, check_high: 'h000000000800011c0, check_inclusive: True } }, specBits: 'h000 } - 18690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h00000000800011b8, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } - 18690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 17230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:64 PC:0x1ffff00000000000000000000800000ea instr:0xfea44023 iType:St [doCommitNormalInst [0]] 1723 +instret:65 PC:0x1ffff00000000000000000000800000ee instr:0xfcb42e23 iType:St [doCommitNormalInst [1]] 1723 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f0c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80e6 } + 17240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } + 17240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000f78 After delta: vaddr = 0x80000f78 - 18690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 18690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } calling cycle - 18700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 18700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h808a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 18700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } - 18700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 18700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 18700 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 18700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 18700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + 17250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 } calling cycle - 18710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 18710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h808e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18710 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000008000000001fffff44000000 - 18710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - 18710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 18710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 17260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 17260 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 17260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h00000000800011b8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 18720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 18720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18720 : [doRespLdForward] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 76 <= 40000000000000000000ffff1fffff44000000 - 18720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - 18720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } - 18720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } - 18720 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 18720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 18720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + 17270 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 17270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 } + 17270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 18730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 18730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18730 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000020000470000000001fffff44000000 - 18730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 18730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 18730 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 18730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 18730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 18730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80ea } + 17280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea } calling cycle -[RFile] wr_ 1: r 78 <= 0000000020000478000000001fffff44000000 - 18740 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7e <= 400000802000047011c0ffff1ffff8047811c0 - 18740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800011e0 o: 'h00000000800011e0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } - 18740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } - 18740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } - 18740 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 18740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 18740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + 17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea } + 17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[RFile] wr_ 0: r 79 <= 0000000000000001000000001fffff44000000 - 18750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 18750 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000004000000001fffff44000000 - 18750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - 18750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f0c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80ee } + 17300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f0c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } calling cycle -[RFile] wr_ 0: r 7a <= 000000002000002c000000001fffff44000000 -[RFile] wr_ 1: r 7b <= 40000000200004700000ffff1fffff44000000 - 18760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 18760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000000800011c0 o: 'h00000000800011c0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } - 18760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 18760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f0c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } + 17310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f0c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 40 <= 000000002000002e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 18770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 18770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } - 18770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } - 18770 : [Ld resp] 'h03; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 18770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 18770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 58 <= 400000802000047011c0ffff1ffff8047411c0 -[RFile] wr_ 1: r 43 <= 00000000200003c4000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 18780 : [doRespLdMem] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 0a <= 400000802000047011c0ffff1ffff8047811c0 - 18780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800011c0 o: 'h0000000000000000 b: 'h00000200800011c0 t: 'h000000200800011d0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } - 18780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 18780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 00000000200003d4000000001fffff44000000 - 18790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 18790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } - 18790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 18790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } - 18800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 18800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } - 18800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 18800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 18810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 18810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800011c0 o: 'h0000000000000000 b: 'h00000200800011c0 t: 'h000000200800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: True, potentialCapLoad: True } - 18810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f2c -After delta: vaddr = 0x80000f2c - 18810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 18820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 18820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: True, capStore: False, potentialCapLoad: False } - 18820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 18820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } - 18830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 18830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: True } - 18830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f2c -After delta: vaddr = 0x80000f2c - 18830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 18840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 18840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 18840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: False, capStore: False, potentialCapLoad: False } - 18840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 17330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000f10 After delta: vaddr = 0x80000f10 - 18840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + 17330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 18850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 18850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f2c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 18850 : [doRespLdForward] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 44 <= 400000802000047011c0ffff1ffff8047811c0 - 18850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } + 17340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } - 18850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 18850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4b <= 00000000200003d4000000001fffff44000000 - 18860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 18860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18860 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000001000000001fffff44000000 - 18860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } - 18860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 18860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 18870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 18870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 18870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } - 18870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - 18870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - 18870 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 18870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 18880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 18880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 18880 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 08 <= 400000802000047011c0ffff1ffff8047811c0 - 18880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 400000802000047011c0ffff1ffff8047811c0 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f2c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 18890 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 000000002000002e000000001fffff44000000 - 18890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800011c0 o: 'h0000000000000000 b: 'h00000200800011c0 t: 'h000000200800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: True, potentialCapLoad: True } - 18890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 18900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 18900 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 00000000200003f0000000001fffff44000000 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 18910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 18910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } - 18920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } - 18920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 18920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 18930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 18930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 18930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800011c0 o: 'h0000000000000000 b: 'h00000200800011c0 t: 'h000000200800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } - 18930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 18930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 18940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 18940 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 000000002000046e000000001fffff44000000 - 18940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - 18940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 18940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h0aa, globalTaken: False, localTaken: False, pcIndex: 'h027 }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 19040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 19050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 64 <= 0000000000000400000000001fffff44000000 - 19060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 19060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 19060 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 19060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000014a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6a <= 0000000000000400400000001fffff44000000 - 19070 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000004000000001fffff44000000 - 19070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 70 <= 40000000000000000000ffff1fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 19080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: True, potentialCapLoad: True } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000144 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6c <= 000000002000041b800000001fffff44000000 - 19090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h001 } - 19090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:106 PC:0x1ffff0000000000000000000080000044 instr:0xfd843583 iType:Ld [doCommitNormalInst [0]] 1909 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6b <= 000000000000000c000000001fffff44000000 - 19100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 19100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 000000002000046e000000001fffff44000000 - 19110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } - 19110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011b8 -After delta: vaddr = 0x800011b8 - 19110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:107 PC:0x1ffff0000000000000000000080000048 instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 1911 -instret:108 PC:0x1ffff000000000000000000008000004a instr:0x00006585 iType:Alu [doCommitNormalInst [1]] 1911 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 000000002000041f000000001fffff44000000 - 19120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 19120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011b8, write: False, capStore: False, potentialCapLoad: False } - 19120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 19120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:109 PC:0x1ffff000000000000000000008000004c instr:0x00002585 iType:Alu [doCommitNormalInst [0]] 1912 -instret:110 PC:0x1ffff000000000000000000008000004e instr:0x00b57463 iType:Br [doCommitNormalInst [1]] 1912 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 0000000020000470000000001fffff44000000 - 19130 : [doFinishMem] DTlbResp { resp: <'h00000000800011b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800011b8, check_high: 'h000000000800011c0, check_inclusive: True } }, specBits: 'h000 } - 19130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h00000000800011b8, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } - 19130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 19130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:111 PC:0x1ffff0000000000000000000080000052 instr:0x0140006f iType:J [doCommitNormalInst [0]] 1913 -instret:112 PC:0x1ffff0000000000000000000080000066 instr:0x0210055b iType:Cap [doCommitNormalInst [1]] 1913 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 19140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h808a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 19140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } - 19140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 19140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 19140 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 19140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:113 PC:0x1ffff000000000000000000008000006a instr:0xfca44023 iType:St [doCommitNormalInst [0]] 1914 -instret:114 PC:0x1ffff000000000000000000008000006e instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1914 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h806a } - 19150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h808e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19150 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000008000000001fffff44000000 - 19150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 19150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } -instret:115 PC:0x1ffff0000000000000000000080000072 instr:0x14a50513 iType:Alu [doCommitNormalInst [0]] 1915 -instret:116 PC:0x1ffff0000000000000000000080000076 instr:0xf8a43c23 iType:St [doCommitNormalInst [1]] 1915 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h00000000800011b8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 19160 : [doRespLdForward] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 76 <= 40000000000000000000ffff1fffff44000000 - 19160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - 19160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } - 19160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } - 19160 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 19160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 19160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 19170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19170 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000020000470000000001fffff44000000 - 19170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - 19170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806a } - 19170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806a } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 19170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 19170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } -instret:117 PC:0x1ffff000000000000000000008000007a instr:0x0000610c iType:Ld [doCommitNormalInst [0]] 1917 -instret:118 PC:0x1ffff000000000000000000008000007c instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1917 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 0000000020000478000000001fffff44000000 - 19180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8076 } - 19180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800011e0 o: 'h00000000800011e0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } - 19180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 19180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 19180 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 19180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 19180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } -instret:119 PC:0x1ffff0000000000000000000080000080 instr:0x14450513 iType:Alu [doCommitNormalInst [0]] 1918 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 19190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 19190 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7e <= 400000802000047011c0ffff1ffff8047811c0 - 19190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - 19190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } - 19190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } - 19190 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 19190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 19190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:120 PC:0x1ffff0000000000000000000080000084 instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 1919 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 79 <= 0000000000000001000000001fffff44000000 -[RFile] wr_ 1: r 7b <= 40000000200004700000ffff1fffff44000000 - 19200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 19200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19200 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000004000000001fffff44000000 - 19200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000000800011c0 o: 'h00000000800011c0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } - 19200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 19200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 19200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } -instret:121 PC:0x1ffff0000000000000000000080000086 instr:0xfaa43c23 iType:St [doCommitNormalInst [0]] 1920 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7a <= 000000002000002c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 19210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8086 } - 19210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } - 19210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } - 19210 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 19210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 19210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8086 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 40 <= 000000002000002e000000001fffff44000000 -[RFile] wr_ 1: r 43 <= 00000000200003c4000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 19220 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 0a <= 400000802000047011c0ffff1ffff8047811c0 - 19220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } - 19220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8086 } - 19220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8086 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 19220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 19220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:122 PC:0x1ffff000000000000000000008000008a instr:0xfc04250f iType:Ld [doCommitNormalInst [0]] 1922 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 58 <= 400000802000047011c0ffff1ffff8047411c0 -[RFile] wr_ 1: r 05 <= 00000000200003d4000000001fffff44000000 - 19230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 19230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800011c0 o: 'h0000000000000000 b: 'h00000200800011c0 t: 'h000000200800011d0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } - 19230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 19230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } - 19240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 19240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } - 19240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 19240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 19250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 19250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800011c0 o: 'h0000000000000000 b: 'h00000200800011c0 t: 'h000000200800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: True, potentialCapLoad: True } - 19250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f2c -After delta: vaddr = 0x80000f2c - 19250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 19260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: True, capStore: False, potentialCapLoad: False } - 19260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 19260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } - 19270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 19270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: True } - 19270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f2c -After delta: vaddr = 0x80000f2c - 19270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 19280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 19280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: False, capStore: False, potentialCapLoad: False } - 19280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 19280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 19290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 19290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f2c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 19290 : [doRespLdForward] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 44 <= 400000802000047011c0ffff1ffff8047811c0 - 19290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } - 19290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 19290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 19300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 19300 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000001000000001fffff44000000 - 19300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } - 19300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4b <= 00000000200003d4000000001fffff44000000 - 19310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 19310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 19310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } - 19310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 19320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 19320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 19320 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 000000002000002e000000001fffff44000000 - 19320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 400000802000047011c0ffff1ffff8047811c0 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f2c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 19330 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 00000000200003f0000000001fffff44000000 - 19330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800011c0 o: 'h0000000000000000 b: 'h00000200800011c0 t: 'h000000200800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: True, potentialCapLoad: True } - 19330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 19340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 19340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 19350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } - 19350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 19350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 19360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - 19360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 19360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 19370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h80c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - 19370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - 19370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - 19370 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 19370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 19370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 19380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 19380 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 000000002000046e000000001fffff44000000 - 19380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } - 19380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - 19380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - 19380 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 19380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb8 -After delta: vaddr = 0x80000fb8 - 19380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 19390 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 19390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h80d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19390 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000004000000001fffff44000000 - 19390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } - 19390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011b8 -After delta: vaddr = 0x800011b8 - 19390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } -calling cycle -calling cycle - 19410 : [doRespLdForward] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: } } - 19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } - 19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } - 19410 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 19420 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: } } -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 19490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } - 19500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 19510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h808e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 19510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 19520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - 19520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } - 19520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } - 19520 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 19520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 19530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19530 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000020000478000000001fffff44000000 - 19530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - 19530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 19540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 19540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 19540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 19540 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 19540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 19540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 19550 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7e <= 400000802000047011c0ffff1ffff8047811c0 - 19550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - 19550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } - 19550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } - 19550 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 19550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 -instret:123 PC:0x1ffff000000000000000000008000008e instr:0xfb843583 iType:Ld [doCommitNormalInst [0]] 1955 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7b <= 40000000200004780000ffff1fffff44000000 - 19560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 19560 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000004000000001fffff44000000 - 19560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000000800011e0 o: 'h00000000800011e0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } - 19560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 0000000000000001000000001fffff44000000 - 19570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 19570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 19570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:124 PC:0x1ffff0000000000000000000080000092 instr:0x20b5055b iType:Cap [doCommitNormalInst [0]] 1957 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 43 <= 00000000200003c4000000001fffff44000000 -[RFile] wr_ 1: r 7a <= 000000002000002c000000001fffff44000000 - 19580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } - 19580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 19580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:125 PC:0x1ffff0000000000000000000080000096 instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 1958 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 58 <= 400000802000047011c0ffff1ffff8047411c0 -[RFile] wr_ 1: r 05 <= 00000000200003d4000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } - 19590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h001 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8096 } - 19590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800011c0 o: 'h0000000000000000 b: 'h00000200800011c0 t: 'h000000200800011d0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } - 19590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 19590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8096 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 40 <= 000000002000002e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 19600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 19600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } - 19600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8096 } - 19600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8096 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 19600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f2c -After delta: vaddr = 0x80000f2c - 19600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 19610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 19610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: True, capStore: False, potentialCapLoad: False } - 19610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 19610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 19620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: True } - 19620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f2c -After delta: vaddr = 0x80000f2c - 19620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 19630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: False, capStore: False, potentialCapLoad: False } - 19630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 19630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 19640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f2c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 19640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } - 19640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } - 19640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } - 19640 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 19640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 19640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 19650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 19650 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 44 <= 400000002000047011c0ffff1ffff8047811c0 - 19650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } - 19650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 19660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 19660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 19660 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000001000000001fffff44000000 - 19660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } - 19660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4b <= 00000000200003d4000000001fffff44000000 - 19670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 19670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 19670 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 000000002000002e000000001fffff44000000 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 19680 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 00000000200003f0000000001fffff44000000 - 19680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 19680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 400000802000047011c0ffff1ffff8047811c0 - 19690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800011c0 o: 'h0000000000000000 b: 'h00000200800011c0 t: 'h000000200800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: True, potentialCapLoad: True } - 19690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 19690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 19700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } - 19700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 19700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 19710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 19710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - 19710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 19710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 19720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h80c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - 19720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - 19720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - 19720 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 19720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 19730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 19730 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 000000002000046e000000001fffff44000000 - 19730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - 19730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - 19730 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 19730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 19730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19740 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000004000000001fffff44000000 - 19740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } - 19740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011b8 -After delta: vaddr = 0x800011b8 - 19740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 19750 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 19750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h80d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19750 : [doRespLdForward] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4c <= 400000802000047011c0ffff1ffff8047411c0 - 19750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011b8, write: False, capStore: False, potentialCapLoad: False } - 19750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } -calling cycle -calling cycle - 19770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } - 19770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } - 19770 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 19770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 19780 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: } } -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 19850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 19860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - 19860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 19870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - 19870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 19880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 19880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 19880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 19880 : [Ld resp] 'h15; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 19880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 19880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 19890 : [doRespLdMem] 'h15; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7e <= 40000000200004780000ffff1fffff44000000 - 19890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - 19890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } - 19890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } - 19890 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 19890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 79 <= 0000000000000001000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 19900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 19900 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000004000000001fffff44000000 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7a <= 000000002000002c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 19910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:126 PC:0x1ffff000000000000000000008000009a instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 1991 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 40 <= 000000002000002e000000001fffff44000000 - 19920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 19920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:127 PC:0x1ffff000000000000000000008000009e instr:0xfd843583 iType:Ld [doCommitNormalInst [0]] 1992 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 58 <= 400000002000047811e0ffff1ffff8047c11e0 - 19930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000000800011e0 o: 'h0000000000000000 b: 'h00000000800011e0 t: 'h000000000800011f0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } - 19930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 19930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 43 <= 00000000200003c4000000001fffff44000000 - 19940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 19940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } - 19940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 19940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:128 PC:0x1ffff00000000000000000000800000a2 instr:0x10b5055b iType:Cap [doCommitNormalInst [0]] 1994 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 05 <= 00000000200003d4000000001fffff44000000 - 19950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 19950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } - 19950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f2c -After delta: vaddr = 0x80000f2c - 19950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:129 PC:0x1ffff00000000000000000000800000a6 instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 1995 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80a6 } - 19960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: True, capStore: False, potentialCapLoad: False } - 19960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 19960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a6 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 19970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: True } - 19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a6 } - 19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a6 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f2c -After delta: vaddr = 0x80000f2c - 19970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 19980 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: False, capStore: False, potentialCapLoad: False } - 19980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 19980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 19990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 19990 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } - 19990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } - 19990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } - 19990 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 19990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 19990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 20000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 20000 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f2c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 20000 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 0a <= 400000002000047811e0ffff1ffff8047c11e0 - 20000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } - 20000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } - 20000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } - 20000 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 20000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 20000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4b <= 00000000200003d4000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 20010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 20010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 20010 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 44 <= 400000002000047011c0ffff1ffff8047811c0 - 20010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } - 20010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 20020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 20020 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000001000000001fffff44000000 - 20020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000000800011e0 o: 'h0000000000000000 b: 'h00000000800011e0 t: 'h000000000800011f0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: True, potentialCapLoad: True } - 20020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:130 PC:0x1ffff00000000000000000000800000aa instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 2002 -instret:131 PC:0x1ffff00000000000000000000800000ae instr:0x00004591 iType:Alu [doCommitNormalInst [1]] 2002 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 20030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 20030 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 20030 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 000000002000002e000000001fffff44000000 -instret:132 PC:0x1ffff00000000000000000000800000b0 instr:0x00000097 iType:Auipc [doCommitNormalInst [0]] 2003 -instret:133 PC:0x1ffff00000000000000000000800000b4 instr:0x032080e7 iType:Jr [doCommitNormalInst [1]] 2003 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20040 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 00000000200003f0000000001fffff44000000 - 20040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 20040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:134 PC:0x1ffff00000000000000000000800000e2 instr:0x00007139 iType:Alu [doCommitNormalInst [0]] 2004 -instret:135 PC:0x1ffff00000000000000000000800000e4 instr:0x0000fc06 iType:St [doCommitNormalInst [1]] 2004 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 400000802000047011c0ffff1ffff8047811c0 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80e4 } - 20050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800011c0 o: 'h0000000000000000 b: 'h00000200800011c0 t: 'h000000200800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: True, potentialCapLoad: True } - 20050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 20050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 } -instret:136 PC:0x1ffff00000000000000000000800000e6 instr:0x0000f822 iType:St [doCommitNormalInst [0]] 2005 -instret:137 PC:0x1ffff00000000000000000000800000e8 instr:0x00000080 iType:Alu [doCommitNormalInst [1]] 2005 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } - 20060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 20060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } - 20060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 } - 20060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 20060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 20060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:138 PC:0x1ffff00000000000000000000800000ea instr:0xfea44023 iType:St [doCommitNormalInst [0]] 2006 -instret:139 PC:0x1ffff00000000000000000000800000ee instr:0xfcb42e23 iType:St [doCommitNormalInst [1]] 2006 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f2c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80e6 } - 20070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - 20070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 20070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 20080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h80c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - 20080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - 20080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - 20080 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 20080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 20080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 20090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 20090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20090 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 000000002000046e000000001fffff44000000 - 20090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } - 20090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - 20090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - 20090 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 20090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb8 -After delta: vaddr = 0x80000fb8 - 20090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca } -calling cycle - 20100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 } -calling cycle - 20110 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 20110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca } - 20110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca } - 20110 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 20110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 20120 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: } } - 20120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 } - 20120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 20120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80ea } - 20130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea } -calling cycle - 20140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea } - 20140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 20140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f2c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80ee } - 20150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f2c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } -calling cycle - 20160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f2c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } - 20160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f2c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 20160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 20190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 20200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: True } - 20200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f2c -After delta: vaddr = 0x80000f2c - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 20210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: False, capStore: False, potentialCapLoad: False } - 20210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 20220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f2c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } - 20220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } - 20220 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 20220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 20220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f2c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f6 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20230 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 44 <= 400000002000047811e0ffff1ffff8047c11e0 - 20230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } - 20230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f2c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f6 } - 20230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f2c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f6 } - 20230 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 20230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 20230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 20240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 20240 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000001000000001fffff44000000 - 20240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } - 20240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f2c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 20250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } - 20250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } -instret:140 PC:0x1ffff00000000000000000000800000f2 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 2025 -calling cycle -[RFile] wr_ 0: r 4b <= 00000000200003d4000000001fffff44000000 - 20260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 20260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } - 20260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } - 20260 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 20260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 20260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } -instret:141 PC:0x1ffff00000000000000000000800000f6 instr:0xfdc42583 iType:Ld [doCommitNormalInst [0]] 2026 -calling cycle -[RFile] wr_ 1: r 0c <= 400000802000047811e0ffff1ffff8047c11e0 - 20270 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 000000002000002e000000001fffff44000000 - 20270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800011e0 o: 'h0000000000000000 b: 'h00000200800011e0 t: 'h000000200800011f0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: True, potentialCapLoad: True } - 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } - 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } - 20270 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 20280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 20280 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 00000000200003f0000000001fffff44000000 -instret:142 PC:0x1ffff00000000000000000000800000fa instr:0x1ab5055b iType:Cap [doCommitNormalInst [0]] 2028 -calling cycle -instret:143 PC:0x1ffff00000000000000000000800000fe instr:0xfca44023 iType:St [doCommitNormalInst [0]] 2029 -calling cycle -[ALU redirect - 0] 'h1ffff00000000000000000000800000b8; 'h0; InstTag { way: 'h0, ptr: 'h04, t: 'h08 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80fe } - 20300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h04, t: 'h08 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle - 20320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } - 20320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 20320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 20330 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } -calling cycle - 20340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - 20340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - 20340 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 20340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 20350 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 08 <= 400000802000047811e0ffff1ffff8047c11e0 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:144 PC:0x1ffff0000000000000000000080000102 instr:0xfc04250f iType:Ld [doCommitNormalInst [0]] 2037 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:145 PC:0x1ffff0000000000000000000080000106 instr:0x000070e2 iType:Ld [doCommitNormalInst [0]] 2038 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 20390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:146 PC:0x1ffff0000000000000000000080000108 instr:0x00007442 iType:Ld [doCommitNormalInst [0]] 2039 -instret:147 PC:0x1ffff000000000000000000008000010a instr:0x00006121 iType:Alu [doCommitNormalInst [1]] 2039 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } - 20400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 20400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:148 PC:0x1ffff000000000000000000008000010c instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2040 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 20410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 20410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800011e0 o: 'h0000000000000000 b: 'h00000200800011e0 t: 'h000000200800011f0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } - 20410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 20410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 20420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 20420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } - 20420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - 20420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } - 20420 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 20420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 20430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h80c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20430 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 000000002000046e000000001fffff44000000 - 20430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - 20440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } - 20440 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 20440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011b8 -After delta: vaddr = 0x800011b8 - 20440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20450 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000004000000001fffff44000000 - 20450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011b8, write: False, capStore: False, potentialCapLoad: False } - 20450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 20450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:149 PC:0x1ffff00000000000000000000800000b8 instr:0xf9843583 iType:Ld [doCommitNormalInst [0]] 2045 -instret:150 PC:0x1ffff00000000000000000000800000bc instr:0xfaa44023 iType:St [doCommitNormalInst [1]] 2045 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20460 : [doFinishMem] DTlbResp { resp: <'h00000000800011b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800011b8, check_high: 'h000000000800011c0, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80bc } - 20460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h00000000800011b8, shiftedBE: tagged DataMemAccess , pcHash: 'h80c4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } - 20460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 20460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 20470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 20470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } - 20470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } - 20470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } - 20470 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } } - 20470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb8 -After delta: vaddr = 0x80000fb8 - 20470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -instret:151 PC:0x1ffff00000000000000000000800000c0 instr:0xfd843603 iType:Ld [doCommitNormalInst [0]] 2047 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 20480 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 20480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h80d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20480 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 45 <= 0000000000000008000000001fffff44000000 - 20480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } - 20480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 20480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 20480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb0 -After delta: vaddr = 0x80000fb0 - 20480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h00000000800011b8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20490 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } - 20490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h80da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20490 : [doRespLdForward] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4c <= 400000802000047811e0ffff1ffff8047c11e0 - 20490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } - 20490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } - 20490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } - 20490 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 20490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } -calling cycle -[RFile] wr_ 0: r 57 <= 00000000200003f0000000001fffff44000000 - 20500 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } - 20500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h80dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20500 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4f <= 400000802000047011c0ffff1ffff8047811c0 - 20500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } - 20500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } - 20500 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 20500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 20500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } -instret:152 PC:0x1ffff00000000000000000000800000c4 instr:0x00006188 iType:Ld [doCommitNormalInst [0]] 2050 -calling cycle -[RFile] wr_ 1: r 59 <= 000000000000000c000000001fffff44000000 - 20510 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000020000054000000001fffff44000000 - 20510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800011e0 o: 'h0000000000000000 b: 'h00000200800011e0 t: 'h000000200800011f0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: True, potentialCapLoad: True } - 20510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } - 20510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } - 20510 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 20510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011b8 -After delta: vaddr = 0x800011b8 -calling cycle - 20520 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 20520 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000020000400000000001fffff44000000 - 20520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000030 o: 'h0000000000000030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011b8, write: True, capStore: False, potentialCapLoad: False } -instret:153 PC:0x1ffff00000000000000000000800000c6 instr:0x00009532 iType:Alu [doCommitNormalInst [0]] 2052 -calling cycle - 20530 : [doFinishMem] DTlbResp { resp: <'h00000000800011b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800011b8, check_high: 'h000000000800011c0, check_inclusive: True } }, specBits: 'h000 } -calling cycle -[ALU redirect - 0] 'h1ffff0000000000000000000080000150; 'h1; InstTag { way: 'h0, ptr: 'h0b, t: 'h16 } -instret:154 PC:0x1ffff00000000000000000000800000c8 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2054 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800011b8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80c8 } - 20550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800011b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c8 } -[ROB incorrectSpec] 'h1 ; InstTag { way: 'h0, ptr: 'h0b, t: 'h16 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800011b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c8 } - 20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800011b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c8 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -instret:155 PC:0x1ffff00000000000000000000800000ca instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 2057 -instret:156 PC:0x1ffff00000000000000000000800000ce instr:0xfea44023 iType:St [doCommitNormalInst [1]] 2057 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80ce } - 20580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ce } -instret:157 PC:0x1ffff00000000000000000000800000d2 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2058 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ce } - 20590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ce } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 20590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 20680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } - 20690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb8 -After delta: vaddr = 0x80000fb8 - 20690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 20700 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 20700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h80d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } - 20700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb0 -After delta: vaddr = 0x80000fb0 - 20700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } -calling cycle - 20710 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } - 20710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h80da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } - 20710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } - 20710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } - 20710 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 20710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } -calling cycle -[RFile] wr_ 1: r 57 <= 00000000200003f0000000001fffff44000000 - 20720 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } - 20720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h80dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20720 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4f <= 400000802000047811e0ffff1ffff8047c11e0 - 20720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } - 20720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } - 20720 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 20720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 20730 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000020000054000000001fffff44000000 - 20730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } - 20730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } - 20730 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 20730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20740 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000020000400000000001fffff44000000 -instret:158 PC:0x1ffff00000000000000000000800000d6 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 2074 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:159 PC:0x1ffff00000000000000000000800000da instr:0x000070a6 iType:Ld [doCommitNormalInst [0]] 2075 -calling cycle -[ALU redirect - 1] 'h1ffff0000000000000000000080000150; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } -instret:160 PC:0x1ffff00000000000000000000800000dc instr:0x00007406 iType:Ld [doCommitNormalInst [0]] 2076 -instret:161 PC:0x1ffff00000000000000000000800000de instr:0x00006165 iType:Alu [doCommitNormalInst [1]] 2076 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle -instret:162 PC:0x1ffff00000000000000000000800000e0 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2078 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fc0 -After delta: vaddr = 0x80000fc0 - 20850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h08, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff88 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800011e0 o: 'h0000000000000000 b: 'h00000200800011e0 t: 'h000000200800011f0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc0, write: True, capStore: True, potentialCapLoad: True } - 20860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fc0 -After delta: vaddr = 0x80000fc0 -calling cycle - 20870 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc0, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h000 } - 20870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc0, write: False, capStore: False, potentialCapLoad: True } -calling cycle -[RFile] wr_ 1: r 63 <= 0000000000000001c00000001fffff44000000 - 20880 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc0, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h000 } - 20880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000fc0, shiftedBE: tagged DataMemAccess , pcHash: 'h8154 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, data: TaggedData { tag: True, data: } } -instret:163 PC:0x1ffff0000000000000000000080000150 instr:0xfca44023 iType:St [doCommitNormalInst [0]] 2088 -calling cycle -[RFile] wr_ 1: r 66 <= 0000000020000056800000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fc0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8150 } - 20890 : [doRespLdForward] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 61 <= 400000802000047811e0ffff1ffff8047c11e0 - 20890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8150 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000fc0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[RFile] wr_ 0: r 65 <= 0000000020000058800000001fffff44000000 -[ALU redirect - 0] 'h1ffff00000000000000000000800000e2; 'h0; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } - 20900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8150 } - 20900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8150 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 20900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; -calling cycle -instret:164 PC:0x1ffff0000000000000000000080000154 instr:0xfc04250f iType:Ld [doCommitNormalInst [0]] 2092 -instret:165 PC:0x1ffff0000000000000000000080000158 instr:0x0000459d iType:Alu [doCommitNormalInst [1]] 2092 -calling cycle -instret:166 PC:0x1ffff000000000000000000008000015a instr:0x00000097 iType:Auipc [doCommitNormalInst [0]] 2093 -instret:167 PC:0x1ffff000000000000000000008000015e instr:0xf88080e7 iType:Jr [doCommitNormalInst [1]] 2093 -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb8 -After delta: vaddr = 0x80000fb8 - 20990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 62 <= 00000000200003e0000000001fffff44000000 - 21000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000162 o: 'h0000000080000162 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: True, capStore: False, potentialCapLoad: False } - 21000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb0 -After delta: vaddr = 0x80000fb0 - 21000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 67 <= 00000000200003f0000000001fffff44000000 - 21010 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } - 21010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: True, capStore: False, potentialCapLoad: False } - 21010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 21010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:168 PC:0x1ffff00000000000000000000800000e2 instr:0x00007139 iType:Alu [doCommitNormalInst [0]] 2101 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21020 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } - 21020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000200800011e0 o: 'h0000000000000000 b: 'h00000200800011e0 t: 'h000000200800011f0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: True, potentialCapLoad: True } - 21020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f9c -After delta: vaddr = 0x80000f9c - 21020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:169 PC:0x1ffff00000000000000000000800000e4 instr:0x0000fc06 iType:St [doCommitNormalInst [0]] 2102 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 21030 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80e4 } - 21030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: True, capStore: False, potentialCapLoad: False } - 21030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 21030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 } -instret:170 PC:0x1ffff00000000000000000000800000e6 instr:0x0000f822 iType:St [doCommitNormalInst [0]] 2103 -instret:171 PC:0x1ffff00000000000000000000800000e8 instr:0x00000080 iType:Alu [doCommitNormalInst [1]] 2103 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 21040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } - 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 } - 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f9c -After delta: vaddr = 0x80000f9c - 21040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:172 PC:0x1ffff00000000000000000000800000ea instr:0xfea44023 iType:St [doCommitNormalInst [0]] 2104 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21050 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80e6 } - 21050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 21050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f9c, write: False, capStore: False, potentialCapLoad: False } - 21050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 21050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 } -instret:173 PC:0x1ffff00000000000000000000800000ee instr:0xfcb42e23 iType:St [doCommitNormalInst [0]] 2105 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f9c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f9c o: 'h0000000080000f9c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f9c, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 21060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f9c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 21060 : [doRespLdForward] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6d <= 400000802000047811e0ffff1ffff8047c11e0 - 21060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } - 21060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 } - 21060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb8 -After delta: vaddr = 0x80000fb8 - 21060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 21070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80ea } - 21070 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000001c00000001fffff44000000 - 21070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } - 21070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb0 -After delta: vaddr = 0x80000fb0 - 21070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21080 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } - 21080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } - 21080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea } - 21080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 21080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } -instret:174 PC:0x1ffff00000000000000000000800000f2 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 2108 -calling cycle -[RFile] wr_ 0: r 6a <= 00000000200003f0000000001fffff44000000 - 21090 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f9c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80ee } - 21090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } - 21090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } - 21090 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 21090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 21090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } -instret:175 PC:0x1ffff00000000000000000000800000f6 instr:0xfdc42583 iType:Ld [doCommitNormalInst [0]] 2109 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6b <= 400000e02000047811e0ffff1ffff8047c11e0 - 21100 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000020000058800000001fffff44000000 - 21100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000380800011e0 o: 'h0000000000000000 b: 'h00000380800011e0 t: 'h000000380800011f0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: True, potentialCapLoad: True } - 21100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } - 21100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } - 21100 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 21100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000041 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 21110 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000020000400000000001fffff44000000 - 21110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } - 21110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f9c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:176 PC:0x1ffff00000000000000000000800000fa instr:0x1ab5055b iType:Cap [doCommitNormalInst [0]] 2111 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 21120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fd0 -After delta: vaddr = 0x80000fd0 -instret:177 PC:0x1ffff00000000000000000000800000fe instr:0xfca44023 iType:St [doCommitNormalInst [0]] 2112 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80fe } - 21130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: False, capStore: False, potentialCapLoad: True } - 21130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000043 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 77 <= 0000000000000010400000001fffff44000000 - 21140 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } - 21140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000fd0, shiftedBE: tagged DataMemAccess , pcHash: 'h8166 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } - 21140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 21140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fd0 -After delta: vaddr = 0x80000fd0 - 21140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8166 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000042 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21150 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: False, capStore: False, potentialCapLoad: True } - 21150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8166 } - 21150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8166 } - 21150 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 21150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 21160 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } - 21160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000fd0, shiftedBE: tagged DataMemAccess , pcHash: 'h8172 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21160 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 75 <= 400000802000047011c0ffff1ffff8047811c0 - 21160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - 21160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } - 21160 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 21160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fc0 -After delta: vaddr = 0x80000fc0 - 21160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8172 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 55 <= 0000000000000010c00000001fffff44000000 - 21170 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 70 <= 400000e02000047811e0ffff1ffff8047c11e0 - 21170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc0, write: False, capStore: False, potentialCapLoad: True } - 21170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8172 } - 21170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8172 } - 21170 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 21170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 4 -Before delta: vaddr = 0x800011c0 -After delta: vaddr = 0x800011c4 - 21170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h0cd }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 0000000000000010800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 21180 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc0, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h000 } - 21180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000fc0, shiftedBE: tagged DataMemAccess , pcHash: 'h8182 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21180 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 73 <= 400000802000047011c0ffff1ffff8047811c0 - 21180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h00000200800011c0 o: 'h0000000000000000 b: 'h00000200800011c0 t: 'h000000200800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000041 o: 'h0000000000000041 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011c4 o: 'h0000000000000000 b: 'h00000000800011c0 t: 'h000000000800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011c4, write: True, capStore: False, potentialCapLoad: False } - 21180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fc0 -After delta: vaddr = 0x80000fc0 - 21180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8182 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000010 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21190 : [doFinishMem] DTlbResp { resp: <'h00000000800011c4,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011c4 o: 'h0000000000000000 b: 'h00000000800011c0 t: 'h000000000800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h00000200800011c0, authority_top: 'h000000200800011e0, authority_idx: 'h0b, check_low: 'h00000000800011c4, check_high: 'h000000000800011c5, check_inclusive: True } }, specBits: 'h000 } - 21190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h00000380800011e0 o: 'h0000000000000000 b: 'h00000380800011e0 t: 'h000000380800011f0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc0, write: True, capStore: True, potentialCapLoad: True } - 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8182 } - 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8182 } - 21190 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fd0 -After delta: vaddr = 0x80000fd0 - 21190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:178 PC:0x1ffff0000000000000000000080000102 instr:0xfc04250f iType:Ld [doCommitNormalInst [0]] 2119 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21200 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc0, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h000 } - 21200 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 54 <= 400000802000047811e0ffff1ffff8047c11e0 - 21200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: False, capStore: False, potentialCapLoad: True } - 21200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 4 -Before delta: vaddr = 0x800011c1 -After delta: vaddr = 0x800011c5 - 21200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:179 PC:0x1ffff0000000000000000000080000106 instr:0x000070e2 iType:Ld [doCommitNormalInst [0]] 2120 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 76 <= 400000802000047051c1ffff1ffff8047811c0 - 21210 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } - 21210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000fd0, shiftedBE: tagged DataMemAccess , pcHash: 'h818e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h00000200800011c1 o: 'h0000000000000001 b: 'h00000200800011c0 t: 'h000000200800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000043 o: 'h0000000000000043 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011c5 o: 'h0000000000000001 b: 'h00000000800011c0 t: 'h000000000800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011c5, write: True, capStore: False, potentialCapLoad: False } - 21210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 4 -Before delta: vaddr = 0x800011e0 -After delta: vaddr = 0x800011e4 - 21210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h818e } -instret:180 PC:0x1ffff0000000000000000000080000108 instr:0x00007442 iType:Ld [doCommitNormalInst [0]] 2121 -instret:181 PC:0x1ffff000000000000000000008000010a instr:0x00006121 iType:Alu [doCommitNormalInst [1]] 2121 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 21220 : [doFinishMem] DTlbResp { resp: <'h00000000800011c5,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011c5 o: 'h0000000000000001 b: 'h00000000800011c0 t: 'h000000000800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h00000200800011c0, authority_top: 'h000000200800011e0, authority_idx: 'h0a, check_low: 'h00000000800011c5, check_high: 'h000000000800011c6, check_inclusive: True } }, specBits: 'h000 } - 21220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h00000200800011e0 o: 'h0000000000000000 b: 'h00000200800011e0 t: 'h000000200800011f0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000042 o: 'h0000000000000042 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011e4 o: 'h0000000000000000 b: 'h00000000800011e0 t: 'h000000000800011f0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011e4, write: True, capStore: False, potentialCapLoad: False } - 21220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h818e } - 21220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h818e } - 21220 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } - 21220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 21220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:182 PC:0x1ffff000000000000000000008000010c instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2122 -instret:183 PC:0x1ffff0000000000000000000080000162 instr:0xfca44023 iType:St [doCommitNormalInst [1]] 2122 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 21230 : [doFinishMem] DTlbResp { resp: <'h00000000800011e4,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011e4 o: 'h0000000000000000 b: 'h00000000800011e0 t: 'h000000000800011f0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h00000200800011e0, authority_top: 'h000000200800011f0, authority_idx: 'h0c, check_low: 'h00000000800011e4, check_high: 'h000000000800011e5, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fc0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8162 } - 21230 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 58 <= 400000802000047011c0ffff1ffff8047811c0 - 21230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } - 21230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 - 21230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8162 } -instret:184 PC:0x1ffff0000000000000000000080000166 instr:0xfd04258f iType:Ld [doCommitNormalInst [0]] 2123 -instret:185 PC:0x1ffff000000000000000000008000016a instr:0x04100513 iType:Alu [doCommitNormalInst [1]] 2123 -calling cycle -[RFile] wr_ 0: r 01 <= 0000000000000000000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 21240 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h001 } - 21240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h81b0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } - 21240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8162 } - 21240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8162 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 21240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b0 } -instret:186 PC:0x1ffff000000000000000000008000016e instr:0xf8a5845b iType:St [doCommitNormalInst [0]] 2124 -calling cycle -[RFile] wr_ 0: r 7d <= 0000000020000400000000001fffff44000000 - 21250 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h001 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800011c4, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h816e } - 21250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h81b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b0 } - 21250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b0 } - 21250 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 21250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 4 -Before delta: vaddr = 0x800011c1 -After delta: vaddr = 0x800011c5 - 21250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b2 } -instret:187 PC:0x1ffff0000000000000000000080000172 instr:0xfd04250f iType:Ld [doCommitNormalInst [0]] 2125 -instret:188 PC:0x1ffff0000000000000000000080000176 instr:0x0015155b iType:Cap [doCommitNormalInst [1]] 2125 -calling cycle -[RFile] wr_ 1: r 7f <= 400000802000047051c1ffff1ffff8047811c0 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000fc0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } - 21260 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000020000006000000001fffff44000000 - 21260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h00000200800011c1 o: 'h0000000000000001 b: 'h00000200800011c0 t: 'h000000200800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011c5 o: 'h0000000000000001 b: 'h00000000800011c0 t: 'h000000000800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011c5, write: False, capStore: False, potentialCapLoad: False } - 21260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b2 } - 21260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b2 } - 21260 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 21260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800011c4, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h816e } -instret:189 PC:0x1ffff000000000000000000008000017a instr:0x04300593 iType:Alu [doCommitNormalInst [0]] 2126 -instret:190 PC:0x1ffff000000000000000000008000017e instr:0xf8b5045b iType:St [doCommitNormalInst [1]] 2126 -calling cycle - 21270 : [doFinishMem] DTlbResp { resp: <'h00000000800011c5,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011c5 o: 'h0000000000000001 b: 'h00000000800011c0 t: 'h000000000800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h00000200800011c0, authority_top: 'h000000200800011e0, authority_idx: 'h0a, check_low: 'h00000000800011c5, check_high: 'h000000000800011c6, check_inclusive: True } }, specBits: 'h000 } - 21270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h00000000800011c5, shiftedBE: tagged DataMemAccess , pcHash: 'h8196 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 21270 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000000000000001fffff44000000 - 21270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800011c4, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h816e } - 21270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace -calling cycle -calling cycle - 21290 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800011c4, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h816e } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800011c4, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 21290 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000042 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 21770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fc0 -After delta: vaddr = 0x80000fc0 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc0, write: False, capStore: False, potentialCapLoad: True } - 21780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h0cd }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 0000000000000010800000001fffff44000000 - 21790 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc0, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h000 } - 21790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000fc0, shiftedBE: tagged DataMemAccess , pcHash: 'h8182 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fd0 -After delta: vaddr = 0x80000fd0 - 21790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8182 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000010 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: False, capStore: False, potentialCapLoad: True } - 21800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8182 } - 21800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8182 } - 21800 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 21800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21810 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } - 21810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000fd0, shiftedBE: tagged DataMemAccess , pcHash: 'h818e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21810 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 54 <= 400000e02000047811e0ffff1ffff8047c11e0 - 21810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h818e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000fc0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 21820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h818e } - 21820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h818e } - 21820 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } - 21820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 7 -Before delta: vaddr = 0x800011e0 -After delta: vaddr = 0x800011e7 - 21820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 01 <= 0000000000000000000000001fffff44000000 - 21830 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 58 <= 400000802000047011c0ffff1ffff8047811c0 - 21830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h00000380800011e0 o: 'h0000000000000000 b: 'h00000380800011e0 t: 'h000000380800011f0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000042 o: 'h0000000000000042 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011e7 o: 'h0000000000000000 b: 'h00000000800011e0 t: 'h000000000800011f0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011e7, write: True, capStore: False, potentialCapLoad: False } - 21830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 21830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:191 PC:0x1ffff0000000000000000000080000182 instr:0xfc04260f iType:Ld [doCommitNormalInst [0]] 2183 -instret:192 PC:0x1ffff0000000000000000000080000186 instr:0x04200513 iType:Alu [doCommitNormalInst [1]] 2183 -calling cycle - 21840 : [doFinishMem] DTlbResp { resp: <'h00000000800011e7,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011e7 o: 'h0000000000000000 b: 'h00000000800011e0 t: 'h000000000800011f0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h00000380800011e0, authority_top: 'h000000380800011f0, authority_idx: 'h0c, check_low: 'h00000000800011e7, check_high: 'h000000000800011e8, check_inclusive: True } }, specBits: 'h000 } - 21840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } - 21840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 - 21840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7d <= 0000000020000400000000001fffff44000000 - 21850 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h001 } - 21850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h81b0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } - 21850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 4 -Before delta: vaddr = 0x800011c1 -After delta: vaddr = 0x800011c5 - 21850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b0 } -instret:193 PC:0x1ffff000000000000000000008000018a instr:0xf8a6045b iType:St [doCommitNormalInst [0]] 2185 -calling cycle -[RFile] wr_ 0: r 7f <= 400000802000047051c1ffff1ffff8047811c0 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 21860 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h001 } - 21860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h81b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h00000200800011c1 o: 'h0000000000000001 b: 'h00000200800011c0 t: 'h000000200800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011c5 o: 'h0000000000000001 b: 'h00000000800011c0 t: 'h000000000800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011c5, write: False, capStore: False, potentialCapLoad: False } - 21860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b0 } - 21860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b0 } - 21860 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 21860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b2 } -calling cycle - 21870 : [doFinishMem] DTlbResp { resp: <'h00000000800011c5,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011c5 o: 'h0000000000000001 b: 'h00000000800011c0 t: 'h000000000800011e0 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h00000200800011c0, authority_top: 'h000000200800011e0, authority_idx: 'h0a, check_low: 'h00000000800011c5, check_high: 'h000000000800011c6, check_inclusive: True } }, specBits: 'h000 } - 21870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h00000000800011c5, shiftedBE: tagged DataMemAccess , pcHash: 'h8196 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 21870 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000020000006000000001fffff44000000 - 21870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b2 } - 21870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b2 } - 21870 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 21870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:194 PC:0x1ffff000000000000000000008000018e instr:0xfd04250f iType:Ld [doCommitNormalInst [0]] 2187 -instret:195 PC:0x1ffff0000000000000000000080000192 instr:0x0015155b iType:Cap [doCommitNormalInst [1]] 2187 -calling cycle - 21880 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000000000000001fffff44000000 -calling cycle - 21890 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000010c00000001fffff44000000 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h00000000800011c5, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff0000000000000000000080000018; 'h2; InstTag { way: 'h0, ptr: 'h06, t: 'h0c } -calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h0, ptr: 'h06, t: 'h0c } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000ff8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:196 PC:0x1ffff0000000000000000000080000196 instr:0xfac5055b iType:Ld [doCommitNormalInst [0]] 2192 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000ff0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -calling cycle -instret:197 PC:0x1ffff000000000000000000008000019a instr:0x00b51463 iType:Br [doCommitNormalInst [0]] 2194 -instret:198 PC:0x1ffff000000000000000000008000019e instr:0x0100006f iType:J [doCommitNormalInst [1]] 2194 -calling cycle -instret:199 PC:0x1ffff00000000000000000000800001ae instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 2195 -instret:200 PC:0x1ffff00000000000000000000800001b0 instr:0x000070e2 iType:Ld [doCommitNormalInst [1]] 2195 -calling cycle -instret:201 PC:0x1ffff00000000000000000000800001b2 instr:0x00007442 iType:Ld [doCommitNormalInst [0]] 2196 -instret:202 PC:0x1ffff00000000000000000000800001b4 instr:0x00006121 iType:Alu [doCommitNormalInst [1]] 2196 -calling cycle -instret:203 PC:0x1ffff00000000000000000000800001b6 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2197 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 22000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22010 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800011c4, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -[RFile] wr_ 0: r 79 <= 0000000000000000000000001fffff44000000 -[RFile] wr_ 1: r 0a <= 0000000000000000000000001fffff44000000 - 22010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 17340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 17350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False } + 17350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 17360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 17360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 17360 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 17360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef0 +After delta: vaddr = 0x80000ef0 + 17360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f0c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17370 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 0a <= 40000000200005261498ffff1ffff805261498 + 17370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True } + 17370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f0c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f6 } + 17370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f0c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f6 } + 17370 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } + 17370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 17370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 17380 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 17380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17380 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000 + 17380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } + 17380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 17380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f0c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 17390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } + 17390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17390 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } + 17390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } +instret:66 PC:0x1ffff00000000000000000000800000f2 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1739 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 02 <= 00000000200003cc000000001fffff44000000 + 17400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 17400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17400 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 43 <= 4000000000000000000000001fffff44000000 + 17400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } + 17400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } + 17400 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 17400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef0 +After delta: vaddr = 0x80000ef0 + 17400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } +instret:67 PC:0x1ffff00000000000000000000800000f6 instr:0xfdc42583 iType:Ld [doCommitNormalInst [0]] 1740 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 44 <= 40000140200005261498ffff1ffff805261498 + 17410 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 000000002000002e000000001fffff44000000 + 17410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050080001498 o: 'h0000000000000000 b: 'h0000050080001498 t: 'h00000050080001498 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: True, capStore: True, potentialCapLoad: True } + 17410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } + 17410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } + 17410 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 17410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17420 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 17420 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 00000000200003e8000000001fffff44000000 + 17420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:68 PC:0x1ffff00000000000000000000800000fa instr:0x1ab5055b iType:Cap [doCommitNormalInst [0]] 1742 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 49 <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 4a <= 0000000000000000000000001fffff44000000 + 17430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } Decoded delta from register = 0 Before delta: vaddr = 0x00000000 After delta: vaddr = 0x00000000 - 22010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:69 PC:0x1ffff00000000000000000000800000fe instr:0xfca44023 iType:St [doCommitNormalInst [0]] 1743 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 44 <= 0000000000000000400000001fffff44000000 - 22020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +[RFile] wr_ 1: r 4d <= 0000000000000000400000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000ef0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } +[ALU redirect - 0] 'h1ffff00000000000000000000800000b8; 'h0; InstTag { way: 'h0, ptr: 'h04, t: 'h08 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ef0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80fe } + 17440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000000000, write: True, capStore: False, potentialCapLoad: False } - 22020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22020 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 22020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800011c4, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h816e } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 22020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 17440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 17440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000ef0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h04, t: 'h08 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000ef0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000ef0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef0 +After delta: vaddr = 0x80000ef0 + 17550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True } + 17560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 17560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17570 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 17570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } + 17570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 17570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } +calling cycle + 17580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 17580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } + 17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17580 : [Ld resp] 'h15; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } + 17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } +calling cycle +[RFile] wr_ 1: r 02 <= 00000000200003cc000000001fffff44000000 + 17590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 17590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17590 : [doRespLdMem] 'h15; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 43 <= 40000140200005261498ffff1ffff805261498 + 17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } + 17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } + 17590 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000ef0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 17600 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 000000002000002e000000001fffff44000000 + 17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } + 17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } + 17600 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17610 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 00000000200003e8000000001fffff44000000 +instret:70 PC:0x1ffff0000000000000000000080000102 instr:0xfc04250f iType:Ld [doCommitNormalInst [0]] 1761 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:71 PC:0x1ffff0000000000000000000080000106 instr:0x000070e2 iType:Ld [doCommitNormalInst [0]] 1762 +calling cycle +[ALU redirect - 1] 'h1ffff00000000000000000000800000b8; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } +instret:72 PC:0x1ffff0000000000000000000080000108 instr:0x00007442 iType:Ld [doCommitNormalInst [0]] 1763 +instret:73 PC:0x1ffff000000000000000000008000010a instr:0x00006121 iType:Alu [doCommitNormalInst [1]] 1763 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:74 PC:0x1ffff000000000000000000008000010c instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 1765 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 17720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } + 17730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 17730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 17740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050080001498 o: 'h0000000000000000 b: 'h0000050080001498 t: 'h00000050080001498 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } + 17740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 17740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 17750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 17750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 17750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 17750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 17750 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 17750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 17760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h80c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17760 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 0000000020000524000000001fffff44000000 + 17760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 17770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 17770 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 17770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001490 +After delta: vaddr = 0x80001490 + 17770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17780 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 0000000000000000000000001fffff44000000 + 17780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: False, capStore: False, potentialCapLoad: False } + 17780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 17780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:75 PC:0x1ffff00000000000000000000800000b8 instr:0xf9843583 iType:Ld [doCommitNormalInst [0]] 1778 +instret:76 PC:0x1ffff00000000000000000000800000bc instr:0xfaa44023 iType:St [doCommitNormalInst [1]] 1778 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17790 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80bc } + 17790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080001490, shiftedBE: tagged DataMemAccess , pcHash: 'h80c4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + 17790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 17790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 17800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 17800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } + 17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } + 17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } + 17800 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } + 17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 17800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } +instret:77 PC:0x1ffff00000000000000000000800000c0 instr:0xfd843603 iType:Ld [doCommitNormalInst [0]] 1780 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 17810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h80d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17810 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4e <= 0000000000000000000000001fffff44000000 + 17810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } + 17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 17810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080001490, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 17820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h80da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17820 : [doRespLdForward] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 51 <= 40000140200005261498ffff1ffff805261498 + 17820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } + 17820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } + 17820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } + 17820 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } + 17820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } +calling cycle +[RFile] wr_ 0: r 4f <= 00000000200003e8000000001fffff44000000 + 17830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 17830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h80dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17830 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4c <= 0000000000000000000000001fffff44000000 + 17830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + 17830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + 17830 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } + 17830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 17830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } +instret:78 PC:0x1ffff00000000000000000000800000c4 instr:0x00006188 iType:Ld [doCommitNormalInst [0]] 1783 +calling cycle +[RFile] wr_ 1: r 08 <= 0000000000000000000000001fffff44000000 + 17840 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 55 <= 00000000200000cf000000001fffff44000000 + 17840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050080001498 o: 'h0000000000000000 b: 'h0000050080001498 t: 'h00000050080001498 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: True, potentialCapLoad: True } + 17840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 17840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 17840 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } + 17840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001490 +After delta: vaddr = 0x80001490 +calling cycle + 17850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 17850 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 56 <= 0000000020000400000000001fffff44000000 + 17850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: True, capStore: False, potentialCapLoad: False } +instret:79 PC:0x1ffff00000000000000000000800000c6 instr:0x00009532 iType:Alu [doCommitNormalInst [0]] 1785 +calling cycle + 17860 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h000 } +calling cycle +[ALU redirect - 0] 'h1ffff000000000000000000008000033c; 'h1; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } +instret:80 PC:0x1ffff00000000000000000000800000c8 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 1787 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001490, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80c8 } + 17880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001490, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c8 } +[ROB incorrectSpec] 'h1 ; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001490, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c8 } + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001490, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c8 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +instret:81 PC:0x1ffff00000000000000000000800000ca instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 1790 +instret:82 PC:0x1ffff00000000000000000000800000ce instr:0xfea44023 iType:St [doCommitNormalInst [1]] 1790 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80ce } + 17910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ce } +instret:83 PC:0x1ffff00000000000000000000800000d2 instr:0x0040006f iType:J [doCommitNormalInst [0]] 1791 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ce } + 17920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ce } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 17920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 18010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } + 18020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 18020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 18030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 18030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h80d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 18030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 18030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } +calling cycle + 18040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 18040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h80da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } + 18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } + 18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } + 18040 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } + 18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } +calling cycle +[RFile] wr_ 1: r 4f <= 00000000200003e8000000001fffff44000000 + 18050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 18050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h80dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18050 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 4c <= 40000140200005261498ffff1ffff805261498 + 18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + 18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + 18050 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } + 18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 18060 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 55 <= 00000000200000cf000000001fffff44000000 + 18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 18060 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } + 18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 18070 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 56 <= 0000000020000400000000001fffff44000000 +instret:84 PC:0x1ffff00000000000000000000800000d6 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1807 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:85 PC:0x1ffff00000000000000000000800000da instr:0x000070a6 iType:Ld [doCommitNormalInst [0]] 1808 +calling cycle +[ALU redirect - 1] 'h1ffff000000000000000000008000033c; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } +instret:86 PC:0x1ffff00000000000000000000800000dc instr:0x00007406 iType:Ld [doCommitNormalInst [0]] 1809 +instret:87 PC:0x1ffff00000000000000000000800000de instr:0x00006165 iType:Alu [doCommitNormalInst [1]] 1809 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:88 PC:0x1ffff00000000000000000000800000e0 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 1811 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000050 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd0 +After delta: vaddr = 0x80000fd0 + 18180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000045 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050080001498 o: 'h0000000000000000 b: 'h0000050080001498 t: 'h00000050080001498 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: True, capStore: True, potentialCapLoad: True } + 18190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc8 +After delta: vaddr = 0x80000fc8 + 18190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h1aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 59 <= 0000000000000014000000001fffff44000000 + 18200 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 18200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000050 o: 'h0000000000000050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc8, write: True, capStore: False, potentialCapLoad: False } + 18200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc8 +After delta: vaddr = 0x80000fc8 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h16, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000116 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18210 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc8, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h000 } + 18210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc8, write: False, capStore: False, potentialCapLoad: False } +instret:89 PC:0x1ffff000000000000000000008000033c instr:0xfca44823 iType:St [doCommitNormalInst [0]] 1821 +instret:90 PC:0x1ffff0000000000000000000080000340 instr:0x05000513 iType:Alu [doCommitNormalInst [1]] 1821 +calling cycle +[RFile] wr_ 0: r 5d <= 0000000000000011400000001fffff44000000 + 18220 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc8, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h833c } + 18220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000fc8, shiftedBE: tagged DataMemAccess , pcHash: 'h834c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 18220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +instret:91 PC:0x1ffff0000000000000000000080000344 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 1822 +instret:92 PC:0x1ffff0000000000000000000080000348 instr:0x0040006f iType:J [doCommitNormalInst [1]] 1822 +calling cycle + 18230 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000000000014000000001fffff44000000 + 18230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 18230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 18230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000fc8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fc8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8344 } + 18240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } +calling cycle + 18250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + 18250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 18250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:93 PC:0x1ffff000000000000000000008000034c instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 1825 +instret:94 PC:0x1ffff0000000000000000000080000350 instr:0x04500513 iType:Alu [doCommitNormalInst [1]] 1825 +calling cycle +calling cycle +instret:95 PC:0x1ffff0000000000000000000080000354 instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 1827 +instret:96 PC:0x1ffff0000000000000000000080000358 instr:0x1160006f iType:J [doCommitNormalInst [1]] 1827 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffcb8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd0 +After delta: vaddr = 0x80000fd0 +calling cycle + 18760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: False, capStore: False, potentialCapLoad: True } +calling cycle +[RFile] wr_ 1: r 60 <= 000000002000011c800000001fffff44000000 + 18770 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 18770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000fd0, shiftedBE: tagged DataMemAccess , pcHash: 'h846e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h846e } +calling cycle +[RFile] wr_ 1: r 62 <= 000000002000011e800000001fffff44000000 +[ALU redirect - 1] 'h1ffff000000000000000000008000012a; 'h0; InstTag { way: 'h1, ptr: 'h07, t: 'h0f } + 18780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h846e } + 18780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h846e } + 18780 : [Ld resp] 'h0a; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } + 18780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h07, t: 'h0f } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 18800 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 5f <= 40000140200005261498ffff1ffff805261498 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } +calling cycle +instret:97 PC:0x1ffff000000000000000000008000046e instr:0xfd04250f iType:Ld [doCommitNormalInst [0]] 1882 +instret:98 PC:0x1ffff0000000000000000000080000472 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1882 +calling cycle +instret:99 PC:0x1ffff0000000000000000000080000476 instr:0xcb8080e7 iType:Jr [doCommitNormalInst [0]] 1883 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 19320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 64 <= 00000000200003dc000000001fffff44000000 + 19330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000047a o: 'h000000008000047a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 19330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 19330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 67 <= 00000000200003e8000000001fffff44000000 + 19340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 19340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } + 19340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 19340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:100 PC:0x1ffff000000000000000000008000012a instr:0x00007179 iType:Alu [doCommitNormalInst [0]] 1934 +calling cycle + 19350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 19350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050080001498 o: 'h0000000000000000 b: 'h0000050080001498 t: 'h00000050080001498 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: True, potentialCapLoad: True } + 19350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 +instret:101 PC:0x1ffff000000000000000000008000012c instr:0x0000f406 iType:St [doCommitNormalInst [0]] 1935 +calling cycle +[RFile] wr_ 0: r 6a <= 0000000000000000000000001fffff44000000 + 19360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h812c } + 19360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } + 19360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812c } +instret:102 PC:0x1ffff000000000000000000008000012e instr:0x0000f022 iType:St [doCommitNormalInst [0]] 1936 +instret:103 PC:0x1ffff0000000000000000000080000130 instr:0x00001800 iType:Alu [doCommitNormalInst [1]] 1936 +calling cycle + 19370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 19370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h8136 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 19370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812c } + 19370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812c } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 19370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:104 PC:0x1ffff0000000000000000000080000132 instr:0xfea44023 iType:St [doCommitNormalInst [0]] 1937 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h812e } + 19380 : [doRespLdForward] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 68 <= 40000140200005261498ffff1ffff805261498 + 19380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812e } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 19390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812e } + 19390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812e } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 19390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8132 } + 19400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8132 } +instret:105 PC:0x1ffff0000000000000000000080000136 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1940 +instret:106 PC:0x1ffff000000000000000000008000013a instr:0xfea005db iType:Cap [doCommitNormalInst [1]] 1940 +calling cycle + 19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8132 } + 19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8132 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h09f }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:107 PC:0x1ffff000000000000000000008000013e instr:0x00b50463 iType:Br [doCommitNormalInst [0]] 1988 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 19890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 +instret:108 PC:0x1ffff0000000000000000000080000142 instr:0x00c0006f iType:J [doCommitNormalInst [0]] 1989 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapInspect GetLen, capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } + 19900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 19910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 19910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h814e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 19910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h814e } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } + 19920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h814e } + 19920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h814e } + 19920 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } + 19920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 19930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h8158 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19930 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 6c <= 40000140200005261498ffff1ffff805261498 + 19930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 19930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8158 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000322 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 19940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 19940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8158 } + 19940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8158 } + 19940 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 19940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 + 19940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 19950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 19950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8164 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19950 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 6e <= 40000140200005261498ffff1ffff805261498 + 19950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: False, capStore: False, potentialCapLoad: False } + 19950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 19950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } +instret:109 PC:0x1ffff000000000000000000008000014e instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1995 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000320 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6d <= 0000014020000526000000001fffff44000000 + 19960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f78, check_inclusive: True } }, specBits: 'h000 } + 19960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f70, shiftedBE: tagged DataMemAccess , pcHash: 'h8168 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000050080001498 o: 'h0000050080001498 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } + 19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } + 19960 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } + 19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 } +calling cycle +[RFile] wr_ 1: r 74 <= 000000002000045b800000001fffff44000000 + 19970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 19970 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000000000000000000000001fffff44000000 + 19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 } + 19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 } + 19970 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } + 19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 + 19970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:110 PC:0x1ffff0000000000000000000080000152 instr:0x0000852a iType:Alu [doCommitNormalInst [0]] 1997 +calling cycle +[RFile] wr_ 0: r 6b <= 0000000000000000000000001fffff44000000 + 19980 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 72 <= 0000000000000000000000001fffff44000000 + 19980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: True, capStore: False, potentialCapLoad: False } + 19980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001490 +After delta: vaddr = 0x80001490 +instret:111 PC:0x1ffff0000000000000000000080000154 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1998 +calling cycle +[RFile] wr_ 0: r 77 <= 0000000020000524000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 19990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f78, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8154 } + 19990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: False, capStore: False, potentialCapLoad: False } + 19990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8154 } +calling cycle +[RFile] wr_ 0: r 75 <= 000000002000045e000000001fffff44000000 + 20000 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h000 } + 20000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080001490, shiftedBE: tagged DataMemAccess , pcHash: 'h8176 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8154 } + 20000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8154 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 } +instret:112 PC:0x1ffff0000000000000000000080000158 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 2000 +instret:113 PC:0x1ffff000000000000000000008000015c instr:0xfe35055b iType:Cap [doCommitNormalInst [1]] 2000 +calling cycle +[RFile] wr_ 1: r 71 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 } + 20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 } + 20010 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:114 PC:0x1ffff0000000000000000000080000160 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2001 +calling cycle +[RFile] wr_ 1: r 53 <= 0000000020000526000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8160 } + 20020 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000000000000001fffff44000000 + 20020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8160 } +calling cycle +calling cycle + 20040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8160 } + 20040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8160 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 20490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000322 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 20500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 20510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 20510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8164 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: False, capStore: False, potentialCapLoad: False } + 20510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000320 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 20520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f78, check_inclusive: True } }, specBits: 'h000 } + 20520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f70, shiftedBE: tagged DataMemAccess , pcHash: 'h8168 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } + 20520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } + 20520 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } + 20520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 20520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h0c2 }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 74 <= 000000002000045b800000001fffff44000000 + 20530 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000014020000526000000001fffff44000000 + 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 } + 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 } + 20530 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } + 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001490 +After delta: vaddr = 0x80001490 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000001e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 77 <= 0000000020000524000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20540 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 72 <= 0000000000000000000000001fffff44000000 + 20540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[RFile] wr_ 0: r 75 <= 000000002000045e000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20550 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h000 } + 20550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080001490, shiftedBE: tagged DataMemAccess , pcHash: 'h8176 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 } +instret:115 PC:0x1ffff0000000000000000000080000164 instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2055 +calling cycle +[RFile] wr_ 0: r 53 <= 0000000020000526000000001fffff44000000 + 20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 } + 20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 } + 20560 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:116 PC:0x1ffff0000000000000000000080000168 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 2056 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 71 <= 0000014020000526000000001fffff44000000 + 20570 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000000000000001fffff44000000 + 20570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080001490, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 20580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:117 PC:0x1ffff000000000000000000008000016c instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 2058 +instret:118 PC:0x1ffff000000000000000000008000016e instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2058 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 20590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 20590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 +instret:119 PC:0x1ffff0000000000000000000080000172 instr:0x32258593 iType:Alu [doCommitNormalInst [0]] 2059 +instret:120 PC:0x1ffff0000000000000000000080000176 instr:0x00006190 iType:Ld [doCommitNormalInst [1]] 2059 +calling cycle +[RFile] wr_ 1: r 7a <= 0000000020000526000000001fffff44000000 + 20600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h001 } + 20600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } + 20600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a4 } +instret:121 PC:0x1ffff0000000000000000000080000178 instr:0x00001597 iType:Auipc [doCommitNormalInst [0]] 2060 +instret:122 PC:0x1ffff000000000000000000008000017c instr:0x32058593 iType:Alu [doCommitNormalInst [1]] 2060 +calling cycle +[RFile] wr_ 0: r 05 <= 00000000200003e8000000001fffff44000000 + 20610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h001 } + 20610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h81a6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a4 } + 20610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a4 } + 20610 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } + 20610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a6 } +instret:123 PC:0x1ffff0000000000000000000080000180 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 2061 +calling cycle + 20620 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7e <= 000000002000011e800000001fffff44000000 + 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a6 } + 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a6 } + 20620 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } + 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:124 PC:0x1ffff0000000000000000000080000182 instr:0x00b50463 iType:Br [doCommitNormalInst [0]] 2062 +instret:125 PC:0x1ffff0000000000000000000080000186 instr:0x01e0006f iType:J [doCommitNormalInst [1]] 2062 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20630 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 57 <= 0000000020000400000000001fffff44000000 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:126 PC:0x1ffff00000000000000000000800001a4 instr:0x000070a2 iType:Ld [doCommitNormalInst [0]] 2064 +calling cycle +instret:127 PC:0x1ffff00000000000000000000800001a6 instr:0x00007402 iType:Ld [doCommitNormalInst [0]] 2065 +instret:128 PC:0x1ffff00000000000000000000800001a8 instr:0x00006145 iType:Alu [doCommitNormalInst [1]] 2065 +calling cycle +instret:129 PC:0x1ffff00000000000000000000800001aa instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2066 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd0 +After delta: vaddr = 0x80000fd0 + 21140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 78 <= 0000000000000000000000001fffff44000000 + 21150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: True, capStore: False, potentialCapLoad: True } + 21150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000ff8 After delta: vaddr = 0x80000ff8 - 22020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:204 PC:0x1ffff0000000000000000000080000018 instr:0x0000832a iType:Alu [doCommitNormalInst [0]] 2202 -instret:205 PC:0x1ffff000000000000000000008000001a instr:0x00004281 iType:Alu [doCommitNormalInst [1]] 2202 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 0c <= 00000000200003e4000000001fffff44000000 - 22030 : [doFinishMem] DTlbResp { resp: <'h0000000000000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000000000, check_high: 'h00000000000000008, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800011c5, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h817e } - 22030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000068, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000018 o: 'h0000000080000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: True, capStore: False, potentialCapLoad: False } - 22030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +[RFile] wr_ 1: r 0a <= 0000000000000000000000001fffff44000000 + 21160 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 21160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } + 21160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000ff0 After delta: vaddr = 0x80000ff0 - 22030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 22030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800011c5, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h817e } -instret:206 PC:0x1ffff000000000000000000008000001c instr:0x00004305 iType:Alu [doCommitNormalInst [0]] 2203 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +instret:130 PC:0x1ffff000000000000000000008000047a instr:0xfea0055b iType:Cap [doCommitNormalInst [0]] 2116 calling cycle -[RFile] wr_ 0: r 43 <= 0000000020000400000000001fffff44000000 - 22040 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } - 22040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000060, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } + 21170 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } + 21170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h8484 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } + 21170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8484 } +instret:131 PC:0x1ffff000000000000000000008000047e instr:0xfca44823 iType:St [doCommitNormalInst [0]] 2117 +instret:132 PC:0x1ffff0000000000000000000080000482 instr:0x00004501 iType:Alu [doCommitNormalInst [1]] 2117 +calling cycle +[RFile] wr_ 0: r 7b <= 0000000020000400000000001fffff44000000 + 21180 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h847e } + 21180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h8486 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8484 } + 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8484 } + 21180 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8486 } +calling cycle + 21190 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000020000006000000001fffff44000000 + 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8486 } + 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8486 } + 21190 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h847e } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000ff8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21200 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000000000000000000001fffff44000000 + 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h847e } + 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h847e } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000ff0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:133 PC:0x1ffff0000000000000000000080000484 instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2121 +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000018; 'h0; InstTag { way: 'h1, ptr: 'h0a, t: 'h15 } +instret:134 PC:0x1ffff0000000000000000000080000486 instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2122 +instret:135 PC:0x1ffff0000000000000000000080000488 instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2122 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h0a, t: 'h15 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:136 PC:0x1ffff000000000000000000008000048a instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2124 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 21320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 45 <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 7c <= 0000000000000000000000001fffff44000000 + 21330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x00000000 +After delta: vaddr = 0x00000000 + 21330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 40 <= 0000000000000000400000001fffff44000000 + 21340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000000000, write: True, capStore: False, potentialCapLoad: False } + 21340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff8 +After delta: vaddr = 0x80000ff8 + 21340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:137 PC:0x1ffff0000000000000000000080000018 instr:0x0000832a iType:Alu [doCommitNormalInst [0]] 2134 +instret:138 PC:0x1ffff000000000000000000008000001a instr:0x00004281 iType:Alu [doCommitNormalInst [1]] 2134 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0c <= 00000000200003e4000000001fffff44000000 + 21350 : [doFinishMem] DTlbResp { resp: <'h0000000000000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000000000, check_high: 'h00000000000000008, check_inclusive: True } }, specBits: 'h000 } + 21350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000018 o: 'h0000000080000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: True, capStore: False, potentialCapLoad: False } + 21350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff0 +After delta: vaddr = 0x80000ff0 + 21350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:139 PC:0x1ffff000000000000000000008000001c instr:0x00004305 iType:Alu [doCommitNormalInst [0]] 2135 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 42 <= 0000000020000400000000001fffff44000000 + 21360 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } + 21360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: True, capStore: False, potentialCapLoad: False } - 22040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800011c5, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h817e } - 22040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800011c5, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h817e } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 22040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 21360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000fd8 After delta: vaddr = 0x80000fd8 - 22040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h1e}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000017e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + 21360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000456 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - 22050 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800011e7, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h818a } - 22050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } + 21370 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_MMIO_issue] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000000000000, isMMIO: True, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h801e }; MMIOCRq { addr: 'h0000000000000000, func: tagged St , byteEn: , data: TaggedData { tag: False, data: }, loadTags: False } + 21370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd8, write: True, capStore: False, potentialCapLoad: False } - 22050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 21370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000fd8 After delta: vaddr = 0x80000fd8 - 22050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800011e7, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h818a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - 22060 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd8, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } - 22060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } + 21380 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd8, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 21380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd8, write: False, capStore: False, potentialCapLoad: False } - 22060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800011e7, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h818a } - 22060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800011e7, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h818a } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 22060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 22070 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd8, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_MMIO_issue] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000000000000, isMMIO: True, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h801e }; MMIOCRq { addr: 'h0000000000000000, func: tagged St , byteEn: , data: TaggedData { tag: False, data: }, loadTags: False } - 22070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000fd8, shiftedBE: tagged DataMemAccess , pcHash: 'h802e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 22070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + 21390 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd8, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 21390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000fd8, shiftedBE: tagged DataMemAccess , pcHash: 'h802e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 21390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00010000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 45 <= 000000002000040e800000001fffff44000000 - 22080 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000000000000001fffff44000000 - 22080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +[RFile] wr_ 0: r 47 <= 000000002000040e800000001fffff44000000 + 21400 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4b <= 0000000000000000000000001fffff44000000 + 21400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x800011b8 -After delta: vaddr = 0x800011b8 - 22080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h055, globalTaken: False, localTaken: False, pcIndex: 'h027 }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 52 <= 000000002000046e000000001fffff44000000 - 22090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011b8, write: False, capStore: False, potentialCapLoad: False } - 22090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fd8 -After delta: vaddr = 0x80000fd8 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22100 : [doFinishMem] DTlbResp { resp: <'h00000000800011b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011b8 o: 'h00000000800011b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800011b8, check_high: 'h000000000800011c0, check_inclusive: True } }, specBits: 'h000 } - 22100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h00000000800011b8, shiftedBE: tagged DataMemAccess , pcHash: 'h8042 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd8, write: False, capStore: False, potentialCapLoad: False } - 22100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 22100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h00000000800011b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -2211: mmioPlatform.rl_tohost: 0x1 (= 1) +Before delta: vaddr = 0x80001490 +After delta: vaddr = 0x80001490 + 21400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: False, localTaken: False, pcIndex: 'h027 }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +2141: mmioPlatform.rl_tohost: 0x1 (= 1) PASS diff --git a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test1.txt b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test1.txt index 31140ee..f038328 100644 --- a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test1.txt +++ b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test1.txt @@ -4,9 +4,11 @@ make[1]: 'elf_to_hex' is up to date. make[1]: Leaving directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/TooobaTest/Toooba/Tests/elf_to_hex' ../../Tests/elf_to_hex/elf_to_hex ../../Tests/isa/testC Mem.hex c_mem_load_elf: ../../Tests/isa/testC is a 64-bit ELF file -Section .text : addr 80000000 to addr 80000010; size 0x 10 (= 16) bytes -Section .comment : Ignored +Section .text : addr 80000000 to addr 80000416; size 0x 416 (= 1046) bytes +Section .sbss : addr 80001418 to addr 80001420; size 0x 8 (= 8) bytes +Section .bss : addr 80001420 to addr 80011420; size 0x 10000 (= 65536) bytes Section .riscv.attributes: Ignored +Section .comment : Ignored Section .symtab : Searching for addresses of '_start', 'exit' and 'tohost' symbols Writing symbols to: symbol_table.txt No 'exit' label found @@ -14,1608 +16,4601 @@ Writing symbols to: symbol_table.txt Section .shstrtab : Ignored Section .strtab : Ignored Min addr: 80000000 (hex) -Max addr: 8000000f (hex) +Max addr: 8001141f (hex) Writing mem hex to file 'Mem.hex' Subtracting 0x80000000 base from addresses ./exe_HW_sim +v1 +tohost -Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 1 to 33554430. +Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 2209 to 33554430. 1: top.soc_top.rl_reset_start_initial ... +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle 11: Mem_Controller.set_addr_map: addr_base 0x80000000 addr_lim 0xc0000000 SoC address map: Boot ROM: 0x1000 .. 0x2000 Mem0 Controller: 0x80000000 .. 0xc0000000 UART0: 0xc0000000 .. 0xc0000080 11: top.soc_top.rl_reset_complete_initial +calling cycle ================================================================ Bluespec RISC-V standalone system simulation v1.2 Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved. ================================================================ INFO: watch_tohost 1, tohost_addr = 0x0, fromhost_addr = 0x0 12: top.soc_top.method start (tohost 0, fromhost 0) +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle 100: top.soc_top.rl_step_0, n = 0, do_release 100: top.soc_top do_release(restartRunning: True, to_host_addr: 0) 100: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0 +calling cycle 101: top.soc_top.rl_ctrl_req 101: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0 101: top.soc_top do_release(restartRunning: True, to_host_addr: 0) +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000020 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle [RFile] wr_ 1: r 40 <= 0000000000000400000000001fffff44000000 +calling cycle [RFile] wr_ 0: r 41 <= 0000000000000408000000001fffff44000000 instret:0 PC:0x1ffff0000000000000000000000001000 instr:0x00000297 iType:Auipc [doCommitNormalInst [0]] 167 +calling cycle instret:1 PC:0x1ffff0000000000000000000000001004 instr:0x02028593 iType:Alu [doCommitNormalInst [0]] 168 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Csr, execFunc: tagged Alu Csrs, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Valid csrAddrMHARTID, scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle [RFile] wr_ 0: r 42 <= 0000000000000000000000001fffff44000000 +calling cycle instret:2 PC:0x1ffff0000000000000000000000001008 instr:0xf1402573 iType:Csr [doCommitSystemInst] 224 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle 3340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle 3350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000018, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x00001018 +After delta: vaddr = 0x00001018 +calling cycle 3360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000018, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000000001000 o: 'h0000000000001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -Decoded delta = 0 DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000001018, write: False, capStore: False, potentialCapLoad: False } -Received delta = 0 - 3370 : [doFinishMem] DTlbResp { resp: <'h0000000000001018,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000001018, check_high: 'h00000000000001020, check_inclusive: True } }, specBits: 'h000 } +calling cycle + 3370 : [doFinishMem] DTlbResp { resp: <'h0000000000001018,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000001018, check_high: 'h00000000000001020, check_inclusive: True } }, specBits: 'h000 } +calling cycle +calling cycle [doDeqLdQ_MMIO_issue] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid }; MMIOCRq { addr: 'h0000000000001018, func: tagged Ld , byteEn: , data: TaggedData { tag: , data: }, loadTags: False } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle [RFile] wr_ 3: r 43 <= 0000000020000000000000001fffff44000000 [doDeqLdQ_MMIO_deq] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid }; TaggedData { tag: False, data: }; TaggedData { tag: False, data: } +calling cycle instret:3 PC:0x1ffff000000000000000000000000100c instr:0x0182b283 iType:Ld [doCommitNormalInst [0]] 403 +calling cycle +calling cycle +calling cycle [ALU redirect - 1] 'h1ffff0000000000000000000080000000; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } +calling cycle [ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle instret:4 PC:0x1ffff0000000000000000000000001010 instr:0x00028067 iType:Jr [doCommitNormalInst [0]] 408 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -[RFile] wr_ 1: r 45 <= 3ffffffffffffff80fff00001fffff44000000 -instret:5 PC:0x1ffff0000000000000000000080000000 instr:0x0000713d iType:Alu [doCommitNormalInst [0]] 1155 -instret:6 PC:0x1ffff0000000000000000000080000002 instr:0x0000a806 iType:St [doCommitTrap] 1157 -instret:7 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1166 -instret:8 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1175 -instret:9 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1184 -instret:10 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1193 -instret:11 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1202 -instret:12 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1211 -instret:13 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1220 -instret:14 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1229 -instret:15 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1238 -instret:16 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1247 -instret:17 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1256 -instret:18 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1265 -instret:19 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1274 -instret:20 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1283 -instret:21 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1292 -instret:22 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1301 -instret:23 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1310 -instret:24 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1319 -instret:25 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1328 -instret:26 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1337 -instret:27 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1346 -instret:28 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1355 -instret:29 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1364 -instret:30 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1373 -instret:31 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1382 -instret:32 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1391 -instret:33 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1400 -instret:34 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1409 -instret:35 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1418 -instret:36 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1427 -instret:37 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1436 -instret:38 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1445 -instret:39 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1454 -instret:40 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1463 -instret:41 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1472 -instret:42 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1481 -instret:43 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1490 -instret:44 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1499 -instret:45 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1508 -instret:46 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1517 -instret:47 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1526 -instret:48 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1535 -instret:49 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1544 -instret:50 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1553 -instret:51 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1562 -instret:52 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1571 -instret:53 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1580 -instret:54 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1589 -instret:55 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1598 -instret:56 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1607 -instret:57 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1616 -instret:58 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1625 -instret:59 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1634 -instret:60 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1643 -instret:61 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1652 -instret:62 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1661 -instret:63 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1670 -instret:64 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1679 -instret:65 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1688 -instret:66 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1697 -instret:67 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1706 -instret:68 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1715 -instret:69 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1724 -instret:70 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1733 -instret:71 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1742 -instret:72 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1751 -instret:73 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1760 -instret:74 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1769 -instret:75 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1778 -instret:76 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1787 -instret:77 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1796 -instret:78 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1805 -instret:79 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1814 -instret:80 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1823 -instret:81 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1832 -instret:82 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1841 -instret:83 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1850 -instret:84 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1859 -instret:85 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1868 -instret:86 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1877 -instret:87 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1886 -instret:88 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1895 -instret:89 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1904 -instret:90 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1913 -instret:91 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1922 -instret:92 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1931 -instret:93 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1940 -instret:94 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1949 -instret:95 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1958 -instret:96 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1967 -instret:97 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1976 -instret:98 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1985 -instret:99 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 1994 -instret:100 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2003 -instret:101 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2012 -instret:102 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2021 -instret:103 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2030 -instret:104 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2039 -instret:105 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2048 -instret:106 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2057 -instret:107 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2066 -instret:108 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2075 -instret:109 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2084 -instret:110 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2093 -instret:111 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2102 -instret:112 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2111 -instret:113 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2120 -instret:114 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2129 -instret:115 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2138 -instret:116 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2147 -instret:117 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2156 -instret:118 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2165 -instret:119 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2174 -instret:120 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2183 -instret:121 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2192 -instret:122 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2201 -instret:123 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2210 -instret:124 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2219 -instret:125 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2228 -instret:126 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2237 -instret:127 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2246 -instret:128 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2255 -instret:129 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2264 -instret:130 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2273 -instret:131 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2282 -instret:132 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2291 -instret:133 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2300 -instret:134 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2309 -instret:135 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2318 -instret:136 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2327 -instret:137 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2336 -instret:138 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2345 -instret:139 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2354 -instret:140 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2363 -instret:141 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2372 -instret:142 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2381 -instret:143 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2390 -instret:144 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2399 -instret:145 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2408 -instret:146 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2417 -instret:147 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2426 -instret:148 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2435 -instret:149 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2444 -instret:150 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2453 -instret:151 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2462 -instret:152 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2471 -instret:153 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2480 -instret:154 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2489 -instret:155 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2498 -instret:156 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2507 -instret:157 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2516 -instret:158 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2525 -instret:159 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2534 -instret:160 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2543 -instret:161 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2552 -instret:162 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2561 -instret:163 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2570 -instret:164 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2579 -instret:165 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2588 -instret:166 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2597 -instret:167 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2606 -instret:168 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2615 -instret:169 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2624 -instret:170 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2633 -instret:171 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2642 -instret:172 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2651 -instret:173 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2660 -instret:174 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2669 -instret:175 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2678 -instret:176 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2687 -instret:177 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2696 -instret:178 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2705 -instret:179 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2714 -instret:180 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2723 -instret:181 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2732 -instret:182 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2741 -instret:183 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2750 -instret:184 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2759 -instret:185 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2768 -instret:186 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2777 -instret:187 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2786 -instret:188 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2795 -instret:189 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2804 -instret:190 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2813 -instret:191 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2822 -instret:192 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2831 -instret:193 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2840 -instret:194 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2849 -instret:195 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2858 -instret:196 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2867 -instret:197 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2876 -instret:198 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2885 -instret:199 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2894 -instret:200 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2903 -instret:201 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2912 -instret:202 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2921 -instret:203 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2930 -instret:204 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2939 -instret:205 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2948 -instret:206 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2957 -instret:207 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2966 -instret:208 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2975 -instret:209 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2984 -instret:210 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 2993 -instret:211 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3002 -instret:212 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3011 -instret:213 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3020 -instret:214 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3029 -instret:215 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3038 -instret:216 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3047 -instret:217 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3056 -instret:218 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3065 -instret:219 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3074 -instret:220 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3083 -instret:221 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3092 -instret:222 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3101 -instret:223 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3110 -instret:224 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3119 -instret:225 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3128 -instret:226 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3137 -instret:227 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3146 -instret:228 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3155 -instret:229 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3164 -instret:230 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3173 -instret:231 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3182 -instret:232 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3191 -instret:233 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3200 -instret:234 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3209 -instret:235 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3218 -instret:236 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3227 -instret:237 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3236 -instret:238 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3245 -instret:239 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3254 -instret:240 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3263 -instret:241 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3272 -instret:242 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3281 -instret:243 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3290 -instret:244 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3299 -instret:245 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3308 -instret:246 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3317 -instret:247 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3326 -instret:248 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3335 -instret:249 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3344 -instret:250 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3353 -instret:251 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3362 -instret:252 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3371 -instret:253 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3380 -instret:254 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3389 -instret:255 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3398 -instret:256 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3407 -instret:257 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3416 -instret:258 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3425 -instret:259 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3434 -instret:260 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3443 -instret:261 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3452 -instret:262 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3461 -instret:263 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3470 -instret:264 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3479 -instret:265 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3488 -instret:266 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3497 -instret:267 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3506 -instret:268 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3515 -instret:269 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3524 -instret:270 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3533 -instret:271 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3542 -instret:272 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3551 -instret:273 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3560 -instret:274 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3569 -instret:275 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3578 -instret:276 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3587 -instret:277 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3596 -instret:278 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3605 -instret:279 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3614 -instret:280 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3623 -instret:281 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3632 -instret:282 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3641 -instret:283 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3650 -instret:284 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3659 -instret:285 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3668 -instret:286 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3677 -instret:287 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3686 -instret:288 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3695 -instret:289 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3704 -instret:290 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3713 -instret:291 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3722 -instret:292 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3731 -instret:293 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3740 -instret:294 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3749 -instret:295 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3758 -instret:296 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3767 -instret:297 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3776 -instret:298 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3785 -instret:299 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3794 -instret:300 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3803 -instret:301 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3812 -instret:302 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3821 -instret:303 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3830 -instret:304 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3839 -instret:305 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3848 -instret:306 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3857 -instret:307 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3866 -instret:308 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3875 -instret:309 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3884 -instret:310 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3893 -instret:311 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3902 -instret:312 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3911 -instret:313 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3920 -instret:314 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3929 -instret:315 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3938 -instret:316 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3947 -instret:317 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3956 -instret:318 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3965 -instret:319 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3974 -instret:320 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3983 -instret:321 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3992 -instret:322 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4001 -instret:323 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4010 -instret:324 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4019 -instret:325 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4028 -instret:326 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4037 -instret:327 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4046 -instret:328 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4055 -instret:329 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4064 -instret:330 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4073 -instret:331 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4082 -instret:332 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4091 -instret:333 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4100 -instret:334 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4109 -instret:335 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4118 -instret:336 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4127 -instret:337 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4136 -instret:338 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4145 -instret:339 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4154 -instret:340 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4163 -instret:341 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4172 -instret:342 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4181 -instret:343 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4190 -instret:344 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4199 -instret:345 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4208 -instret:346 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4217 -instret:347 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4226 -instret:348 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4235 -instret:349 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4244 -instret:350 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4253 -instret:351 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4262 -instret:352 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4271 -instret:353 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4280 -instret:354 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4289 -instret:355 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4298 -instret:356 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4307 -instret:357 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4316 -instret:358 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4325 -instret:359 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4334 -instret:360 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4343 -instret:361 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4352 -instret:362 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4361 -instret:363 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4370 -instret:364 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4379 -instret:365 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4388 -instret:366 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4397 -instret:367 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4406 -instret:368 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4415 -instret:369 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4424 -instret:370 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4433 -instret:371 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4442 -instret:372 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4451 -instret:373 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4460 -instret:374 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4469 -instret:375 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4478 -instret:376 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4487 -instret:377 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4496 -instret:378 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4505 -instret:379 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4514 -instret:380 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4523 -instret:381 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4532 -instret:382 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4541 -instret:383 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4550 -instret:384 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4559 -instret:385 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4568 -instret:386 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4577 -instret:387 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4586 -instret:388 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4595 -instret:389 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4604 -instret:390 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4613 -instret:391 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4622 -instret:392 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4631 -instret:393 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4640 -instret:394 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4649 -instret:395 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4658 -instret:396 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4667 -instret:397 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4676 -instret:398 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4685 -instret:399 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4694 -instret:400 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4703 -instret:401 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4712 -instret:402 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4721 -instret:403 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4730 -instret:404 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4739 -instret:405 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4748 -instret:406 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4757 -instret:407 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4766 -instret:408 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4775 -instret:409 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4784 -instret:410 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4793 -instret:411 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4802 -instret:412 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4811 -instret:413 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4820 -instret:414 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4829 -instret:415 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4838 -instret:416 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4847 -instret:417 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4856 -instret:418 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4865 -instret:419 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4874 -instret:420 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4883 -instret:421 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4892 -instret:422 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4901 -instret:423 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4910 -instret:424 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4919 -instret:425 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4928 -instret:426 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4937 -instret:427 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4946 -instret:428 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4955 -instret:429 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4964 -instret:430 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4973 -instret:431 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4982 -instret:432 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4991 -instret:433 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5000 -instret:434 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5009 -instret:435 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5018 -instret:436 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5027 -instret:437 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5036 -instret:438 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5045 -instret:439 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5054 -instret:440 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5063 -instret:441 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5072 -instret:442 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5081 -instret:443 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5090 -instret:444 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5099 -instret:445 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5108 -instret:446 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5117 -instret:447 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5126 -instret:448 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5135 -instret:449 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5144 -instret:450 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5153 -instret:451 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5162 -instret:452 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5171 -instret:453 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5180 -instret:454 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5189 -instret:455 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5198 -instret:456 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5207 -instret:457 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5216 -instret:458 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5225 -instret:459 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5234 -instret:460 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5243 -instret:461 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5252 -instret:462 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5261 -instret:463 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5270 -instret:464 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5279 -instret:465 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5288 -instret:466 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5297 -instret:467 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5306 -instret:468 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5315 -instret:469 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5324 -instret:470 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5333 -instret:471 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5342 -instret:472 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5351 -instret:473 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5360 -instret:474 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5369 -instret:475 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5378 -instret:476 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5387 -instret:477 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5396 -instret:478 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5405 -instret:479 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5414 -instret:480 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5423 -instret:481 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5432 -instret:482 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5441 -instret:483 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5450 -instret:484 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5459 -instret:485 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5468 -instret:486 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5477 -instret:487 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5486 -instret:488 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5495 -instret:489 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5504 -instret:490 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5513 -instret:491 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5522 -instret:492 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5531 -instret:493 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5540 -instret:494 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5549 -instret:495 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5558 -instret:496 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5567 -instret:497 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5576 -instret:498 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5585 -instret:499 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5594 -instret:500 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5603 -instret:501 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5612 -instret:502 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5621 -instret:503 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5630 -instret:504 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5639 -instret:505 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5648 -instret:506 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5657 -instret:507 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5666 -instret:508 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5675 -instret:509 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5684 -instret:510 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5693 -instret:511 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5702 -instret:512 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5711 -instret:513 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5720 -instret:514 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5729 -instret:515 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5738 -instret:516 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5747 -instret:517 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5756 -instret:518 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5765 -instret:519 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5774 -instret:520 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5783 -instret:521 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5792 -instret:522 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5801 -instret:523 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5810 -instret:524 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5819 -instret:525 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5828 -instret:526 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5837 -instret:527 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5846 -instret:528 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5855 -instret:529 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5864 -instret:530 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5873 -instret:531 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5882 -instret:532 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5891 -instret:533 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5900 -instret:534 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5909 -instret:535 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5918 -instret:536 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5927 -instret:537 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5936 -instret:538 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5945 -instret:539 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5954 -instret:540 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5963 -instret:541 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5972 -instret:542 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5981 -instret:543 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5990 -instret:544 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5999 -instret:545 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6008 -instret:546 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6017 -instret:547 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6026 -instret:548 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6035 -instret:549 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6044 -instret:550 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6053 -instret:551 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6062 -instret:552 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6071 -instret:553 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6080 -instret:554 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6089 -instret:555 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6098 -instret:556 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6107 -instret:557 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6116 -instret:558 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6125 -instret:559 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6134 -instret:560 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6143 -instret:561 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6152 -instret:562 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6161 -instret:563 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6170 -instret:564 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6179 -instret:565 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6188 -instret:566 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6197 -instret:567 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6206 -instret:568 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6215 -instret:569 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6224 -instret:570 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6233 -instret:571 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6242 -instret:572 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6251 -instret:573 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6260 -instret:574 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6269 -instret:575 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6278 -instret:576 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6287 -instret:577 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6296 -instret:578 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6305 -instret:579 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6314 -instret:580 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6323 -instret:581 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6332 -instret:582 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6341 -instret:583 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6350 -instret:584 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6359 -instret:585 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6368 -instret:586 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6377 -instret:587 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6386 -instret:588 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6395 -instret:589 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6404 -instret:590 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6413 -instret:591 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6422 -instret:592 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6431 -instret:593 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6440 -instret:594 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6449 -instret:595 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6458 -instret:596 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6467 -instret:597 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6476 -instret:598 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6485 -instret:599 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6494 -instret:600 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6503 -instret:601 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6512 -instret:602 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6521 -instret:603 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6530 -instret:604 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6539 -instret:605 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6548 -instret:606 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6557 -instret:607 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6566 -instret:608 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6575 -instret:609 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6584 -instret:610 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6593 -instret:611 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6602 -instret:612 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6611 -instret:613 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6620 -instret:614 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6629 -instret:615 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6638 -instret:616 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6647 -instret:617 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6656 -instret:618 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6665 -instret:619 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6674 -instret:620 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6683 -instret:621 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6692 -instret:622 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6701 -instret:623 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6710 -instret:624 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6719 -instret:625 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6728 -instret:626 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6737 -instret:627 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6746 -instret:628 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6755 -instret:629 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6764 -instret:630 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6773 -instret:631 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6782 -instret:632 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6791 -instret:633 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6800 -instret:634 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6809 -instret:635 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6818 -instret:636 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6827 -instret:637 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6836 -instret:638 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6845 -instret:639 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6854 -instret:640 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6863 -instret:641 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6872 -instret:642 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6881 -instret:643 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6890 -instret:644 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6899 -instret:645 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6908 -instret:646 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6917 -instret:647 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6926 -instret:648 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6935 -instret:649 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6944 -instret:650 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6953 -instret:651 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6962 -instret:652 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6971 -instret:653 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6980 -instret:654 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6989 -instret:655 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6998 -instret:656 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7007 -instret:657 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7016 -instret:658 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7025 -instret:659 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7034 -instret:660 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7043 -instret:661 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7052 -instret:662 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7061 -instret:663 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7070 -instret:664 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7079 -instret:665 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7088 -instret:666 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7097 -instret:667 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7106 -instret:668 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7115 -instret:669 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7124 -instret:670 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7133 -instret:671 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7142 -instret:672 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7151 -instret:673 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7160 -instret:674 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7169 -instret:675 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7178 -instret:676 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7187 -instret:677 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7196 -instret:678 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7205 -instret:679 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7214 -instret:680 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7223 -instret:681 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7232 -instret:682 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7241 -instret:683 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7250 -instret:684 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7259 -instret:685 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7268 -instret:686 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7277 -instret:687 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7286 -instret:688 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7295 -instret:689 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7304 -instret:690 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7313 -instret:691 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7322 -instret:692 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7331 -instret:693 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7340 -instret:694 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7349 -instret:695 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7358 -instret:696 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7367 -instret:697 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7376 -instret:698 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7385 -instret:699 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7394 -instret:700 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7403 -instret:701 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7412 -instret:702 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7421 -instret:703 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7430 -instret:704 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7439 -instret:705 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7448 -instret:706 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7457 -instret:707 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7466 -instret:708 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7475 -instret:709 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7484 -instret:710 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7493 -instret:711 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7502 -instret:712 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7511 -instret:713 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7520 -instret:714 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7529 -instret:715 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7538 -instret:716 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7547 -instret:717 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7556 -instret:718 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7565 -instret:719 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7574 -instret:720 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7583 -instret:721 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7592 -instret:722 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7601 -instret:723 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7610 -instret:724 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7619 -instret:725 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7628 -instret:726 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7637 -instret:727 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7646 -instret:728 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7655 -instret:729 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7664 -instret:730 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7673 -instret:731 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7682 -instret:732 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7691 -instret:733 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7700 -instret:734 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7709 -instret:735 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7718 -instret:736 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7727 -instret:737 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7736 -instret:738 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7745 -instret:739 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7754 -instret:740 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7763 -instret:741 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7772 -instret:742 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7781 -instret:743 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7790 -instret:744 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7799 -instret:745 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7808 -instret:746 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7817 -instret:747 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7826 -instret:748 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7835 -instret:749 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7844 -instret:750 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7853 -instret:751 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7862 -instret:752 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7871 -instret:753 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7880 -instret:754 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7889 -instret:755 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7898 -instret:756 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7907 -instret:757 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7916 -instret:758 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7925 -instret:759 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7934 -instret:760 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7943 -instret:761 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7952 -instret:762 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7961 -instret:763 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7970 -instret:764 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7979 -instret:765 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7988 -instret:766 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7997 -instret:767 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8006 -instret:768 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8015 -instret:769 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8024 -instret:770 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8033 -instret:771 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8042 -instret:772 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8051 -instret:773 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8060 -instret:774 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8069 -instret:775 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8078 -instret:776 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8087 -instret:777 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8096 -instret:778 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8105 -instret:779 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8114 -instret:780 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8123 -instret:781 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8132 -instret:782 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8141 -instret:783 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8150 -instret:784 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8159 -instret:785 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8168 -instret:786 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8177 -instret:787 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8186 -instret:788 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8195 -instret:789 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8204 -instret:790 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8213 -instret:791 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8222 -instret:792 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8231 -instret:793 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8240 -instret:794 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8249 -instret:795 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8258 -instret:796 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8267 -instret:797 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8276 -instret:798 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8285 -instret:799 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8294 -instret:800 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8303 -instret:801 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8312 -instret:802 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8321 -instret:803 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8330 -instret:804 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8339 -instret:805 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8348 -instret:806 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8357 -instret:807 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8366 -instret:808 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8375 -instret:809 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8384 -instret:810 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8393 -instret:811 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8402 -instret:812 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8411 -instret:813 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8420 -instret:814 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8429 -instret:815 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8438 -instret:816 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8447 -instret:817 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8456 -instret:818 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8465 -instret:819 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8474 -instret:820 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8483 -instret:821 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8492 -instret:822 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8501 -instret:823 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8510 -instret:824 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8519 -instret:825 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8528 -instret:826 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8537 -instret:827 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8546 -instret:828 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8555 -instret:829 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8564 -instret:830 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8573 -instret:831 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8582 -instret:832 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8591 -instret:833 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8600 -instret:834 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8609 -instret:835 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8618 -instret:836 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8627 -instret:837 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8636 -instret:838 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8645 -instret:839 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8654 -instret:840 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8663 -instret:841 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8672 -instret:842 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8681 -instret:843 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8690 -instret:844 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8699 -instret:845 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8708 -instret:846 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8717 -instret:847 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8726 -instret:848 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8735 -instret:849 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8744 -instret:850 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8753 -instret:851 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8762 -instret:852 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8771 -instret:853 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8780 -instret:854 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8789 -instret:855 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8798 -instret:856 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8807 -instret:857 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8816 -instret:858 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8825 -instret:859 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8834 -instret:860 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8843 -instret:861 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8852 -instret:862 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8861 -instret:863 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8870 -instret:864 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8879 -instret:865 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8888 -instret:866 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8897 -instret:867 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8906 -instret:868 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8915 -instret:869 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8924 -instret:870 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8933 -instret:871 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8942 -instret:872 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8951 -instret:873 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8960 -instret:874 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8969 -instret:875 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8978 -instret:876 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8987 -instret:877 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8996 -instret:878 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9005 -instret:879 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9014 -instret:880 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9023 -instret:881 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9032 -instret:882 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9041 -instret:883 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9050 -instret:884 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9059 -instret:885 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9068 -instret:886 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9077 -instret:887 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9086 -instret:888 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9095 -instret:889 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9104 -instret:890 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9113 -instret:891 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9122 -instret:892 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9131 -instret:893 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9140 -instret:894 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9149 -instret:895 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9158 -instret:896 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9167 -instret:897 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9176 -instret:898 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9185 -instret:899 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9194 -instret:900 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9203 -instret:901 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9212 -instret:902 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9221 -instret:903 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9230 -instret:904 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9239 -instret:905 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9248 -instret:906 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9257 -instret:907 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9266 -instret:908 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9275 -instret:909 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9284 -instret:910 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9293 -instret:911 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9302 -instret:912 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9311 -instret:913 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9320 -instret:914 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9329 -instret:915 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9338 -instret:916 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9347 -instret:917 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9356 -instret:918 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9365 -instret:919 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9374 -instret:920 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9383 -instret:921 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9392 -instret:922 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9401 -instret:923 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9410 -instret:924 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9419 -instret:925 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9428 -instret:926 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9437 -instret:927 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9446 -instret:928 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9455 -instret:929 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9464 -instret:930 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9473 -instret:931 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9482 -instret:932 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9491 -instret:933 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9500 -instret:934 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9509 -instret:935 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9518 -instret:936 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9527 -instret:937 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9536 -instret:938 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9545 -instret:939 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9554 -instret:940 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9563 -instret:941 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9572 -instret:942 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9581 -instret:943 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9590 -instret:944 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9599 -instret:945 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9608 -instret:946 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9617 -instret:947 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9626 -instret:948 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9635 -instret:949 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9644 -instret:950 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9653 -instret:951 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9662 -instret:952 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9671 -instret:953 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9680 -instret:954 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9689 -instret:955 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9698 -instret:956 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9707 -instret:957 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9716 -instret:958 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9725 -instret:959 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9734 -instret:960 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9743 -instret:961 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9752 -instret:962 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9761 -instret:963 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9770 -instret:964 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9779 -instret:965 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9788 -instret:966 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9797 -instret:967 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9806 -instret:968 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9815 -instret:969 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9824 -instret:970 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9833 -instret:971 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9842 -instret:972 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9851 -instret:973 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9860 -instret:974 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9869 -instret:975 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9878 -instret:976 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9887 -instret:977 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9896 -instret:978 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9905 -instret:979 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9914 -instret:980 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9923 -instret:981 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9932 -instret:982 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9941 -instret:983 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9950 -instret:984 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9959 -instret:985 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9968 -instret:986 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9977 -instret:987 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9986 -instret:988 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9995 -instret:989 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10004 -instret:990 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10013 -instret:991 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10022 -instret:992 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10031 -instret:993 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10040 -instret:994 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10049 -instret:995 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10058 -instret:996 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10067 -instret:997 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10076 -instret:998 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10085 -instret:999 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10094 -instret:1000 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10103 -instret:1001 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10112 -instret:1002 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10121 -instret:1003 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10130 -instret:1004 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10139 -instret:1005 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10148 -instret:1006 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10157 -instret:1007 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10166 -instret:1008 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10175 -instret:1009 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10184 -instret:1010 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10193 -instret:1011 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10202 -instret:1012 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10211 -instret:1013 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10220 -instret:1014 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10229 -instret:1015 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10238 -instret:1016 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10247 -instret:1017 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10256 -instret:1018 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10265 -instret:1019 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10274 -instret:1020 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10283 -instret:1021 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10292 -instret:1022 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10301 -instret:1023 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10310 -instret:1024 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10319 -instret:1025 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10328 -instret:1026 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10337 -instret:1027 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10346 -instret:1028 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10355 -instret:1029 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10364 -instret:1030 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10373 -instret:1031 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10382 -instret:1032 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10391 -instret:1033 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10400 -instret:1034 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10409 -instret:1035 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10418 -instret:1036 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10427 -instret:1037 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10436 -instret:1038 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10445 -instret:1039 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10454 -instret:1040 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10463 -instret:1041 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10472 -instret:1042 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10481 -instret:1043 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10490 -instret:1044 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10499 -instret:1045 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10508 -instret:1046 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10517 -instret:1047 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10526 -instret:1048 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10535 -instret:1049 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10544 -instret:1050 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10553 -instret:1051 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10562 -instret:1052 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10571 -instret:1053 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10580 -instret:1054 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10589 -instret:1055 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10598 -instret:1056 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10607 -instret:1057 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10616 -instret:1058 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10625 -instret:1059 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10634 -instret:1060 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10643 -instret:1061 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10652 -instret:1062 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10661 -instret:1063 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10670 -instret:1064 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10679 -instret:1065 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10688 -instret:1066 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10697 -instret:1067 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10706 -instret:1068 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10715 -instret:1069 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10724 -instret:1070 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10733 -instret:1071 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10742 -instret:1072 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10751 -instret:1073 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10760 -instret:1074 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10769 -instret:1075 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10778 -instret:1076 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10787 -instret:1077 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10796 -instret:1078 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10805 -instret:1079 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10814 -instret:1080 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10823 -instret:1081 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10832 -instret:1082 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10841 -instret:1083 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10850 -instret:1084 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10859 -instret:1085 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10868 -instret:1086 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10877 -instret:1087 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10886 -instret:1088 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10895 -instret:1089 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10904 -instret:1090 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10913 -instret:1091 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10922 -instret:1092 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10931 -instret:1093 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10940 -instret:1094 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10949 -instret:1095 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10958 -instret:1096 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10967 -instret:1097 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10976 -instret:1098 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10985 -instret:1099 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10994 -instret:1100 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11003 -instret:1101 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11012 -instret:1102 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11021 -instret:1103 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11030 -instret:1104 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11039 -instret:1105 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11048 -instret:1106 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11057 -instret:1107 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11066 -instret:1108 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11075 -instret:1109 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11084 -instret:1110 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11093 -instret:1111 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11102 -instret:1112 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11111 -instret:1113 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11120 -instret:1114 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11129 -instret:1115 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11138 -instret:1116 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11147 -instret:1117 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11156 -instret:1118 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11165 -instret:1119 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11174 -instret:1120 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11183 -instret:1121 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11192 -instret:1122 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11201 -instret:1123 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11210 -instret:1124 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11219 -instret:1125 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11228 -instret:1126 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11237 -instret:1127 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11246 -instret:1128 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11255 -instret:1129 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11264 -instret:1130 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11273 -instret:1131 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11282 -instret:1132 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11291 -instret:1133 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11300 -instret:1134 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11309 -instret:1135 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11318 -instret:1136 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11327 -instret:1137 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11336 -instret:1138 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11345 -instret:1139 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11354 -instret:1140 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11363 -instret:1141 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11372 -instret:1142 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11381 -instret:1143 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11390 -instret:1144 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11399 -instret:1145 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11408 -instret:1146 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11417 -instret:1147 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11426 -instret:1148 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11435 -instret:1149 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11444 -instret:1150 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11453 -instret:1151 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11462 -instret:1152 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11471 -instret:1153 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11480 -instret:1154 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11489 -instret:1155 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11498 -instret:1156 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11507 -instret:1157 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11516 -instret:1158 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11525 -instret:1159 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11534 -instret:1160 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11543 -instret:1161 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11552 -instret:1162 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11561 -instret:1163 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11570 -instret:1164 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11579 -instret:1165 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11588 -instret:1166 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11597 -instret:1167 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11606 -instret:1168 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11615 -instret:1169 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11624 -instret:1170 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11633 -instret:1171 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11642 -instret:1172 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11651 -instret:1173 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11660 -instret:1174 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11669 -instret:1175 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11678 -instret:1176 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11687 -instret:1177 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11696 -instret:1178 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11705 -instret:1179 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11714 -instret:1180 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11723 -instret:1181 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11732 -instret:1182 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11741 -instret:1183 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11750 -instret:1184 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11759 -instret:1185 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11768 -instret:1186 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11777 -instret:1187 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11786 -instret:1188 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11795 -instret:1189 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11804 -instret:1190 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11813 -instret:1191 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11822 -instret:1192 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11831 -instret:1193 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11840 -instret:1194 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11849 -instret:1195 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11858 -instret:1196 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11867 -instret:1197 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11876 -instret:1198 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11885 -instret:1199 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11894 -instret:1200 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11903 -instret:1201 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11912 -instret:1202 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11921 -instret:1203 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11930 -instret:1204 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11939 -instret:1205 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11948 -instret:1206 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11957 -instret:1207 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11966 -instret:1208 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11975 -instret:1209 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11984 -instret:1210 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11993 -instret:1211 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12002 -instret:1212 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12011 -instret:1213 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12020 -instret:1214 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12029 -instret:1215 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12038 -instret:1216 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12047 -instret:1217 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12056 -instret:1218 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12065 -instret:1219 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12074 -instret:1220 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12083 -instret:1221 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12092 -instret:1222 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12101 -instret:1223 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12110 -instret:1224 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12119 -instret:1225 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12128 -instret:1226 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12137 -instret:1227 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12146 -instret:1228 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12155 -instret:1229 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12164 -instret:1230 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12173 -instret:1231 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12182 -instret:1232 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12191 -instret:1233 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12200 -instret:1234 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12209 -instret:1235 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12218 -instret:1236 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12227 -instret:1237 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12236 -instret:1238 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12245 -instret:1239 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12254 -instret:1240 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12263 -instret:1241 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12272 -instret:1242 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12281 -instret:1243 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12290 -instret:1244 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12299 -instret:1245 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12308 -instret:1246 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12317 -instret:1247 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12326 -instret:1248 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12335 -instret:1249 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12344 -instret:1250 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12353 -instret:1251 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12362 -instret:1252 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12371 -instret:1253 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12380 -instret:1254 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12389 -instret:1255 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12398 -instret:1256 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12407 -instret:1257 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12416 -instret:1258 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12425 -instret:1259 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12434 -instret:1260 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12443 -instret:1261 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12452 -instret:1262 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12461 -instret:1263 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12470 -instret:1264 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12479 -instret:1265 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12488 -instret:1266 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12497 -instret:1267 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12506 -instret:1268 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12515 -instret:1269 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12524 -instret:1270 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12533 -instret:1271 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12542 -instret:1272 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12551 -instret:1273 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12560 -instret:1274 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12569 -instret:1275 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12578 -instret:1276 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12587 -instret:1277 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12596 -instret:1278 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12605 -instret:1279 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12614 -instret:1280 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12623 -instret:1281 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12632 -instret:1282 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12641 -instret:1283 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12650 -instret:1284 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12659 -instret:1285 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12668 -instret:1286 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12677 -instret:1287 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12686 -instret:1288 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12695 -instret:1289 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12704 -instret:1290 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12713 -instret:1291 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12722 -instret:1292 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12731 -instret:1293 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12740 -instret:1294 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12749 -instret:1295 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12758 -instret:1296 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12767 -instret:1297 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12776 -instret:1298 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12785 -instret:1299 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12794 -instret:1300 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12803 -instret:1301 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12812 -instret:1302 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12821 -instret:1303 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12830 -instret:1304 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12839 -instret:1305 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12848 -instret:1306 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12857 -instret:1307 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12866 -instret:1308 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12875 -instret:1309 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12884 -instret:1310 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12893 -instret:1311 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12902 -instret:1312 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12911 -instret:1313 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12920 -instret:1314 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12929 -instret:1315 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12938 -instret:1316 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12947 -instret:1317 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12956 -instret:1318 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12965 -instret:1319 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12974 -instret:1320 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12983 -instret:1321 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12992 -instret:1322 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13001 -instret:1323 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13010 -instret:1324 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13019 -instret:1325 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13028 -instret:1326 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13037 -instret:1327 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13046 -instret:1328 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13055 -instret:1329 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13064 -instret:1330 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13073 -instret:1331 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13082 -instret:1332 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13091 -instret:1333 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13100 -instret:1334 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13109 -instret:1335 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13118 -instret:1336 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13127 -instret:1337 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13136 -instret:1338 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13145 -instret:1339 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13154 -instret:1340 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13163 -instret:1341 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13172 -instret:1342 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13181 -instret:1343 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13190 -instret:1344 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13199 -instret:1345 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13208 -instret:1346 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13217 -instret:1347 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13226 -instret:1348 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13235 -instret:1349 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13244 -instret:1350 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13253 -instret:1351 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13262 -instret:1352 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13271 -instret:1353 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13280 -instret:1354 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13289 -instret:1355 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13298 -instret:1356 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13307 -instret:1357 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13316 -instret:1358 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13325 -instret:1359 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13334 -instret:1360 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13343 -instret:1361 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13352 -instret:1362 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13361 -instret:1363 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13370 -instret:1364 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13379 -instret:1365 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13388 -instret:1366 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13397 -instret:1367 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13406 -instret:1368 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13415 -instret:1369 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13424 -instret:1370 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13433 -instret:1371 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13442 -instret:1372 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13451 -instret:1373 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13460 -instret:1374 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13469 -instret:1375 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13478 -instret:1376 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13487 -instret:1377 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13496 -instret:1378 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13505 -instret:1379 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13514 -instret:1380 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13523 -instret:1381 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13532 -instret:1382 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13541 -instret:1383 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13550 -instret:1384 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13559 -instret:1385 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13568 -instret:1386 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13577 -instret:1387 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13586 -instret:1388 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13595 -instret:1389 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13604 -instret:1390 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13613 -instret:1391 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13622 -instret:1392 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13631 -instret:1393 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13640 -instret:1394 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13649 -instret:1395 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13658 -instret:1396 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13667 -instret:1397 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13676 -instret:1398 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13685 -instret:1399 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13694 -instret:1400 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13703 -instret:1401 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13712 -instret:1402 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13721 -instret:1403 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13730 -instret:1404 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13739 -instret:1405 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13748 -instret:1406 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13757 -instret:1407 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13766 -instret:1408 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13775 -instret:1409 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13784 -instret:1410 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13793 -instret:1411 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13802 -instret:1412 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13811 -instret:1413 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13820 -instret:1414 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13829 -instret:1415 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13838 -instret:1416 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13847 -instret:1417 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13856 -instret:1418 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13865 -instret:1419 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13874 -instret:1420 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13883 -instret:1421 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13892 -instret:1422 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13901 -instret:1423 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13910 -instret:1424 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13919 -instret:1425 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13928 -instret:1426 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13937 -instret:1427 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13946 -instret:1428 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13955 -instret:1429 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13964 -instret:1430 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13973 -instret:1431 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13982 -instret:1432 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13991 -instret:1433 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14000 -instret:1434 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14009 -instret:1435 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14018 -instret:1436 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14027 -instret:1437 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14036 -instret:1438 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14045 -instret:1439 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14054 -instret:1440 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14063 -instret:1441 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14072 -instret:1442 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14081 -instret:1443 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14090 -instret:1444 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14099 -instret:1445 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14108 -instret:1446 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14117 -instret:1447 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14126 -instret:1448 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14135 -instret:1449 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14144 -instret:1450 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14153 -instret:1451 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14162 -instret:1452 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14171 -instret:1453 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14180 -instret:1454 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14189 -instret:1455 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14198 -instret:1456 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14207 -instret:1457 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14216 -instret:1458 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14225 -instret:1459 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14234 -instret:1460 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14243 -instret:1461 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14252 -instret:1462 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14261 -instret:1463 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14270 -instret:1464 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14279 -instret:1465 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14288 -instret:1466 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14297 -instret:1467 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14306 -instret:1468 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14315 -instret:1469 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14324 -instret:1470 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14333 -instret:1471 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14342 -instret:1472 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14351 -instret:1473 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14360 -instret:1474 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14369 -instret:1475 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14378 -instret:1476 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14387 -instret:1477 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14396 -instret:1478 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14405 -instret:1479 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14414 -instret:1480 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14423 -instret:1481 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14432 -instret:1482 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14441 -instret:1483 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14450 -instret:1484 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14459 -instret:1485 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14468 -instret:1486 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14477 -instret:1487 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14486 -instret:1488 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14495 -instret:1489 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14504 -instret:1490 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14513 -instret:1491 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14522 -instret:1492 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14531 -instret:1493 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14540 -instret:1494 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14549 -instret:1495 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14558 -instret:1496 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14567 -instret:1497 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14576 -instret:1498 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14585 -instret:1499 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14594 -instret:1500 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14603 -instret:1501 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14612 -instret:1502 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14621 -instret:1503 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14630 -instret:1504 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14639 -instret:1505 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14648 -instret:1506 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14657 -instret:1507 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14666 -instret:1508 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14675 -instret:1509 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14684 -instret:1510 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14693 -instret:1511 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14702 -instret:1512 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14711 -instret:1513 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14720 -instret:1514 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14729 -instret:1515 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14738 -instret:1516 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14747 -instret:1517 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14756 -instret:1518 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14765 -instret:1519 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14774 -instret:1520 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14783 -instret:1521 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14792 -instret:1522 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14801 -instret:1523 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14810 -instret:1524 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14819 -instret:1525 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14828 -instret:1526 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14837 -instret:1527 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14846 -instret:1528 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14855 -instret:1529 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14864 -instret:1530 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14873 -instret:1531 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14882 -instret:1532 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14891 -instret:1533 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14900 -instret:1534 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14909 -instret:1535 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14918 -instret:1536 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14927 -instret:1537 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14936 -instret:1538 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14945 -instret:1539 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14954 -instret:1540 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14963 -instret:1541 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14972 -instret:1542 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14981 -instret:1543 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14990 -instret:1544 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14999 -instret:1545 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15008 -instret:1546 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15017 -instret:1547 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15026 -instret:1548 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15035 -instret:1549 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15044 -instret:1550 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15053 -instret:1551 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15062 -instret:1552 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15071 -instret:1553 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15080 -instret:1554 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15089 -instret:1555 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15098 -instret:1556 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15107 -instret:1557 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15116 -instret:1558 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15125 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle 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+calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00080000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipcc, execFunc: tagged Alu Add, capFunc: tagged CapModify tagged SpecialRW tagged TCC , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrPCC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h48, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h48, src2: tagged Valid 'h48, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000316 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 46 <= 0000000000020000000000001fffff44000000 +[RFile] wr_ 1: r 45 <= 40000000200000000000ffff1fffff44000000 +calling cycle +[RFile] wr_ 1: r 47 <= 0000000000020000400000001fffff44000000 +instret:5 PC:0x1ffff0000000000000000000080000000 instr:0x020000db iType:Auipcc [doCommitNormalInst [0]] 1155 +instret:6 PC:0x1ffff0000000000000000000080000004 instr:0x000802b7 iType:Alu [doCommitNormalInst [1]] 1155 +calling cycle +[RFile] wr_ 0: r 48 <= 0000000020000400000000001fffff44000000 +instret:7 PC:0x1ffff0000000000000000000080000008 instr:0x00002285 iType:Alu [doCommitNormalInst [0]] 1156 +calling cycle +[RFile] wr_ 0: r 4a <= 0000000020000004000000001fffff44000000 +[RFile] wr_ 1: r 49 <= 0000000020000400000000001fffff44000000 +instret:8 PC:0x1ffff000000000000000000008000000a instr:0x000002b2 iType:Alu [doCommitNormalInst [0]] 1157 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4b <= 0000000020000006000000001fffff44000000 +[ALU redirect - 1] 'h1ffff0000000000000000000080000326; 'h0; InstTag { way: 'h1, ptr: 'h05, t: 'h0b } + 11580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:9 PC:0x1ffff000000000000000000008000000c instr:0x2052815b iType:Cap [doCommitNormalInst [0]] 1158 +instret:10 PC:0x1ffff0000000000000000000080000010 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1158 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h05, t: 'h0b } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:11 PC:0x1ffff0000000000000000000080000014 instr:0x316080e7 iType:Jr [doCommitNormalInst [0]] 1160 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 12640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 12650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff8 +After delta: vaddr = 0x80000ff8 + 12650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffcee }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4c <= 00000000200003e8000000001fffff44000000 + 12660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000018 o: 'h0000000080000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: True, capStore: False, potentialCapLoad: False } + 12660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff0 +After delta: vaddr = 0x80000ff0 + 12660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4f <= 0000000020000400000000001fffff44000000 + 12670 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } + 12670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: True, capStore: False, potentialCapLoad: False } + 12670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffec, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fec +After delta: vaddr = 0x80000fec +instret:12 PC:0x1ffff0000000000000000000080000326 instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 1267 +calling cycle +[RFile] wr_ 0: r 50 <= 0000000000000000000000001fffff44000000 + 12680 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } + 12680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffec, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fec, write: True, capStore: False, potentialCapLoad: False } +instret:13 PC:0x1ffff0000000000000000000080000328 instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 1268 +calling cycle +[RFile] wr_ 0: r 52 <= 00000000200000cd000000001fffff44000000 + 12690 : [doFinishMem] DTlbResp { resp: <'h0000000080000fec,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fec, check_high: 'h00000000080000ff0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8328 } + 12690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } +instret:14 PC:0x1ffff000000000000000000008000032a instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 1269 +instret:15 PC:0x1ffff000000000000000000008000032c instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 1269 +calling cycle +[RFile] wr_ 1: r 53 <= 00000000200000cf000000001fffff44000000 +[ALU redirect - 1] 'h1ffff0000000000000000000080000022; 'h0; InstTag { way: 'h1, ptr: 'h09, t: 'h13 } + 12700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 12700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } + 12700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:16 PC:0x1ffff000000000000000000008000032e instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 1270 +instret:17 PC:0x1ffff0000000000000000000080000330 instr:0xfea42623 iType:St [doCommitNormalInst [1]] 1270 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h09, t: 'h13 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 12720 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000ff8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +instret:18 PC:0x1ffff0000000000000000000080000334 instr:0x00000097 iType:Auipc [doCommitNormalInst [0]] 1272 +instret:19 PC:0x1ffff0000000000000000000080000338 instr:0xcee080e7 iType:Jr [doCommitNormalInst [1]] 1272 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 13210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 13220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 13220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 54 <= 00000000200003cc000000001fffff44000000 + 13230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000033c o: 'h000000008000033c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 13230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 13230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 57 <= 00000000200003e8000000001fffff44000000 + 13240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 13240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } + 13240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 13240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:20 PC:0x1ffff0000000000000000000080000022 instr:0x00007159 iType:Alu [doCommitNormalInst [0]] 1324 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000003de }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 13250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 13250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 13250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +instret:21 PC:0x1ffff0000000000000000000080000024 instr:0x0000f486 iType:St [doCommitNormalInst [0]] 1325 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 13260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 13260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +instret:22 PC:0x1ffff0000000000000000000080000026 instr:0x0000f0a2 iType:St [doCommitNormalInst [0]] 1326 +instret:23 PC:0x1ffff0000000000000000000080000028 instr:0x00001880 iType:Alu [doCommitNormalInst [1]] 1326 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 13270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 13270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h802e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 13270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:24 PC:0x1ffff000000000000000000008000002a instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1327 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00010000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5d <= 000000002000040e800000001fffff44000000 + 13280 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000000000000001fffff44000000 + 13280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001418 +After delta: vaddr = 0x80001418 + 13280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h027 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5e <= 0000000020000506000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 13290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001418, write: False, capStore: False, potentialCapLoad: False } + 13290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 13300 : [doFinishMem] DTlbResp { resp: <'h0000000080001418,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001418, check_high: 'h00000000080001420, check_inclusive: True } }, specBits: 'h000 } + 13300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080001418, shiftedBE: tagged DataMemAccess , pcHash: 'h8042 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 13300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 13300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 13300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080001418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } +instret:25 PC:0x1ffff000000000000000000008000002e instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 1330 +calling cycle +[RFile] wr_ 0: r 5a <= 0000000000000001c00000001fffff44000000 +[RFile] wr_ 1: r 62 <= 0000000000004000000000001fffff44000000 + 13310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 13310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 13310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 13310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080001418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } + 13310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 13310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +calling cycle +[RFile] wr_ 0: r 63 <= 0000000000004000400000001fffff44000000 +[RFile] wr_ 1: r 5b <= 0000000000000000000000001fffff44000000 + 13320 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 60 <= 0000000000000000000000001fffff44000000 + 13320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +instret:26 PC:0x1ffff0000000000000000000080000032 instr:0x0000051d iType:Alu [doCommitNormalInst [0]] 1332 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 13330 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080001418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001418, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 13330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } +instret:27 PC:0x1ffff0000000000000000000080000034 instr:0x00009961 iType:Alu [doCommitNormalInst [0]] 1333 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000003aa }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 13340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:28 PC:0x1ffff0000000000000000000080000036 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1334 +instret:29 PC:0x1ffff000000000000000000008000003a instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1334 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 13350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 +instret:30 PC:0x1ffff000000000000000000008000003e instr:0x3de50513 iType:Alu [doCommitNormalInst [0]] 1335 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 66 <= 40000000000000000000ffff1fffff44000000 + 13360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } + 13360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 68 <= 000000002000041b800000001fffff44000000 + 13370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h001 } + 13370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 13370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 69 <= 0000000020000506000000001fffff44000000 + 13380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } + 13380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001418 +After delta: vaddr = 0x80001418 +calling cycle +[RFile] wr_ 1: r 6c <= 000000002000041f000000001fffff44000000 + 13390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } + 13390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001418, write: False, capStore: False, potentialCapLoad: False } +calling cycle + 13400 : [doFinishMem] DTlbResp { resp: <'h0000000080001418,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001418, check_high: 'h00000000080001420, check_inclusive: True } }, specBits: 'h001 } + 13400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080001418, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 13400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080001418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } +calling cycle + 13410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 13410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080001418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 13410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 14240 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000ff8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 14250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14250 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 14250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h832a } + 14260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +calling cycle + 14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } + 14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fec, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8330 } + 14280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } +calling cycle + 14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } + 14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8024 } + 14300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } +calling cycle + 14310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } + 14310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +calling cycle +calling cycle + 14330 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f98, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 14760 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001418, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 14770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14770 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 14770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080001418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } + 14770 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } + 14770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 +calling cycle + 14780 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5f <= 0000000000000000000000001fffff44000000 + 14780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080001418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 14780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 14780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080001418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 14780 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } + 14780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080001418, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 14790 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6b <= 0000000000000000000000001fffff44000000 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } +instret:31 PC:0x1ffff0000000000000000000080000042 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 1480 +calling cycle +[RFile] wr_ 1: r 61 <= 0000000000000000000000001fffff44000000 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00010000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h027 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 15150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 15160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, data: TaggedData { tag: False, data: } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 62 <= 0000000000004000000000001fffff44000000 + 15170 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 60 <= 0000000000000000000000001fffff44000000 + 15170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000003aa }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 63 <= 0000000000004000400000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 15180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 66 <= 40000000000000000000ffff1fffff44000000 + 15190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } +instret:32 PC:0x1ffff0000000000000000000080000044 instr:0xfd843583 iType:Ld [doCommitNormalInst [0]] 1519 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000003a4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 61 <= 0000000000000000000000001fffff44000000 + 15200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h001 } + 15200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 68 <= 000000002000041b800000001fffff44000000 + 15210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 15210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:33 PC:0x1ffff0000000000000000000080000048 instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 1521 +instret:34 PC:0x1ffff000000000000000000008000004a instr:0x000065c1 iType:Alu [doCommitNormalInst [1]] 1521 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6c <= 000000002000041f000000001fffff44000000 +[RFile] wr_ 1: r 69 <= 0000000020000506000000001fffff44000000 + 15220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } + 15220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001418 +After delta: vaddr = 0x80001418 + 15220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:35 PC:0x1ffff000000000000000000008000004c instr:0x00002585 iType:Alu [doCommitNormalInst [0]] 1522 +instret:36 PC:0x1ffff000000000000000000008000004e instr:0x00b57463 iType:Br [doCommitNormalInst [1]] 1522 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6d <= 0000000020000508000000001fffff44000000 + 15230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 15230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001418, write: False, capStore: False, potentialCapLoad: False } + 15230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 15230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:37 PC:0x1ffff0000000000000000000080000052 instr:0x0140006f iType:J [doCommitNormalInst [0]] 1523 +instret:38 PC:0x1ffff0000000000000000000080000066 instr:0x0210055b iType:Cap [doCommitNormalInst [1]] 1523 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 15240 : [doFinishMem] DTlbResp { resp: <'h0000000080001418,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001418, check_high: 'h00000000080001420, check_inclusive: True } }, specBits: 'h000 } + 15240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080001418, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 15240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } + 15240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 15240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080001418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } +instret:39 PC:0x1ffff000000000000000000008000006a instr:0xfca44023 iType:St [doCommitNormalInst [0]] 1524 +instret:40 PC:0x1ffff000000000000000000008000006e instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1524 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 15250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h808a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 15250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 15250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080001418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 15250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 15250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080001418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 15250 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } + 15250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 15250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:41 PC:0x1ffff0000000000000000000080000072 instr:0x3aa50513 iType:Alu [doCommitNormalInst [0]] 1525 +instret:42 PC:0x1ffff0000000000000000000080000076 instr:0xf8a43c23 iType:St [doCommitNormalInst [1]] 1525 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 15260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h808e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 15260 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6b <= 0000000000000000000000001fffff44000000 + 15260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 15260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 15260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080001418, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 15270 : [doRespLdForward] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 70 <= 40000000000000000000ffff1fffff44000000 + 15270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + 15270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } + 15270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 15270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 15270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 15280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 15280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 15280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 15280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 15280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } +instret:43 PC:0x1ffff000000000000000000008000007a instr:0x0000610c iType:Ld [doCommitNormalInst [0]] 1528 +instret:44 PC:0x1ffff000000000000000000008000007c instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1528 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15290 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f58, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[RFile] wr_ 1: r 6e <= 0000000020000508000000001fffff44000000 + 15290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 15290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 15290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001420 o: 'h0000000080001420 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 15290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 15290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 15290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 +instret:45 PC:0x1ffff0000000000000000000080000080 instr:0x3a450513 iType:Alu [doCommitNormalInst [0]] 1529 +calling cycle + 15300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 15300 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 + 15300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } +instret:46 PC:0x1ffff0000000000000000000080000084 instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 1530 +calling cycle +[RFile] wr_ 0: r 79 <= 0000000000000002800000001fffff44000000 + 15310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 15310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 15310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } +instret:47 PC:0x1ffff0000000000000000000080000086 instr:0xfaa43c23 iType:St [doCommitNormalInst [0]] 1531 +calling cycle +[RFile] wr_ 1: r 7a <= 000000002000002c000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 15320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + 15320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h0 +calling cycle +[RFile] wr_ 0: r 7b <= 000000002000002e000000001fffff44000000 +[ALU redirect - 0] 'h1ffff00000000000000000000800000e2; 'h0; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } +instret:48 PC:0x1ffff000000000000000000008000008a instr:0xfc04250f iType:Ld [doCommitNormalInst [0]] 1533 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +calling cycle +calling cycle +calling cycle + 15380 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f98, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 15390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15390 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 15390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8026 } + 15400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } +calling cycle + 15410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } + 15410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 15410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h802a } + 15420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } +calling cycle + 15430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } + 15430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h3 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 15830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 15830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7c <= 00000000200003bc000000001fffff44000000 + 15840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } + 15840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 15840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7f <= 00000000200003cc000000001fffff44000000 + 15850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 15850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } + 15850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + 15850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 15860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: True, capStore: False, potentialCapLoad: False } + 15860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 15860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 15870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } + 15870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c +calling cycle + 15880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 15880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 15880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False } + 15880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } +calling cycle + 15890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 15890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +calling cycle + 15900 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000 +calling cycle + 15910 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f10, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 16060 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f58, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 16070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16070 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 16070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } + 16070 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } + 16070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 +calling cycle + 16080 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000000000000000000001fffff44000000 + 16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 16080 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 16090 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000000000000000000001fffff44000000 + 16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + 16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + 16090 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 16090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16100 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000000000000000000001fffff44000000 + 16100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } + 16100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 16100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 16100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 16100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8036 } + 16110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } +calling cycle + 16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } + 16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h806a } + 16130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806a } +calling cycle + 16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806a } + 16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8076 } + 16150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } +calling cycle + 16160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } + 16160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 16450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 16460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h808e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 16460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 16460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16470 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 71 <= 0000000020000508000000001fffff44000000 + 16470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + 16470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 16480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 16480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 16480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 16490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 16490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } + 16490 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 16490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 16490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } +instret:49 PC:0x1ffff000000000000000000008000008e instr:0xfb843583 iType:Ld [doCommitNormalInst [0]] 1649 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 72 <= 40000000200005080000ffff1fffff44000000 + 16500 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000000000000000000001fffff44000000 + 16500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001420 o: 'h0000000080001420 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } + 16500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } + 16500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } + 16500 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } + 16500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 0000000000000002800000001fffff44000000 + 16510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 16510 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 + 16510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + 16510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:50 PC:0x1ffff0000000000000000000080000092 instr:0x20b5055b iType:Cap [doCommitNormalInst [0]] 1651 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7a <= 000000002000002c000000001fffff44000000 + 16520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 16520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 16520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:51 PC:0x1ffff0000000000000000000080000096 instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 1652 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7b <= 000000002000002e000000001fffff44000000 +[RFile] wr_ 1: r 7c <= 00000000200003bc000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 16530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } + 16530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 16530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 76 <= 0000000000000000000000001ffff800000000 +[RFile] wr_ 1: r 7f <= 00000000200003cc000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 16540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 16540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h00000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: True } + 16540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 16540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 16550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } + 16550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + 16550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 16560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: True, capStore: False, potentialCapLoad: False } + 16560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 16560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 16570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } + 16570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + 16570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 16580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False } + 16580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef0 +After delta: vaddr = 0x80000ef0 + 16580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 16590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 16590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True } + 16590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 16590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h4 + 16590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 16590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 16600 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 16600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16600 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000 + 16600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } + 16600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 16600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } +calling cycle +calling cycle + 16620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 16620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +calling cycle +calling cycle + 16640 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000ef0, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16680 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f10, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 16680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16690 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 16690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 16690 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 16690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 16690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 16690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16700 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: } } + 16700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + 16700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } + 16700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 16700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 16700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 16700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8086 } + 16710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 16710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 16710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 16710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 16710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 16710 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } + 16710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8086 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 16720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 16720 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8086 } + 16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8086 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8096 } + 16730 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16730 : [doRespLdForward] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 74 <= 40000000200005080000ffff1fffff44000000 + 16730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + 16730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 79 <= 0000000000000002800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 16740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 16740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 16740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } + 16740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e } + 16740 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } + 16740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8096 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7a <= 000000002000002c000000001fffff44000000 + 16750 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8096 } + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8096 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:52 PC:0x1ffff000000000000000000008000009a instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 1675 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7b <= 000000002000002e000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 16760 : [doRespLdForward] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 78 <= 40000000200005080000ffff1fffff44000000 + 16760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 16760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7c <= 00000000200003bc000000001fffff44000000 + 16770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } + 16770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 16770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:53 PC:0x1ffff000000000000000000008000009e instr:0xfd843583 iType:Ld [doCommitNormalInst [0]] 1677 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7f <= 00000000200003cc000000001fffff44000000 +[RFile] wr_ 1: r 76 <= 40000000200005081420ffff1ffff805081420 + 16780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 16780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001420 o: 'h0000000000000000 b: 'h0000000080001420 t: 'h00000000080001420 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } + 16780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 16780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 16790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } + 16790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 16790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:54 PC:0x1ffff00000000000000000000800000a2 instr:0x10b5055b iType:Cap [doCommitNormalInst [0]] 1679 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 16800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001420 o: 'h0000000080001420 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: True, potentialCapLoad: True } + 16800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + 16800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:55 PC:0x1ffff00000000000000000000800000a6 instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 1680 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 16810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80a6 } + 16810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: True, capStore: False, potentialCapLoad: False } + 16810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 16810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 16820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } + 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a6 } + 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + 16820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 16830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 16830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False } + 16830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef0 +After delta: vaddr = 0x80000ef0 + 16830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 16840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 16840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 16840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True } + 16840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 16840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 02 <= 00000000200003cc000000001fffff44000000 + 16850 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 16850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16850 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000 + 16850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } + 16850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 16850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 16860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 16860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 16860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } + 16860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 16860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 16870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 16870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 16870 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 000000002000002e000000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16880 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 00000000200003e8000000001fffff44000000 + 16880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 16890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } + 16900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 16900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 16910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 16910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 16910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 16920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h80c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + 16920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 16920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 16920 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 16920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 16920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 16930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 16930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16930 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 0000000020000506000000001fffff44000000 + 16930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } + 16930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 16930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 16930 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 16930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 16930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca } +calling cycle +calling cycle + 16950 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 16950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca } + 16950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca } + 16950 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 16950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 16960 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: } } +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 17030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 0000000000000002800000001fffff44000000 + 17040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7a <= 000000002000002c000000001fffff44000000 + 17050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7b <= 000000002000002e000000001fffff44000000 + 17060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 17060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7c <= 00000000200003bc000000001fffff44000000 + 17070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } + 17070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 17070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7f <= 00000000200003cc000000001fffff44000000 + 17080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 17080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } + 17080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + 17080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 17090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 17090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: True, capStore: False, potentialCapLoad: False } + 17090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 17090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 17100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } + 17100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + 17100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 17110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False } + 17110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef0 +After delta: vaddr = 0x80000ef0 + 17110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17120 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000ef0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 17120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 17120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True } + 17120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 17120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 17120 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 17120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 17120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17130 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 17130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17130 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 0a <= 4000000000000000000000001fffff44000000 + 17130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } + 17130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17130 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 17130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17130 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 17130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 17130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 17130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 17140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 17140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 17140 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: } } + 17140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } + 17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17140 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } + 17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 02 <= 00000000200003cc000000001fffff44000000 + 17150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 17150 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17150 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17150 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } + 17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17160 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 17160 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 43 <= 4000000000000000000000001fffff44000000 + 17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + 17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa } + 17160 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 17170 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 78 <= 40000000200005081420ffff1ffff805081420 + 17170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 17180 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 000000002000002e000000001fffff44000000 + 17180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 17180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 17190 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 17190 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000 + 17190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001420 o: 'h0000000000000000 b: 'h0000000080001420 t: 'h00000000080001420 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: True, potentialCapLoad: True } +instret:56 PC:0x1ffff00000000000000000000800000aa instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 1719 +instret:57 PC:0x1ffff00000000000000000000800000ae instr:0x000045a9 iType:Alu [doCommitNormalInst [1]] 1719 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 17200 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 00000000200003e8000000001fffff44000000 +instret:58 PC:0x1ffff00000000000000000000800000b0 instr:0x00000097 iType:Auipc [doCommitNormalInst [0]] 1720 +instret:59 PC:0x1ffff00000000000000000000800000b4 instr:0x032080e7 iType:Jr [doCommitNormalInst [1]] 1720 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef0 +After delta: vaddr = 0x80000ef0 + 17210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:60 PC:0x1ffff00000000000000000000800000e2 instr:0x00007139 iType:Alu [doCommitNormalInst [0]] 1721 +instret:61 PC:0x1ffff00000000000000000000800000e4 instr:0x0000fc06 iType:St [doCommitNormalInst [1]] 1721 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 44 <= 4000014000000000000000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80e4 } + 17220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050000000000 o: 'h0000050000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: True, capStore: True, potentialCapLoad: True } + 17220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 17220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 } +instret:62 PC:0x1ffff00000000000000000000800000e6 instr:0x0000f822 iType:St [doCommitNormalInst [0]] 1722 +instret:63 PC:0x1ffff00000000000000000000800000e8 instr:0x00000080 iType:Alu [doCommitNormalInst [1]] 1722 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 17230 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 17230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } + 17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 } + 17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 17230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:64 PC:0x1ffff00000000000000000000800000ea instr:0xfea44023 iType:St [doCommitNormalInst [0]] 1723 +instret:65 PC:0x1ffff00000000000000000000800000ee instr:0xfcb42e23 iType:St [doCommitNormalInst [1]] 1723 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f0c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80e6 } + 17240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } + 17240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 17240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } +calling cycle + 17250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 } +calling cycle + 17260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 17260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 17260 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 17260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 17270 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 17270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 } + 17270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80ea } + 17280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea } +calling cycle + 17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea } + 17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f0c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80ee } + 17300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f0c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } +calling cycle + 17310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f0c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } + 17310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f0c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 17330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 17340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } + 17340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f0c +After delta: vaddr = 0x80000f0c + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 17350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False } + 17350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } + 17360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess , pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 17360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } + 17360 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 17360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef0 +After delta: vaddr = 0x80000ef0 + 17360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f0c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17370 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 0a <= 40000000200005081420ffff1ffff805081420 + 17370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True } + 17370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f0c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f6 } + 17370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f0c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f6 } + 17370 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } + 17370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 17370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 17380 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 17380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17380 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000 + 17380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } + 17380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 17380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f0c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 17390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } + 17390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17390 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } + 17390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } +instret:66 PC:0x1ffff00000000000000000000800000f2 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1739 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 02 <= 00000000200003cc000000001fffff44000000 + 17400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 17400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17400 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 43 <= 4000000000000000000000001fffff44000000 + 17400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } + 17400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } + 17400 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 17400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef0 +After delta: vaddr = 0x80000ef0 + 17400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } +instret:67 PC:0x1ffff00000000000000000000800000f6 instr:0xfdc42583 iType:Ld [doCommitNormalInst [0]] 1740 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 44 <= 40000140200005081420ffff1ffff805081420 + 17410 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 000000002000002e000000001fffff44000000 + 17410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050080001420 o: 'h0000000000000000 b: 'h0000050080001420 t: 'h00000050080001420 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: True, capStore: True, potentialCapLoad: True } + 17410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } + 17410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } + 17410 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 17410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17420 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 17420 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 00000000200003e8000000001fffff44000000 + 17420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:68 PC:0x1ffff00000000000000000000800000fa instr:0x1ab5055b iType:Cap [doCommitNormalInst [0]] 1742 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 49 <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 4a <= 0000000000000000000000001fffff44000000 + 17430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x00000000 +After delta: vaddr = 0x00000000 + 17430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:69 PC:0x1ffff00000000000000000000800000fe instr:0xfca44023 iType:St [doCommitNormalInst [0]] 1743 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4d <= 0000000000000000400000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000ef0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } +[ALU redirect - 0] 'h1ffff00000000000000000000800000b8; 'h0; InstTag { way: 'h0, ptr: 'h04, t: 'h08 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ef0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80fe } + 17440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000000000, write: True, capStore: False, potentialCapLoad: False } + 17440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 17440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000ef0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h04, t: 'h08 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000ef0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000ef0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef0 +After delta: vaddr = 0x80000ef0 + 17550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True } + 17560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 17560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17570 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 17570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } + 17570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 17570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } +calling cycle + 17580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 17580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } + 17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } + 17580 : [Ld resp] 'h15; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } + 17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } +calling cycle +[RFile] wr_ 1: r 02 <= 00000000200003cc000000001fffff44000000 + 17590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 17590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17590 : [doRespLdMem] 'h15; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 43 <= 40000140200005081420ffff1ffff805081420 + 17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } + 17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 } + 17590 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000ef0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 17600 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 000000002000002e000000001fffff44000000 + 17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } + 17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 } + 17600 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17610 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 00000000200003e8000000001fffff44000000 +instret:70 PC:0x1ffff0000000000000000000080000102 instr:0xfc04250f iType:Ld [doCommitNormalInst [0]] 1761 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:71 PC:0x1ffff0000000000000000000080000106 instr:0x000070e2 iType:Ld [doCommitNormalInst [0]] 1762 +calling cycle +[ALU redirect - 1] 'h1ffff00000000000000000000800000b8; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } +instret:72 PC:0x1ffff0000000000000000000080000108 instr:0x00007442 iType:Ld [doCommitNormalInst [0]] 1763 +instret:73 PC:0x1ffff000000000000000000008000010a instr:0x00006121 iType:Alu [doCommitNormalInst [1]] 1763 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:74 PC:0x1ffff000000000000000000008000010c instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 1765 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 17720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } + 17730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 17730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 17740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050080001420 o: 'h0000000000000000 b: 'h0000050080001420 t: 'h00000050080001420 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } + 17740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 17740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 17750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 17750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 17750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 17750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 17750 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 17750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 17760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h80c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17760 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 0000000020000506000000001fffff44000000 + 17760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 17770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 17770 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 17770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001418 +After delta: vaddr = 0x80001418 + 17770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17780 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 0000000000000000000000001fffff44000000 + 17780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001418, write: False, capStore: False, potentialCapLoad: False } + 17780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 17780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:75 PC:0x1ffff00000000000000000000800000b8 instr:0xf9843583 iType:Ld [doCommitNormalInst [0]] 1778 +instret:76 PC:0x1ffff00000000000000000000800000bc instr:0xfaa44023 iType:St [doCommitNormalInst [1]] 1778 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17790 : [doFinishMem] DTlbResp { resp: <'h0000000080001418,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001418, check_high: 'h00000000080001420, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80bc } + 17790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080001418, shiftedBE: tagged DataMemAccess , pcHash: 'h80c4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } + 17790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 17790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080001418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 17800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 17800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } + 17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080001418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } + 17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080001418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 } + 17800 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } + 17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 17800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } +instret:77 PC:0x1ffff00000000000000000000800000c0 instr:0xfd843603 iType:Ld [doCommitNormalInst [0]] 1780 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 17810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 17810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h80d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17810 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4e <= 0000000000000000000000001fffff44000000 + 17810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } + 17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 17810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080001418, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 17820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h80da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17820 : [doRespLdForward] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 51 <= 40000140200005081420ffff1ffff805081420 + 17820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } + 17820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } + 17820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } + 17820 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } + 17820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } +calling cycle +[RFile] wr_ 0: r 4f <= 00000000200003e8000000001fffff44000000 + 17830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 17830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h80dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17830 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4c <= 0000000000000000000000001fffff44000000 + 17830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + 17830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + 17830 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } + 17830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 17830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } +instret:78 PC:0x1ffff00000000000000000000800000c4 instr:0x00006188 iType:Ld [doCommitNormalInst [0]] 1783 +calling cycle +[RFile] wr_ 1: r 08 <= 0000000000000000000000001fffff44000000 + 17840 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 55 <= 00000000200000cf000000001fffff44000000 + 17840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050080001420 o: 'h0000000000000000 b: 'h0000050080001420 t: 'h00000050080001420 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: True, potentialCapLoad: True } + 17840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 17840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 17840 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } + 17840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001418 +After delta: vaddr = 0x80001418 +calling cycle + 17850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 17850 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 56 <= 0000000020000400000000001fffff44000000 + 17850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001418, write: True, capStore: False, potentialCapLoad: False } +instret:79 PC:0x1ffff00000000000000000000800000c6 instr:0x00009532 iType:Alu [doCommitNormalInst [0]] 1785 +calling cycle + 17860 : [doFinishMem] DTlbResp { resp: <'h0000000080001418,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001418, check_high: 'h00000000080001420, check_inclusive: True } }, specBits: 'h000 } +calling cycle +[ALU redirect - 0] 'h1ffff000000000000000000008000033c; 'h1; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } +instret:80 PC:0x1ffff00000000000000000000800000c8 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 1787 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001418, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80c8 } + 17880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001418, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c8 } +[ROB incorrectSpec] 'h1 ; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001418, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c8 } + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001418, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c8 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +instret:81 PC:0x1ffff00000000000000000000800000ca instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 1790 +instret:82 PC:0x1ffff00000000000000000000800000ce instr:0xfea44023 iType:St [doCommitNormalInst [1]] 1790 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80ce } + 17910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ce } +instret:83 PC:0x1ffff00000000000000000000800000d2 instr:0x0040006f iType:J [doCommitNormalInst [0]] 1791 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 17920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ce } + 17920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ce } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 17920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 18010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } + 18020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 18020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 18030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 18030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h80d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 18030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 18030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } +calling cycle + 18040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 18040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h80da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } + 18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } + 18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 } + 18040 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } + 18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } +calling cycle +[RFile] wr_ 1: r 4f <= 00000000200003e8000000001fffff44000000 + 18050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 18050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h80dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18050 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 4c <= 40000140200005081420ffff1ffff805081420 + 18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + 18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da } + 18050 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } + 18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 18060 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 55 <= 00000000200000cf000000001fffff44000000 + 18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc } + 18060 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } + 18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 18070 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 56 <= 0000000020000400000000001fffff44000000 +instret:84 PC:0x1ffff00000000000000000000800000d6 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1807 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:85 PC:0x1ffff00000000000000000000800000da instr:0x000070a6 iType:Ld [doCommitNormalInst [0]] 1808 +calling cycle +[ALU redirect - 1] 'h1ffff000000000000000000008000033c; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } +instret:86 PC:0x1ffff00000000000000000000800000dc instr:0x00007406 iType:Ld [doCommitNormalInst [0]] 1809 +instret:87 PC:0x1ffff00000000000000000000800000de instr:0x00006165 iType:Alu [doCommitNormalInst [1]] 1809 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:88 PC:0x1ffff00000000000000000000800000e0 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 1811 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000050 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd0 +After delta: vaddr = 0x80000fd0 + 18180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000001d }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050080001420 o: 'h0000000000000000 b: 'h0000050080001420 t: 'h00000050080001420 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: True, capStore: True, potentialCapLoad: True } + 18190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc8 +After delta: vaddr = 0x80000fc8 + 18190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h1a9 }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 59 <= 0000000000000014000000001fffff44000000 + 18200 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 18200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000050 o: 'h0000000000000050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc8, write: True, capStore: False, potentialCapLoad: False } + 18200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc8 +After delta: vaddr = 0x80000fc8 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000a2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18210 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc8, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h000 } + 18210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc8, write: False, capStore: False, potentialCapLoad: False } +instret:89 PC:0x1ffff000000000000000000008000033c instr:0xfca44823 iType:St [doCommitNormalInst [0]] 1821 +instret:90 PC:0x1ffff0000000000000000000080000340 instr:0x05000513 iType:Alu [doCommitNormalInst [1]] 1821 +calling cycle +[RFile] wr_ 0: r 5d <= 0000000000000007400000001fffff44000000 + 18220 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc8, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h833c } + 18220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000fc8, shiftedBE: tagged DataMemAccess , pcHash: 'h834c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 18220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +instret:91 PC:0x1ffff0000000000000000000080000344 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 1822 +instret:92 PC:0x1ffff0000000000000000000080000348 instr:0x0040006f iType:J [doCommitNormalInst [1]] 1822 +calling cycle + 18230 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000000000014000000001fffff44000000 + 18230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } + 18230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 18230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000fc8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fc8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8344 } + 18240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } +calling cycle + 18250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } + 18250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 18250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:93 PC:0x1ffff000000000000000000008000034c instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 1825 +instret:94 PC:0x1ffff0000000000000000000080000350 instr:0x00004575 iType:Alu [doCommitNormalInst [1]] 1825 +calling cycle +calling cycle +instret:95 PC:0x1ffff0000000000000000000080000352 instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 1827 +instret:96 PC:0x1ffff0000000000000000000080000356 instr:0x0a20006f iType:J [doCommitNormalInst [1]] 1827 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd0 +After delta: vaddr = 0x80000fd0 +calling cycle + 18760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: False, capStore: False, potentialCapLoad: True } +calling cycle +[RFile] wr_ 1: r 60 <= 00000000200000ff000000001fffff44000000 + 18770 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 18770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000fd0, shiftedBE: tagged DataMemAccess , pcHash: 'h83f8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83f8 } +calling cycle + 18780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83f8 } + 18780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h83f8 } + 18780 : [Ld resp] 'h0a; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } + 18780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 18790 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 5f <= 40000140200005081420ffff1ffff805081420 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } +calling cycle +instret:97 PC:0x1ffff00000000000000000000800003f8 instr:0xfd04250f iType:Ld [doCommitNormalInst [0]] 1881 +instret:98 PC:0x1ffff00000000000000000000800003fc instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1881 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffd2e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle +[RFile] wr_ 1: r 62 <= 0000000020000101000000001fffff44000000 +[ALU redirect - 1] 'h1ffff000000000000000000008000012a; 'h0; InstTag { way: 'h1, ptr: 'h07, t: 'h0f } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h07, t: 'h0f } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:99 PC:0x1ffff0000000000000000000080000400 instr:0xd2e080e7 iType:Jr [doCommitNormalInst [0]] 1910 +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 19170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 64 <= 00000000200003dc000000001fffff44000000 + 19180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000404 o: 'h0000000080000404 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } + 19180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 19180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 67 <= 00000000200003e8000000001fffff44000000 + 19190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 19190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } + 19190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 19190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:100 PC:0x1ffff000000000000000000008000012a instr:0x00007179 iType:Alu [doCommitNormalInst [0]] 1919 +calling cycle + 19200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 19200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050080001420 o: 'h0000000000000000 b: 'h0000050080001420 t: 'h00000050080001420 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: True, potentialCapLoad: True } + 19200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 +instret:101 PC:0x1ffff000000000000000000008000012c instr:0x0000f406 iType:St [doCommitNormalInst [0]] 1920 +calling cycle +[RFile] wr_ 0: r 6a <= 0000000000000000000000001fffff44000000 + 19210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h812c } + 19210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } + 19210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812c } +instret:102 PC:0x1ffff000000000000000000008000012e instr:0x0000f022 iType:St [doCommitNormalInst [0]] 1921 +instret:103 PC:0x1ffff0000000000000000000080000130 instr:0x00001800 iType:Alu [doCommitNormalInst [1]] 1921 +calling cycle + 19220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 19220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h8136 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 19220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812c } + 19220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812c } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 19220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:104 PC:0x1ffff0000000000000000000080000132 instr:0xfea44023 iType:St [doCommitNormalInst [0]] 1922 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h812e } + 19230 : [doRespLdForward] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 68 <= 40000140200005081420ffff1ffff805081420 + 19230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812e } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 19240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812e } + 19240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812e } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 19240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8132 } + 19250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8132 } +instret:105 PC:0x1ffff0000000000000000000080000136 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1925 +instret:106 PC:0x1ffff000000000000000000008000013a instr:0xfea005db iType:Cap [doCommitNormalInst [1]] 1925 +calling cycle + 19260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8132 } + 19260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8132 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 19260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h09f }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:107 PC:0x1ffff000000000000000000008000013e instr:0x00b50463 iType:Br [doCommitNormalInst [0]] 1972 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 19730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 +instret:108 PC:0x1ffff0000000000000000000080000142 instr:0x00c0006f iType:J [doCommitNormalInst [0]] 1973 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapInspect GetLen, capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } + 19740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 19750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 19750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h814e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 19750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h814e } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } + 19760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h814e } + 19760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h814e } + 19760 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } + 19760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 19770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h8158 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19770 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 6c <= 40000140200005081420ffff1ffff805081420 + 19770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 19770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8158 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002aa }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 19780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 19780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8158 } + 19780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8158 } + 19780 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 19780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 + 19780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 19790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 19790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8164 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19790 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 6e <= 40000140200005081420ffff1ffff805081420 + 19790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: False, capStore: False, potentialCapLoad: False } + 19790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 19790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } +instret:109 PC:0x1ffff000000000000000000008000014e instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1979 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002a8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6d <= 0000014020000508000000001fffff44000000 + 19800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f78, check_inclusive: True } }, specBits: 'h000 } + 19800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f70, shiftedBE: tagged DataMemAccess , pcHash: 'h8168 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000050080001420 o: 'h0000050080001420 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } + 19800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } + 19800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } + 19800 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } + 19800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 } +calling cycle +[RFile] wr_ 1: r 74 <= 000000002000045b800000001fffff44000000 + 19810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 19810 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000000000000000000000001fffff44000000 + 19810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 } + 19810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 } + 19810 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } + 19810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 + 19810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:110 PC:0x1ffff0000000000000000000080000152 instr:0x0000852a iType:Alu [doCommitNormalInst [0]] 1981 +calling cycle +[RFile] wr_ 0: r 6b <= 0000000000000000000000001fffff44000000 + 19820 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 72 <= 0000000000000000000000001fffff44000000 + 19820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: True, capStore: False, potentialCapLoad: False } + 19820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001418 +After delta: vaddr = 0x80001418 +instret:111 PC:0x1ffff0000000000000000000080000154 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1982 +calling cycle +[RFile] wr_ 0: r 77 <= 0000000020000506000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 19830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f78, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8154 } + 19830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001418, write: False, capStore: False, potentialCapLoad: False } + 19830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8154 } +calling cycle +[RFile] wr_ 0: r 75 <= 000000002000045e000000001fffff44000000 + 19840 : [doFinishMem] DTlbResp { resp: <'h0000000080001418,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001418, check_high: 'h00000000080001420, check_inclusive: True } }, specBits: 'h000 } + 19840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080001418, shiftedBE: tagged DataMemAccess , pcHash: 'h8176 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8154 } + 19840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8154 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 19840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080001418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 } +instret:112 PC:0x1ffff0000000000000000000080000158 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1984 +instret:113 PC:0x1ffff000000000000000000008000015c instr:0xfe35055b iType:Cap [doCommitNormalInst [1]] 1984 +calling cycle +[RFile] wr_ 1: r 71 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 19850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080001418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 } + 19850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080001418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 } + 19850 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 19850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:114 PC:0x1ffff0000000000000000000080000160 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 1985 +calling cycle +[RFile] wr_ 1: r 53 <= 0000000020000508000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8160 } + 19860 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000000000000001fffff44000000 + 19860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8160 } +calling cycle +calling cycle + 19880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8160 } + 19880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8160 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 19880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 20330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002aa }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } + 20340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 20350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 20350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8164 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: False, capStore: False, potentialCapLoad: False } + 20350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002a8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 20360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f78, check_inclusive: True } }, specBits: 'h000 } + 20360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f70, shiftedBE: tagged DataMemAccess , pcHash: 'h8168 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } + 20360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } + 20360 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } + 20360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 20360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h0c2 }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 74 <= 000000002000045b800000001fffff44000000 + 20370 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000014020000508000000001fffff44000000 + 20370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 } + 20370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 } + 20370 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } + 20370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001418 +After delta: vaddr = 0x80001418 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000001e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 77 <= 0000000020000506000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20380 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 72 <= 0000000000000000000000001fffff44000000 + 20380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001418, write: False, capStore: False, potentialCapLoad: False } +calling cycle +[RFile] wr_ 0: r 75 <= 000000002000045e000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20390 : [doFinishMem] DTlbResp { resp: <'h0000000080001418,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001418 o: 'h0000000080001418 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001418, check_high: 'h00000000080001420, check_inclusive: True } }, specBits: 'h000 } + 20390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080001418, shiftedBE: tagged DataMemAccess , pcHash: 'h8176 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080001418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 } +instret:115 PC:0x1ffff0000000000000000000080000164 instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2039 +calling cycle +[RFile] wr_ 0: r 53 <= 0000000020000508000000001fffff44000000 + 20400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080001418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 } + 20400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080001418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 } + 20400 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 20400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:116 PC:0x1ffff0000000000000000000080000168 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 2040 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 71 <= 0000014020000508000000001fffff44000000 + 20410 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000000000000001fffff44000000 + 20410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080001418, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 20420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:117 PC:0x1ffff000000000000000000008000016c instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 2042 +instret:118 PC:0x1ffff000000000000000000008000016e instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2042 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 20430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } + 20430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 +instret:119 PC:0x1ffff0000000000000000000080000172 instr:0x2aa58593 iType:Alu [doCommitNormalInst [0]] 2043 +instret:120 PC:0x1ffff0000000000000000000080000176 instr:0x00006190 iType:Ld [doCommitNormalInst [1]] 2043 +calling cycle +[RFile] wr_ 1: r 7a <= 0000000020000508000000001fffff44000000 + 20440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h001 } + 20440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } + 20440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a4 } +instret:121 PC:0x1ffff0000000000000000000080000178 instr:0x00001597 iType:Auipc [doCommitNormalInst [0]] 2044 +instret:122 PC:0x1ffff000000000000000000008000017c instr:0x2a858593 iType:Alu [doCommitNormalInst [1]] 2044 +calling cycle +[RFile] wr_ 0: r 05 <= 00000000200003e8000000001fffff44000000 + 20450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h001 } + 20450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h81a6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a4 } + 20450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a4 } + 20450 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } + 20450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a6 } +instret:123 PC:0x1ffff0000000000000000000080000180 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 2045 +calling cycle + 20460 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7e <= 0000000020000101000000001fffff44000000 + 20460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a6 } + 20460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a6 } + 20460 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } + 20460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:124 PC:0x1ffff0000000000000000000080000182 instr:0x00b50463 iType:Br [doCommitNormalInst [0]] 2046 +instret:125 PC:0x1ffff0000000000000000000080000186 instr:0x01e0006f iType:J [doCommitNormalInst [1]] 2046 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20470 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 57 <= 0000000020000400000000001fffff44000000 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:126 PC:0x1ffff00000000000000000000800001a4 instr:0x000070a2 iType:Ld [doCommitNormalInst [0]] 2048 +calling cycle +instret:127 PC:0x1ffff00000000000000000000800001a6 instr:0x00007402 iType:Ld [doCommitNormalInst [0]] 2049 +instret:128 PC:0x1ffff00000000000000000000800001a8 instr:0x00006145 iType:Alu [doCommitNormalInst [1]] 2049 +calling cycle +instret:129 PC:0x1ffff00000000000000000000800001aa instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2050 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd0 +After delta: vaddr = 0x80000fd0 + 20980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 78 <= 0000000000000000000000001fffff44000000 + 20990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: True, capStore: False, potentialCapLoad: True } + 20990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff8 +After delta: vaddr = 0x80000ff8 + 20990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0a <= 0000000000000000000000001fffff44000000 + 21000 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 21000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } + 21000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff0 +After delta: vaddr = 0x80000ff0 +instret:130 PC:0x1ffff0000000000000000000080000404 instr:0xfea0055b iType:Cap [doCommitNormalInst [0]] 2100 +calling cycle +[RFile] wr_ 0: r 7b <= 0000000020000400000000001fffff44000000 + 21010 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } + 21010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h840e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } + 21010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h840e } +instret:131 PC:0x1ffff0000000000000000000080000408 instr:0xfca44823 iType:St [doCommitNormalInst [0]] 2101 +instret:132 PC:0x1ffff000000000000000000008000040c instr:0x00004501 iType:Alu [doCommitNormalInst [1]] 2101 +calling cycle + 21020 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8408 } + 21020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h8410 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h840e } + 21020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h840e } + 21020 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 21020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8410 } +calling cycle + 21030 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000020000006000000001fffff44000000 + 21030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8410 } + 21030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8410 } + 21030 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 21030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8408 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000ff8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21040 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000000000000000000001fffff44000000 + 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8408 } + 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8408 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000ff0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:133 PC:0x1ffff000000000000000000008000040e instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2105 +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000018; 'h0; InstTag { way: 'h1, ptr: 'h0a, t: 'h15 } +instret:134 PC:0x1ffff0000000000000000000080000410 instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2106 +instret:135 PC:0x1ffff0000000000000000000080000412 instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2106 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h0a, t: 'h15 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +instret:136 PC:0x1ffff0000000000000000000080000414 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2108 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 21160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 45 <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 7c <= 0000000000000000000000001fffff44000000 + 21170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x00000000 +After delta: vaddr = 0x00000000 + 21170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 40 <= 0000000000000000400000001fffff44000000 + 21180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000000000, write: True, capStore: False, potentialCapLoad: False } + 21180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff8 +After delta: vaddr = 0x80000ff8 + 21180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:137 PC:0x1ffff0000000000000000000080000018 instr:0x0000832a iType:Alu [doCommitNormalInst [0]] 2118 +instret:138 PC:0x1ffff000000000000000000008000001a instr:0x00004281 iType:Alu [doCommitNormalInst [1]] 2118 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0c <= 00000000200003e4000000001fffff44000000 + 21190 : [doFinishMem] DTlbResp { resp: <'h0000000000000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000000000, check_high: 'h00000000000000008, check_inclusive: True } }, specBits: 'h000 } + 21190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000018 o: 'h0000000080000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: True, capStore: False, potentialCapLoad: False } + 21190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff0 +After delta: vaddr = 0x80000ff0 + 21190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:139 PC:0x1ffff000000000000000000008000001c instr:0x00004305 iType:Alu [doCommitNormalInst [0]] 2119 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 42 <= 0000000020000400000000001fffff44000000 + 21200 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } + 21200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: True, capStore: False, potentialCapLoad: False } + 21200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd8 +After delta: vaddr = 0x80000fd8 + 21200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000003de }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 21210 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_MMIO_issue] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000000000000, isMMIO: True, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h801e }; MMIOCRq { addr: 'h0000000000000000, func: tagged St , byteEn: , data: TaggedData { tag: False, data: }, loadTags: False } + 21210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd8, write: True, capStore: False, potentialCapLoad: False } + 21210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd8 +After delta: vaddr = 0x80000fd8 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 21220 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd8, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 21220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd8, write: False, capStore: False, potentialCapLoad: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21230 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd8, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 21230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000fd8, shiftedBE: tagged DataMemAccess , pcHash: 'h802e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 21230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00010000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 47 <= 000000002000040e800000001fffff44000000 + 21240 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4b <= 0000000000000000000000001fffff44000000 + 21240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001418 +After delta: vaddr = 0x80001418 + 21240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: False, localTaken: False, pcIndex: 'h027 }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +2125: mmioPlatform.rl_tohost: 0x1 (= 1) +PASS